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PD Design 3

The document discusses various aspects of physical verification for VLSI chip design such as design rule checking (DRC), layout vs schematic (LVS) checking, and parasitic extraction. It covers terminology, different design rules for layers like nWell and active, differences between flat and hierarchical checking, how to run DRC and LVS tools, and extracting parasitic resistances and capacitances. The document appears to be notes from a training session on key signoff checks for VLSI chip design.

Uploaded by

Kanhaiya Mishra

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© Attribution Non-Commercial (BY-NC)

We take content rights seriously. If you suspect this is your content, claim it here.

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0% found this document useful (0 votes)

131 views26 pages

PD Design 3

The document discusses various aspects of physical verification for VLSI chip design such as design rule checking (DRC), layout vs schematic (LVS) checking, and parasitic extraction. It covers terminology, different design rules for layers like nWell and active, differences between flat and hierarchical checking, how to run DRC and LVS tools, and extracting parasitic resistances and capacitances. The document appears to be notes from a training session on key signoff checks for VLSI chip design.

Uploaded by

Kanhaiya Mishra

Copyright

© Attribution Non-Commercial (BY-NC)

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

You are on page 1/ 26

PHYSICALVERIFICATION VENKATESHPRASAD

DAY3

01/07/09

CUSTOMFLOW

Ph:08040788574

www.rvvlsi.com
RVVLSIConfidential

TERMINOLOGY

Ph:08040788574

www.rvvlsi.com
RVVLSIConfidential

DRC

Ph:08040788574

www.rvvlsi.com
RVVLSIConfidential

DESIGNRULECHECK

Ph:08040788574

www.rvvlsi.com
RVVLSIConfidential

DESIGNRULES

y z z

Ph:08040788574

www.rvvlsi.com
RVVLSIConfidential

DESIGNRULES

1.Minimumwidth(x) 2.Minimumspacing(y) 3.Minimumenclosure(z)

Ph:08040788574

www.rvvlsi.com
RVVLSIConfidential

FLATversusHIERARCHICAL

Ph:08040788574

www.rvvlsi.com
RVVLSIConfidential

THEMOMENTOFUSINGHIERARCHICAL DRCCHECK

Ph:08040788574

www.rvvlsi.com
RVVLSIConfidential

RUNNINGCALIBREDRC

Ph:08040788574

www.rvvlsi.com
RVVLSIConfidential

10

DESIGNRULES:nWELL

Ph:08040788574

www.rvvlsi.com
RVVLSIConfidential

11

DESIGNRULES:ACTIVE

Ph:08040788574

www.rvvlsi.com
RVVLSIConfidential

12

DESIGNRULES:N+andP+

Ph:08040788574

www.rvvlsi.com
RVVLSIConfidential

13

DESIGNRULES:POLY

Ph:08040788574

www.rvvlsi.com
RVVLSIConfidential

14

DESIGNRULES:POLYandCONTACT

Ph:08040788574

www.rvvlsi.com
RVVLSIConfidential

15

DESIGNRULES:METAL1

Ph:08040788574

www.rvvlsi.com
RVVLSIConfidential

16

DESIGNRULES:CONTACTOVERLAP

Ph:08040788574

www.rvvlsi.com
RVVLSIConfidential

17

DESIGNRULES:VIA1

Ph:08040788574

www.rvvlsi.com
RVVLSIConfidential

18

LVS

Ph:08040788574

www.rvvlsi.com
RVVLSIConfidential

19

LAYOUTversusSCHEMATIC

Ph:08040788574

www.rvvlsi.com
RVVLSIConfidential

20

FLATversusHIERARCHICAL

Ph:08040788574

www.rvvlsi.com
RVVLSIConfidential

21

OPENSandSHORTS

Ph:08040788574

www.rvvlsi.com
RVVLSIConfidential

22

EXTRACTINGDEVICES

Ph:08040788574

www.rvvlsi.com
RVVLSIConfidential

23

LAYOUTversusSCHEMATIC

Ph:08040788574

www.rvvlsi.com
RVVLSIConfidential

24

PARASITICEXTRACTION/EXTRACTRC

Ph:08040788574

www.rvvlsi.com
RVVLSIConfidential

25

Done

Ph:08040788574

www.rvvlsi.com
RVVLSIConfidential

26

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