Low-Cost Anti-Tamper Technology: MITRE Sponsored Research
Low-Cost Anti-Tamper Technology: MITRE Sponsored Research
Brian Faull, E536 (781) 271 5736 - bfaull@mitre.org Richard Pietravalle, G026 (781) 271 7994 - rpietravalle@mitre.org
Problem
Traditional anti-tamper (AT) techniques for large systems are not feasible to use in smaller systems Need better low-cost approaches for protecting information in low-end embedded systems
2008 The MITRE Corporation. All rights reserved.
Background
Protection/Cost Tradeoffs
Objective
Activities
Investigate current methods and strategies for protecting low-end systems and components Engage in dialog with private sector and academia Investigate characteristics of current methods in the laboratory Identify new techniques or extensions to current methods that hold promise for acceptable cost/protection tradeoffs
Highlight
Tamper Methods
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Fault induction
protocol attack, glitching (force test / failure mode), flip bits with X-Ray, change FW / SW,
Modify hardware
cut traces,
flip bits with light / FIB, damage circuit,
Active
Passive
differential power analysis [DPA], Electromagnetic [EM] signature, probe interface signals, disassemble/RE SW, FW, HW
Non-invasive
Invasive
$$$$
Demonstration
Power Side-Channel Analysis
Green, peaks: Correct hypothesis
Incorrect hypotheses
Correct hypothesis
Impacts
More effective protection for intelligent field devices Improved cost characteristics for current devices needed for widespread deployment
Increased dialog with the information and system protection community on new methods of protection Increased flow of expertise and product to government sponsors from the private sector
Future Plans
Vulnerabilities, goals and adversaries Anti-tamper techniques Conventional tamper techniques