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This document analyzes crosstalk coupling effects between interconnect lines using a two-port network model. It develops an ABCD matrix model to represent the capacitive coupling between an aggressor and victim interconnect line. The model accounts for different signal combinations on the lines and derives expressions for the output voltage and current on the victim line. Simulation results using the reduced order crosstalk model can estimate signal delays, overshoots and undershoots caused by crosstalk coupling.

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0% found this document useful (0 votes)
55 views4 pages

10 1 1 142 103 PDF

This document analyzes crosstalk coupling effects between interconnect lines using a two-port network model. It develops an ABCD matrix model to represent the capacitive coupling between an aggressor and victim interconnect line. The model accounts for different signal combinations on the lines and derives expressions for the output voltage and current on the victim line. Simulation results using the reduced order crosstalk model can estimate signal delays, overshoots and undershoots caused by crosstalk coupling.

Uploaded by

Rajeev Pandey
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Analysis of Crosstalk Coupling Effects between Aggressor and Victim Interconnect Using Two-Port

Network Model
Ajoy K. Palit, Volker Meyer, Walter Anheier and Juergen Schloeffel
Institute of Electromagnetic Theory and Microelectronics, University of Bremen,
Otto-Hahn-Allee-NW1, D-28359 Bremen, Germany
Fax:+49-421-2184434, E-mails:{palit|anheier}@item.uni-bremen.de
Philips Semiconductors GmbH, Design Technology Center,
Georg-Heyken-Strasse-1, D-21147 Hamburg, Germany.
E-mail: juergen.schloeffel@philips.com
Abstract
Signal Integrity (SI) losses in the interconnects are the
disturbances coming out of their distributed nature of parasitic
capacitances, resistances, and inductances at high frequency
operation [1]. SI losses are further aggravated if multiple
interconnect lines couple energy from, or to each other.
Therefore, this paper aims to analyze the cross-talk coupling
effects between the two interconnects, namely the aggressor
and victim lines, using the ABCD two-port network model. In
order to reduce the simulation time a reduced order modeling
of the interconnect line is considered. Furthermore, as stated
in various literatures [7] the rising (or falling) input signal
represented by a simple step function is not accurate enough,
therefore in this paper the rising transitions and the falling
transitions are represented more accurately using the
exponential terms, and based on such input representation the
time domain output signal voltage in presence of crosstalk
noise, at the far end side of both aggressor line and victim
line, is determined. Such output voltage representation is very
helpful in estimating the delay, overshoot or undershoot etc.,
which are believed to cause SI losses in the SoC.
1. Introduction
With the continuous increase in signal switching speed
and higher density of integrated circuits the system designers
and test engineers are currently confronted with new
challenging problems. The interconnect lines that were in the
past considered to be electrically isolated, can now interfere
with each other and have serious impact on the system
performance and its correct functionality. One such
interaction caused by parasitic coupling between the
interconnect wires is known as crosstalk [3]. In general, the
term crosstalk that is defined as the leakage of any signal from
one conductor to another, can be induced through three
coupling mechanisms: capacitive, inductive and radiative [8].
Radiative coupling is essentially a self induced EMI
disturbance and should be treated within an EMI design
framework. Crosstalk may cause undesirable effects including
excessive overshoot, undershoot, glitch, additional signal
delay and even in reduction in signal delay (speed-up of
signal) etc. Crosstalk can produce logic errors in the circuits.
Current trends in integrated circuit design indicate that signal
noise and skew due to crosstalk creates severe design and test
problems. Therefore, in this paper an attempt has been made
to analyze the crosstalk coupling effect between two
interconnect wires, namely the aggressor and a victim line,
that is presented in section-2, using a simple ABCD two-port
network model. Furthermore, in order to improve the
simulation performance the derived final crosstalk model
undergoes order reduction, as presented in Section-3, and
based on such reduced order model the time domain response
or the output signal voltages, at the far end side of the victim,
is determined. Thereafter, the estimation of the signal delay,
overshoot and undershoot etc. that are believed to cause signal
integrity losses in system on chip (SoC), is presented in
section-4 and the simulation result is presented in section-5.
Finally, section-6 presents brief concluding remarks.
2. Crosstalk Coupling
This section is concerned with the capacitive coupling
between an aggressor and a victim line. Capacitive coupling is
initially considered in this paper as because the effect of
inductive coupling becomes significantly strong only when
the operating frequencies of the SoCs are in several GHz
range. Furthermore, the coupling is assumed to be a weak
coupling implying that, only the active (aggressor) line will
continuously leak certain amount of displacement current to
the passive (victim) line, whereas, the reverse case is not
allowed. In the following the crosstalk model is developed
strictly based on the consideration of a single aggressor and a
victim line only. Justification for using such a model is
explained by the maximal aggressor fault (MAF) model [4],
where multiple aggressor lines, with simultaneous
(synchronized) identical rising transitions at the near end of
each aggressor line, but with only one victim line with
opposite / quiescent signal at its near end are considered.
Because of identical simultaneous (synchronized) rising
transition on each aggressor line the cross-talk noise (due to
coupling capacitance / mutual inductance) between any two
aggressors will be zero, whereas all aggressors couple energy
to the victim line through their individual coupling
capacitances / mutual inductances. The above situation is
equivalent to a single aggressor and a single victim model but
with resulting coupling capacitance / mutual inductance equal
to sum of all coupling capacitances / reciprocal of sum of
reciprocal of mutual inductances between the individual
aggressor and the victim line respectively. Furthermore, cross-
talk model of an aggressor and victim line is developed in the
subsection-2.1 based on the ABCD model (two-port network)
of long interconnect as described in the appendix of [6].
2.1. Development of Crosstalk ABCD Model
Referring to the fig.-1 and considering the first part ( x
segment, i.e., first ABCD block) of the victim (bottom) line
Fig.-1: Crosstalk Modeling of an aggressor and victim line
(before the coupling capacitance
c
c x ) the input-output
voltage and current can be written using the ABCD model as:
( )
( )
( )
( )
( )
0 1
0 1
1
,
1
p p
p p
V s V s
ab a
I s I s b
1 1
+ 1
1 1
1
1 1
]
] ]
(1)
where, ( ) a r sl x + , ( ) b g sc x + ; and r, l, g, c be the per unit
length resistance, self inductance, conductance, and self
capacitance (with respect to ground) respectively of the
concerned interconnect line and s be the Laplace variable.
This after rearrangement gives the following equations:
( ) ( ) ( ) ( )
( ) ( ) ( )
0 1 1
0 1 1
1
p p p
p p p
V s ab V s aI s
I s bV s I s
+ +
+
(2)
Since there will be some leakage of current from the aggressor
line to the victim line through the coupling capacitance
c
c x ,
the final current will be governed as follows:
( ) ( ) ( )
( ) ( ) ( ) ( ) ( )
1
1
1 1
1 1
, and
m
m
p c p f
c c a p
I t I t I t
I t c x d v t v t dt
+

(3)
There are several possibilities of input signal combinations on
the aggressor line and the victim line, which are listed below.
Case-1: Both aggressor and victim are driven by identical
(synchronized) transitions i.e., both are driven by either rising
transitions, or falling transitions. In such case it follows that
( ) ( ) ( )
1 1
0,
a p
d v t v t dt (4)
implying that ( )
1
0
m
c
I t and hence, crosstalk effect is zero.
Case-2: Aggressor and victim are driven by mutually opposite
transitions i.e., for instance, aggressor is driven by rising
transition whereas, the victim is driven by falling
(synchronized) transition, or vice versa. In such case the
derivative term can be expressed as:
( ) ( ) ( ) ( ) ( )
1 1 1
2 .
a p p
d v t v t dt d v t dt (5)
Case-3: The aggressor driver is driven by either rising or
falling transition, whereas victim line is driven by either
quiescent 1, or quiescent 0. In this case the derivative of
victim line signal is zero, thereby resulting in
( ) ( ) ( ) ( ) ( )
1 1 1
.
a p a
d v t v t dt d v t dt (6)
Note that in case-3 derivative of difference of aggressor and
victim line voltage can not be represented using the derivative
of victim line voltage at all. Therefore, taking into
consideration both case-1 and case-2 and writing (3) in s-
domain we have,
( ) ( ) ( )
( ) ( ) ( ) ( )
1
1
1 1
1
, and
1
m
m
p c p f
c c p
I s I s I s
I s k c x sv s
+

(7)
where, k =1 for synchronized identical transitions on both
aggressor and victim, whereas k =-1, for mutually opposite
transitions on aggressor and victim. Applying (7) equation (2)
can be written in ABCD matrix form as
( )
( )
( )
( )
( )
0 1
0 1
1
1
p pf p
p pf p
V s V s ad a
I s I s d
1 1 1 +
1 1 1
1 1 1
] ] ]
(8a)
Where, ( ) ( ) , with 1 , and .
p ap ap c
d b c c k sc x b g sc x + + If we
assume that ( ) ( ) 0, then 1
p c
g d s c k c x + . Equation (7)
represents the ABCD model for the first segment of the victim
line including the leakage current through the coupling
capacitance. Therefore, the entire length of victim line can be
modeled cascading several (n number of) such ABCD models.
So, the input-output voltage and current can be written as:
( )
( )
( ) ( )
( )
0 n
0 n
1
1
n
p pf p
p pf p
V s V s ad a
I s I s d
1 1 1 +
1 1 1
1 1 1
] ] ]
(8b)
Now, the n
th
power ( n ) of this ABCD matrix can be
computed as shown in appendix of [6], but with characteristic
impedance
p
Z and propagation constant
p
(the subscript p
refers to victim or passive line related parameter) as follows:
( )
( ) ( )
( ) ( )
cosh sinh
1
lim 1
sinh cosh 1
n
p p p
n
p p
p
p
p
L Z L
ad a
L L d
Z


1
1
+ 1
1

1
1
1
]
1
]
(9)
( )
( ) ( ) ( )
( ) ( ) ( ) ( )
,
1
1 .
p
p c
p
p c
r sl a
Z
d g s c K c
ad
r sl g s c K c
x

+

+ +
+ + +

(10)
Therefore, equation (9) represents the ABCD model of the
entire victim line of length L in presence of cross-talk noise
Adopting the similar procedure the corresponding ABCD
model of the aggressor line in presence of crosstalk noise can
also be developed.
3. Modeling of Driver - Victim Load
Considering an infinitesimally small segment of an victim
interconnect (see fig.-1) as a two-port network the
corresponding ABCD transmission parameter model of a long
victim line of length L, in presence of cross-talk noise, has
been derived in (9). However, (9) uses new characteristic
impedance parameter and new propagation constant (different
from the one used in appendix of paper [6]).
The similar kind of result is also obtained and used in
[6],[2]. The victim model (9) will be used here for estimating
the signal delay time, overshoot and undershoot voltages etc.
of the victim output signal at the far end (CMOS receiver
R
sa
v
in
R
sp
v
a0
i
a1f
i
a0
+
i
a1
+
v
a1
i
p0
i
p1
+ v
p1
v
p0
c
c
x
i
cm1
...
....
i
a(n-1)f
+
i
an
+
i
p(n-1)f
+ i
pn
+ v
pn v
p(n-1)f
c
c
x
i
cmn
i
lmn
v
a(n-1)f
C
L1
C
L2
i
p1f
i
pnf
A B
C D
1
1
]
A B
C D
1
1
]
A B
C D
1
1
]
A B
C D
1
1
]
aggressor active
v
o
(t)
C
L
c
s
...
v
i
(t)
R
s rx lx rx lx
L
Fig.- 2: Equivalent circuit of a driver- victim - load segment.
cx cx
output) side of victim line when any arbitrary combinations of
high frequency input transitions at the near end side of
aggressor and victim lines are given.
Based on the victim model (9) the corresponding cascaded
ABCD model for CMOS driver-victim, excluding the CMOS
receiver load segment (fig.-2), can be obtained as:
( )
( )
( ) ( )
( ) ( )
( )
( )
cosh sinh
1 1 0
1
1 0 1 sinh cosh
p p p
i o
s
i o s p p
p
L Z L
s s R v v
sc L L s s I I
Z


1
1 1
1 1 1
1 1
1 1 1
1 1 ] ]
] ] 1
]
(11)
Note that in fig.-2, the CMOS driver is modeled as a voltage
source driving a small output impedance (series resistance) R
s
,
and c
s
whereas, the CMOS receiver is modeled as a capacitive
load C
L
[2]. Simplifying (10) we get:
( )
( )
( )
( )
0 0
0 0
i o
i o
s s A B v v
C D s s
I I
1 1
1
1 1
1
1 1 ]
] ]
(12)
with,
( ) ( ) ( ) ( ) ( )
( ) ( ) ( ) ( ) ( )
0 0
0 0
1
1 cosh sinh , cosh sinh
1 sinh cosh , sinh cosh
s
s s p p s p p
p p
s s p p s p s p p p
R
A sR c L L C sc L L
Z Z
B sR c Z L R L D sc Z L L


+ + +
+ + +
(13)
In order to determine the output voltage, the matrix equation
(12) is rearranged, taking the inverse of the ABCD matrix:
( )
( ) ( )
( )
( )
0 0
0 0 0 0 0 0 0
1 o i
i
s s D B v v
C A A D B C s s
I I
1 1 1
1 1
1

1 1 ]
] ]
(14)
Now considering the CMOS receiver as capacitance C
L
the
load current can be written as, ( ) ( ).
o L o
s s s
c v I
Therefore,
further rearranging the above equation and by eliminating the
input current we have,
( )
( )
( )
i
o
L o o
s
v
s
v
A s B
c

+
(15)
3.1. Reduced Order Model and SI Loss Estimation
Since, we are interested to estimate the crosstalk coupling
effect on signal integrity (SI) loss on the victim line, for any
arbitrary combinations of input transitions on the drivers
input of aggressor and victim, (15) is rewritten, noting that
input to the victim driver is ( ).
i
s
v
Therefore, it follows that
( )
( )
( ) ( ) ( ) ( ) ( ) 1 cosh 1 sinh
i
o
s
s L s p L p s s p
p
v s
s v
R
sR C C L sC Z sC R L
Z

_
+ + + + +

,
(16)
Using only the capacitive crosstalk coupling and fourth
order Pades approximation as suggested in [6], that gives
sufficiently accurate model, the output voltage from (16) can
be written as shown in (17).
( ) ( )
2 3 4
1 2 3 4
1
1
o i
v s v s
b s b s b s b s
_


+ + + +
,
, where (17)

( )
( ) ( ) ( )
2
1
2 2 2 4 2 2
2
2
2 24 2 6
s s L s L
s s L s L L s s L
rcL
b R C C R cL C rL
lcL r c L rcL rcL
b R C C R cL C rL C lL R C C rL
+ + + +
+ + + + + + +
(18)

( )
( ) ( )
( )
( )
3 3 6 2 4 2 2 2 4
3
3 2 2 5 3
2 2 4 2 3 6 4 4 8 2 4 3 3 6
4
2 5 3 3 7
2
720 24 2 24
,
6 120 6
3 2
24 720 40320 24 720
2
120 5
s s L
s L L s s L s s L
s s L
s L
r c L lrc L lcL r c L
b R C C
lcL r c L rcL
R c C r C l R C C r R C C lL
l c L lr c L r c L lrc L r c L
b R C C
lrc L r c L
R c C r
_
+ + + + +

,
_
+ + + + +

,
_
+ + + + + +

,
+ + ( )
3 3 2 2 5
.
040 6 120 6
s s L
L s s L
R C C rlcL lcL r c L
C l R C C r
_ _
+ + + +

, ,
(19)
Note that in (18) and (19) the term c includes both the per unit
length self capacitance and coupling capacitance (1-K).c
c
term
of the interconnect (victim) line. The poles of the model (p
1
,
p
2
, p
3
and p
4
) are computed using semi-numerical and semi-
algebraic method. Therefore, (17) can be written as
( )
( )
( )( )( )( )
4 1 2 3 4
i
o
v s
v s
b s p s p s p s p
_



,
, (20)
3.2. Input Representation
The aggressor and victims drivers can have only the four
possible states of input signal which are as follows:
Rising, or ( ) 0 1 and Falling, or ( ) 1 0 transition,
Quiescent 1, or ( ) 1 1 and Quiescent 0, or ( ) 0 0 .
The rising input transition in time domain can be
mathematically described by (21), where = constant, and t
r
= signal rise time (constant), and u(t)= step function.
( ) ( ) ( ) 1 exp , with .
ir r
v t u t t t 1
]
(21)
This equation in s (Laplace) domain can be written as follows:
( )
( )
1 1
.
ir
v s
s s s s


_


+ +
,
(22)
However, the differentiation of (21) in time domain is as
( ) ( ) exp
ir
dv t dt t (23)
Similarly, falling transition in the time domain can be written
as (24), where the constant term t
f
= signal fall time = t
r
.
( ) ( ) ( ) exp , with
f if
v t u t t
t
1
]
(24)
Therefore, the corresponding s-domain representation and
differentiation in time can respectively be represented as
( )
1
,
if
v s
s

+
(25)
( ) ( ) exp
if
dv t dt t (26)
Likewise, the static input signals i.e., quiescent 1 or
quiescent 0 can respectively be written in time domain and
s-domain as (27) and (28).
( ) ( ), where 1.0, or 0.1.
iq L L
v t v u t v (27)
( ) .
L
iq
v
v s
s
(28)
Furthermore, 1.0
L
v for quiescent 1 and 0.1
L
v for
quiescent 0 respectively. The time derivative of the static
signals are obviously zero i.e., ( ) 0.
iq
dv t dt (29)
4. Time Domain Response of the Output Signal
The time domain response of the output voltage at the
receiver end of the victim can be easily computed from (20)
when any input signal v
i
(s) is substituted in (20). For instance,
in case of rising input transition at the drivers input of the
victim, substituting (24) in (20) and thereafter by partial
fraction method the output voltage at the receiver end of the
victim line can be written as
( )
( )( )( )( )( )
4 1 2 3 4
o
v s
b s s s p s p s p s p

+
(30)
or, ( )
01 02 3 1 2 4
4 1 2 3 4
o
k k k k k k
v s
b s s s p s p s p s p

_
+ + + + +

+
,
(31)
where, the partial fraction co-efficients are given by (32).
Taking the inverse Laplace transform of (31) the output
voltage at the victims receiver end is
( )
( )
( )
( )
( )
01 02 1 2 4 4
1
1 1
1 1
, ,
n
i n
i
i i
i i
k k p p p p
p p


+
" (32a)

( ) ( )
( )
( )( ) ( )
( )
1 2 4 4
1 1 1 2 2 2 1 2
2 3
1 1
,
i i
i i
k k
p p p p p p p p p p


+ +
(32b)

( )( ) ( ) ( ) ( )
3 4 2 3
3 3 3 4 3 4 4 4
1 1
1 1
,
i i
i i
k k
p p p p p p p p p p


+ +
(32c)
( )
3 1 2 4
0 01 02 1 2 3 4
4
p t p t p t p t t
v t k k e k e k e k e k e
b


1 + + + + +
]
. (33)
4.1. Delay Estimation
Now defining the delay at 90% of desired signal value,
i.e., ( ) 0.9 ,
o d dd
v t v (34)
the delay
d
t can be computed by solving (35) for
d
t .

1 2 3 4
01 02 1 2 3 4
4
0.9
d d d d d
t p t p t p t p t
dd
v k k e k e k e k e k e
b


1 + + + + +
]
(35)
Equation (35) can be solved easily by numerical method.
4.2. Overshoot and Undershoot Estimation
Overshoot occurs when a signal momentarily exceeds V
dd
whereas, undershoot occurs when the signal momentarily falls
below the permissible threshold voltage (logic high) V
dd-min
. In
other words, overshoot is the global maximum (max- voltage)
of the output waveform of the system taking place at time t
ov
in the neighborhood of the delay (t
d
). In contrast, undershoot
is the global minimum of the waveform within t
ov
and t
settling
.
Therefore, t
ov
and t
un
can respectively be determined by
solving (36) and (37) using Newton-Raphsons method.
( )
( ]
0
0 ,
d d
v t
t t t
t

(36)
( )
( ]
0
0 ,
ov ov
v t
t t t
t

(37)
5. Simulation and Discussion
In this section we present a simulation experiment for the
driver-victim-load segment using fourth order model and
Fig.-3: Crosstalk coupling effect on the victims signal
using the distributed parasitic r, l, c and c
c
as follows: r=
0.075 m , l = 0.123 pH m , c=8.8 fF m , c
c
= 0.88 fF m .
Furthermore, the additional parameters considered are as
follows: driver resistance R
s
= 10 , C
s
= 20fF, receiver load
C
L
=2.0fF, and length of victim line L= 400 m . PSPICE
simulation for victim line is also carried out using the n = 20
ABCD blocks (similar to (8a)) for verification of analytical
result, but not reported here because of space restriction. The
simulation with our crosstalk model is performed applying a
falling transition as the aggressors input and a rising
transition as the victims input. The simulation result is
depicted in figure-3. From the figure it is seen that victims
output is delayed in comparison to the input signal even if
there is no crosstalk (k = 1) and it is further aggravated (more
delayed) in presence of crosstalk coupling effect (k = -1). The
delay is further increased if the value of the coupling
capacitance is made even larger. This simulation result is also
supported by the PSPICE simulation result.
6. Concluding Remarks
In the paper the cross-talk coupling effect is analyzed
between the two interconnects namely, the aggressor and a
victim line, using the ABCD model. As the effect of inductive
cross-talk becomes significant only beyond several GHz
frequency range, in the paper capacitive cross-talk coupling
effect is only considered for various combinations of input
signals at the driver sides of aggressor and victim line.
However, when the victim line is fed with quiescent 1 or
quiescent 0 signal the ABCD model of the victim line can
not be developed as the derivative of the victim line voltage
vanishes for any quiescent (static) signal on the victim line
thereby, resulting in ( ) ( ) ( ) ( ) ( ) ,
c a p c a
c x d v t v t dt c x d v t dt
and that can not be represented at all in terms of derivative of
victim line voltage. Therefore, the corresponding ABCD
model development of victim line for quiescent 1 and 0
signal as its driver input remains unsolved and currently left
as future perspective of this work.
Acknowledgments
The Research work was supported by the German Federal Ministry of
Education and Research (BMBF) in the project AZTEKE under contract
number 01M3063C.
References
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Faults on Long Interconnects, Proc. of VTS-2002, April 2002.
[2] Banerjee, K., Mehrotra, A., Analysis of On-Chip Inductance Effects for
Distributed RLC Interconnects, IEEE Trans on CAD of Integrated
Circuits and Systems, Vol. 21, No. 8, August 2002, pp. 904 - 915.
[3] Chen, W., Gupta, S.K., Breuer, M.A., Test Generation in VLSI Circuits
for Crosstalk Noise, Proc. of Intern. Test Conference (ITC98), 1998,
pp.641-650.
[4] Cuviello, M., et. al., Fault Modelling and Simulation for Crosstalk in
system-on-Chip Interconnects, ISBN: 0-7803-5832-X / 99, 1999 IEEE.
[5] Kahng, A.B., and Muddu, S., An Analytical Delay Model for RLC
interconnects, IEEE Transaction on CAD of Integrated Circuits and
Systems, Vol. 16, No.12, December 1997, pp. 1507 - 1514.
[6] Palit, A.K., Anheier, W., Schloeffel, J., Estimation of Signal Integrity
Loss through Reduced Order Interconnect Model, Proc. of 7
th
IEEE
Workshop on Signal Propagation on Interconnects (IEEE-SPI 2003), 11-
14
th
May, 2003, Siena, Italy, ISBN:0-7803-7051-1, pp.163-166.
[7] Sinha, A., Gupta, S.K., Breuer, M.A., Validation and Test Generation
for Oscillatory Noise in VLSI Interconnects, ISBN: 0-7803-5832-X / 99,
1999 IEEE.
[8] Young, B, Digital Signal Integrity, Prentice-Hall, (Upper Saddle River,
NJ, 2001), pp. 12-13,56-57, 98-104.
0 0.2 0.4 0.6 0.8 1 1.2
x 10
-9
0
0.2
0.4
0.6
0.8
1
Crosstalk coupling Effect on Victim line
Time (ns)
V
o
(
t
)
k = -1 (Victim's output with crosstalk effect)
Rising Input transition on Victim's Driver (rise time: 120 ps)
k = 1 ( i.e., no crosstalk effect)
Aggressor & victim's input = falling & rising resp.

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