Lecture 2 EE143 Sp2011

Principle of Monolithic Process Integration p g

* Asequence of Additive and Subtractive steps A sequence of Additive and Subtractive steps
with lateral patterning
Example: CMOS Integrated Circuit
Processing
Steps
Si wafer
Professor J . Bokor, U.C. Berkeley
Lecture 2 EE143 Sp2011
Crystal Pulling
Crystal Ingots
Czochralski Crystal Growth
Shaping and Polishing
Professor J . Bokor, U.C. Berkeley
2
p g g
300 mm wafer
Lecture 2 EE143 Sp2011
Professor J . Bokor, U.C. Berkeley
3
Lecture 2 EE143 Sp2011
Purity of Starting IC Si Wafer Purity of Starting IC Si Wafer
Maximumimpurity of starting Si wafer is equivalent to
99.999999999 % (so 99.999999999 % (so--called eleven nines ) !! called eleven nines ) !!
Maximum impurity of starting Si wafer is equivalent to
1 mg of sugar dissolved in an Olympic-size swimming pool..
Professor J . Bokor, U.C. Berkeley
Lecture 2 EE143 Sp2011
Photolithography
glass plate
chromium
Processing Temperature
Ambient Ambient
Positive Resist
Region exposed to light will Region exposed to light will
be dissolved in development
solution.
Professor J . Bokor, U.C. Berkeley
5
Lithography
Resist Coating
Development
Positiveresist Negativeresist
Photoresist
Positive resist Negative resist
Oxide
Si
(a)
Deep Ultraviolet Light
Si Si
(c)
Optical
Lens system
Photomask with
opaque and
clear patterns
(c)
Exposure
Et hi dR i t St i
Si
Si
(d)
(b)
Exposure
Etching and Resist Strip
(b)
Lecture 2 EE143 Sp2011
Deep UV Photolithography
Sequence:
(1)Surface Prime, (2) Coat, (3) Prebake, (1)Surface Prime, (2) Coat, (3) Prebake,
(4) Expose, (5) Post Exposure bake,
(6) Develop, (7) Hard Bake
Professor J . Bokor, U.C. Berkeley
Lecture 2 EE143 Sp2011
Deep UV Photolithography
(continued)
Professor J . Bokor, U.C. Berkeley
Lecture 2 EE143 Sp2011
*All b ki
Example :
Deep UV
Photolithography
*All baking
sub-steps
are similar
but with different
temperat re and time
Photolithography
(continued)
temperature and time
Professor J . Bokor, U.C. Berkeley
Lecture 2 EE143 Sp2011
Deep UV Wafer Stepper p pp
Professor J . Bokor, U.C. Berkeley
Lecture 2 EE143 Sp2011
Etching
Pattern resist mask
Etching thin film g
Etching completed Etching completed
A i t i
Remove resist mask
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11
Isotropic
(e.g. Wet Etching)
Anisotropic
(e.g. Reactive Ion Etching RIE )
Processing Temperature
Ambient
Lecture 2 EE143 Sp2011
Etching Selectivity Etching Selectivity
Example: HF solution etches SiO
2
but not Si
SiO solution
HF
Example: HF solution etches SiO
2
but not Si
SiO
2
Si
solution
Si
* A high etching selectivity is usually desired
Professor J . Bokor, U.C. Berkeley
12
Lecture 2 EE143 Sp2011
Thermal Oxidation
Processing Temperature
Si +O
2
SiO
2
Processing Temperature
900-1100
o
C
Si + O
2
SiO
2
Si + 2 H
2
O SiO
2
+ 2H
2
O
2
(or H
2
O) diffuses through SiO
2
and
reacts with Si at the interface to form
more SiO
2
.
1mm of SiO
2
formed consumes 0.44
mm of Si substrate.
Thin oxide growth (e.g. gate oxide) -
use O
2
Dry oxidation
Oxide (X
ox
)
hi k
use O
2
. Dry oxidation
Thick oxide growth (e.g. field oxide) -
use H
2
O. Wet oxidation
thickness
t
t
Professor J . Bokor, U.C. Berkeley
13
Oxidation time(t)
t
Lecture 2 EE143 Sp2011
Oxidation of Silicon
Si Wafers
Quartz tube
Flow
controller

O
2
N
2
H
2
O or TCE(trichloroethylene) Resistance-heated furnace
Professor J . Bokor, U.C. Berkeley
Lecture 2 EE143 Sp2011
Uneven surface topography with window
id ti oxidation
1
st
oxidation
Si
1
st
oxidation
Si
SiO
2
2
nd
oxidation
Pattern oxide window
by litho and etch
Si
Realistic topography
with 2-dimensional effect
by litho and etch
SiO
2
SiO
2
SiO
2
Si
Si
Si
2
Professor J . Bokor, U.C. Berkeley
15
Note uneven Si surface
after window oxidation
Lecture 2 EE143 Sp2011
silicon nitride
Local Oxidation
Si N
O
2
as oxidation mask
Si
3
N
4
Si
pad oxide
~100 A
Thermal Oxidization
Si
LOCOS
nitride
Process
SiO
2
Si
Professor J . Bokor, U.C. Berkeley
16
Lecture 2 EE143 Sp2011
Ion Implantation
t picall sed to introd ce dopants into semicond ctors
Ion Energy
1 keV to
P i T t
typically used to introduce dopants into semiconductors
~1 keV to
200 keV
Processing Temperature
Room temp during
implantation. p
After implantation,
a 900
o
C-1000
o
C
anneal step is needed to: anneal step is needed to:
1) activate dopants
2) restore Si crystallinity
Professor J . Bokor, U.C. Berkeley
17
Lecture 2 EE143 Sp2011
Ion Implanter
Professor J . Bokor, U.C. Berkeley
18
Lecture 2 EE143 Sp2011
Ion Implant Numbers p
Professor J . Bokor, U.C. Berkeley
Lecture 2 EE143 Sp2011
Diffusion
To introduce dopants into semiconductors [ Predeposition] To introduce dopants into semiconductors [ Predeposition]
To spread out the dopant profile [ Drive-in]
Processing Temperature
850-1150
o
C
=

e D D
kT
Q
0
=
=
Energy Activation Q
Constant Diffusion D
e D D
0
( ) | | = T as D K in Temp T
Energy Activation Q
Professor J . Bokor, U.C. Berkeley
20
Lecture 2 EE143 Sp2011
Predeposition
Si surface concentration
maintained at constant C
s
(solid-solubility)
during predep during predep.
X: Dose of dopant
incorporation
(in #/cm2)
Dt C
s
2
X
t
s
X =
Professor J . Bokor, U.C. Berkeley
21
Lecture 2 EE143 Sp2011
Predeposition and Drive-in
Drive-in means removing dopant
supply after Predep step and
anneal at high temperature
Half-gaussiandepth profile after
long drive-in.
Predep only
Dopant dose conserved during
drive-in.
Diffusion distance Diffusion distance
( ) Dt ~
Predep +Drive-in
Professor J . Bokor, U.C. Berkeley
22
Concentration (in #/cm
3
) versus Depth
Lecture 2 EE143 Sp2011
Physical Vapor Deposition (1)
Evaporation Deposition
S b t t
Si Substrate
Substrate
at ~ room temp
Deposited Al film
(polycrystalline)
evaporation
Al charge
Professor J . Bokor, U.C. Berkeley
23
(T
source
>>T
boiling
of Al , 700
O
C)
Lecture 2 EE143 Sp2011
Physical Vapor Deposition (2)
Sputtering Deposition
S b t t t
Si Substrate
Deposited Al film
Substrate ~ at room
temp
Ar
+
Al atoms ejected due to
Deposited Al film
(polycrystalline)
Ar ions
with ~ keV
Al atoms ejected due to
Ar ion bombardment
Al target
with ~ keV
kinetic energy
Professor J . Bokor, U.C. Berkeley
24
Lecture 2 EE143 Sp2011
Chemical Vapor Deposition (CVD)
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25
Lecture 2 EE143 Sp2011
Chemical Vapor Deposition (CVD) of SiO
2
2 2 2 4
2H SiO O SiH + +
O H C SiO O H O H C Si
6 2 2 2 4 5 2
4 2 ) ( + +
or
LTO
TEOS
2 2 2 4
Temperature range:
350
o
C to 450
o
C for silane
~700
o
C for TEOS
Process:
Precursor gases dissociate at the
wafer surface to form SiO
2
oxide
thickness
wafer surface to form SiO
2
No Si on the wafer surface is
consumed
Film thickness is controlled by the
t
Film thickness is controlled by the
deposition time
time, t
Professor J . Bokor, U.C. Berkeley
Lecture 2 EE143 Sp2011
Chemical Mechanical Polishing (CMP)
Wafer is polished using a slurry containing
silica abrasives (10-90 nm particle size)
etching agents (e.g. dilute HF)
Backing film provides elasticity
between carrier and wafer
Polishing pad made of polyurethane, with
1 mm perforations
rough surface to hold slurry
Ambient
T
Professor J . Bokor, U.C. Berkeley
27
rough surface to hold slurry
Temperature
Lecture 2 EE143 Sp2011
Chemical Mechanical Polishing (CMP)
CMP is used to planarize the surface of a wafer at various
steps in the process of fabricating an integrated circuit.
interlevel dielectric (ILD) layers
shallow trench isolation (STI)
copper metallization
ILD with 5 layers of Al wiring
Shallow Trench Oxide
SiO
2
p n
n+ n+ p+ p+
Professor J . Bokor, U.C. Berkeley
p
Lecture 2 EE143 Sp2011
Copper Plating
Dual Damascene Process
(1)
courtesy of Sung Gyu Pyo,
Hynix Semiconductor
(2)
(4)
(3)
(5)
Professor J . Bokor, U.C. Berkeley
Lecture 2 EE143 Sp2011
Multilevel Metal
Professor J . Bokor, U.C. Berkeley
Lecture 2 EE143 Sp2011
Rapid Thermal Annealing (RTA)
Special annealing tools have been developed to enable
much faster temperature ramping, and precise control of
annealing time annealing time
ramp rates as fast as 200
o
C/second
anneal times as short as 0.5 second
typically single-wafer process chamber
Sub-micron MOSFETs need ultra-shallow junctions (x
j
<50 nm)
Dopant diffusion during activationanneal must be minimized Dopant diffusion during activation anneal must be minimized
Short annealing time (<1 min.) at high temperature is required
Ordinary furnaces (e.g. used for thermal oxidation and CVD)
Professor J . Bokor, U.C. Berkeley
y ( g )
heat and cool wafers at a slow rate (<50
o
C per minute)
Lecture 2 EE143 Sp2011
Rapid Thermal Annealing Tools
There are 2 types of RTA systems:
1. Furnace-based
steady heat source +fast mechanical wafer transport steady heat source + fast mechanical wafer transport
2. Lamp-based
stationary wafer + time-varying optical output from lamp(s)
Lamp RTA
Furnace RTA
Professor J . Bokor, U.C. Berkeley
A.T. Fiory, Proc. RTP2000
Lecture 2 EE143 Sp2011
Microfabrication Module Summary List
Lithography
Thermal Oxidation Thermal Oxidation
Etching (Chemical , RIE)
Ion Implantation
Diffusion (Furnace Annealing, Rapid Thermal Annealing RTA)
Physical Vapor Deposition PVD
Chemical Vapor Deposition CVD C e ca apo epos to C
Chemical Mechanical Polishing CMP
Metal Plating
Others Others.
Professor J . Bokor, U.C. Berkeley
33
Lecture 2 EE143 Sp2011
Principle of Monolithic Process Integration p g
* Asequence of Additive and Subtractive steps A sequence of Additive and Subtractive steps
with lateral patterning
Example: CMOS Integrated Circuit
Processing
Steps
Si wafer
Professor J . Bokor, U.C. Berkeley
Lecture 2 EE143 Sp2011
The EE143 Lab Process (part I)
Professor J . Bokor, U.C. Berkeley
Lecture 2 EE143 Sp2011
The EE143 Lab Process (Part II)
Professor J . Bokor, U.C. Berkeley
Lecture 2 EE143 Sp2011
Process Yield
Complex CMOS process may require 25 masks
What fraction of dice must be good (what yield %) at at acto o dce ust be good ( at yed %) at
each mask step to get 30% yield overall?
How about to get 70% ?
99% ?
Professor J . Bokor, U.C. Berkeley