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04 14 LTSSM Implementation at 5GTs and Beyond PDF

LTSSM Implementation

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271 views18 pages

04 14 LTSSM Implementation at 5GTs and Beyond PDF

LTSSM Implementation

Uploaded by

Hardik Trivedi
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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LTSSM Implementation at 5 GT/s and Beyond

Anujan Varma Denali Software, Inc.

Copyright 2007, PCI-SIG, All Rights Reserved

Agenda
Link Training Status State Machine (LTSSM) Overview
Speed negotiation overview Negotiating lane speeds beyond 5 GT/s

LTSSM Example Implementation


Implementation challenges Modular LTSSM design Results from FPGA implementation at 10 GT/s lane speed

PCI-SIG Developers Conference

Copyright 2007, PCI-SIG, All Rights Reserved

LTSSM Overview

States not shown: L0s, L1, L2, Loopback, Disabled, Hot Reset
PCI-SIG Developers Conference Copyright 2007, PCI-SIG, All Rights Reserved 3

LTSSM Speed Negotiation


Recovery.Idle

Recovery.RcvrCfg

Recovery.Speed

L0

Recovery.RcvrLock

Speed switched from 2.5G to 5G

Successful speed negotiation from 2.5G to 5G

PCI-SIG Developers Conference

Copyright 2007, PCI-SIG, All Rights Reserved

Speed Negotiation From 2.5G to 5G


Component A
L0 (2.5G)
Directed_speed_change set

Component B
L0 (2.5G)
TS1 received

Recovery.RcvrLock

Sends TS1 with speed_change bit = 1. Advertises 2.5G and 5G rates

Sends TS1. Sets speed_change bit on Receiving 8 TS1s, and advertises 2.5G and 5G rates.

Recovery.RcvrLock

8 TS1/TS2s received with speed_change bit = 1

8 TS1/TS2s received with speed_change bit = 1

Recovery.RcvrCfg

Sends TS2 with speed_change bit = 1. Advertises 2.5G and 5G rates

Recovery.RcvrCfg
8 TS2s received with speed_change bit = 1

8 TS2s received with speed_change bit = 1

Recovery.Speed

Speed changed to 5G

Speed changed to 5G

Recovery.Speed

Recovery.RcvrLock

Recovery.RcvrLock

Recovery.RcvrCfg

Recovery.RcvrCfg

Recovery.Idle

Recovery.Idle

L0 (5G)

L0 (5G)

PCI-SIG Developers Conference

Copyright 2007, PCI-SIG, All Rights Reserved

Speed Advertisement
Supported speeds advertised in TS1/TS2 sequences
Training Control Data Rate Identifier Lane Num Link Num

D10.2/ D5.2 (10 symbols)

N_FTS

COM

Bit 7 Speed change

5G

2.5G

Supported Speeds

Bit 3 used to advertise 10G capability in our implementation

PCI-SIG Developers Conference

Copyright 2007, PCI-SIG, All Rights Reserved

Negotiating Speeds Beyond 5 GT/s


PCIe 2.0 defines lanes speeds of 2.5 and 5.0 GT/s Speed negotiation protocol may be extended for lane speeds beyond 5 GT/s
Example implementation allows 2.5, 5 and 10 GT/s lane speeds. Demonstrates:
1) Scaling of speed negotiation protocol beyond 5 GT/s 2) Feasibility of implementing LTSSM in relatively low-speed logic

PCI-SIG Developers Conference

Copyright 2007, PCI-SIG, All Rights Reserved

Speed Negotiation From 2.5G to 10G


Component A
L0 (2.5G)
Directed_speed_change set

Component B
L0 (2.5G)
TS1 received

Recovery.RcvrLock

Sends TS1 with speed_change bit = 1. Advertises 2.5G, 5G and 10G rates

8 TS1/TS2s received with speed_change bit = 1

Sends TS1. Sets speed_change bit on Recovery.RcvrLock Receiving 8 TS1s, and advertises 2.5G, 5G and 10G rates. 8 TS1/TS2s received with speed_change bit = 1

Recovery.RcvrCfg

Sends TS2 with speed_change bit = 1. Advertises 2.5G, 5G and 10G rates

Recovery.RcvrCfg
8 TS2s received with speed_change bit = 1

8 TS2s received with speed_change bit = 1

Recovery.Speed

Speed changed to 10G

Speed changed to 10G

Recovery.Speed

Recovery.RcvrLock

Recovery.RcvrLock

Recovery.RcvrCfg

Recovery.RcvrCfg

Recovery.Idle

Recovery.Idle

L0 (10G)

L0 (10G)

PCI-SIG Developers Conference

Copyright 2007, PCI-SIG, All Rights Reserved

LTSSM Implementation
Specification facilitates modular implementation
All lanes transmit same TS data, except link and lane number fields
Single transmit-side module for all lanes

Separate receive-side module per lane

Challenges
Lane skew on receive side Phy errors on receive side Transmitting compliance pattern

PCI-SIG Developers Conference

Copyright 2007, PCI-SIG, All Rights Reserved

LTSSM Example Implementation

PCI-SIG Developers Conference

Copyright 2007, PCI-SIG, All Rights Reserved

10

Transmitting Training Sequences

Transmit side primarily transmits TS1/TS2 on all configured lanes


Some field settings are a function of LTSSM state
TS1/TS2, link number, lane number

Most fields can be changed on all lanes simultaneously

Data path can be from 1 byte to 16 bytes per lane Single data path can feed all lanes

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Copyright 2007, PCI-SIG, All Rights Reserved

11

LTSSM Transmit-Side Implementation

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LTSSM Receive-Side Implementation


Independent receive-side modules needed to decode Training Sequences
Skew may cause outputs to be misaligned Phy errors may disqualify output

Decoding may be done in parallel


Data path can be from 1 byte to 16 bytes

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Copyright 2007, PCI-SIG, All Rights Reserved

13

LTSSM Receive-Side Example Implementation


Consists of N instances of same Training Sequence Decoder module
Module decodes TS1/TS2, extracts fields Implements building blocks for generating LTSSM inputs
Example: 8 TS1s received with link number and lane number = PAD

Enables same LTSSM design to be used at different lane speeds

PCI-SIG Developers Conference

Copyright 2007, PCI-SIG, All Rights Reserved

14

LTSSM Example Implementation


Implemented RC and EP sides of LTSSM
Max lane speed of 10 GT/s, and up to 10 lanes 125 MHz clock

Consists of
Main LTSSM module Training Sequence Generator Module with configurable data path width Training Sequence Decoder Modules (1 per lane) with configurable data path width

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Copyright 2007, PCI-SIG, All Rights Reserved

15

LTSSM Example Implementation

PCI-SIG Developers Conference

Copyright 2007, PCI-SIG, All Rights Reserved

16

Summary
The PCIe LTSSM Specification, despite its complexity, enables a scalable and modular implementation.
Design can be partitioned into 3 key blocks
Main LTSSM module, independent of lane speed Common transmit-side module with configurable data path width Per-lane receive-side modules with configurable data path width

Example implementation demonstrates feasibility at lane speeds higher than 5 GT/s

PCI-SIG Developers Conference

Copyright 2007, PCI-SIG, All Rights Reserved

17

Thank you for attending the PCI-SIG Developers Conference 2007.

For more information please go to www.pcisig.com


PCI-SIG Developers Conference Copyright 2007, PCI-SIG, All Rights Reserved 18

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