Erick Cafferata: Personal Data
Erick Cafferata: Personal Data
Personal Data
Place and Date of Birth: Address: Phone: email: Per u 03 February 1989 Eng Humberto Soares Camargo 1155 Cidade Universitaria 13083-780, Campinas, SP, Brasil (19) 982786487 lcaeratac@gmail.com
Work Experience
Current Apr 2013 Integrated Circuits Trainee at CT2, Campinas CTI Renato Archer - Programa CI Brasil
Design of digital blocks for ASICs using Cadence EDA tools. Involved in the development of an ARM Cortex-M3 microcontroller. Designed a JTAG serializer IP block according to ARM Coresight specications. Developed the verication environment for an Independent Watchdog IP block.
Jan-Mar 2011
Education
2006 - 2011 Undergraduate Degree in Electronic Engineering
Embedded Systems Specialization, Universidad Peruana de Ciencias Aplicadas,
Lima, Per u Design and Implementation of a Wireless Sensor Network optimized for Home Automation Advisor: Renatto Gonzales
Languages
English: Spanish: Japanese: Portuguese: Fluent Native Intermediate Knowledge Intermediate Knowledge
Technical Skills
Basic Knowledge: . Intermediate Knowledge:
A System Verilog, C++, L TEX E Verication Language, Cadence EDA tools(Digital), C#, Orcad Spice, Matlab, Linux, ASM(x86, PIC16fxxx, Intel 8051, Freescale 68xx, ARM, Thumb, Thumb2). C, Verilog, Architecture ARMv6 & ARMv7-M, Experience with several RTOS, Eagle.
Advanced Knowledge: