Introduction to Digital Logic with Laboratory Exercises

Introduction to Digital Logic with Laboratory Exercises

James Feher
Copyright 2010 James Feher

Editor-In-Chief: James Feher Associate Editor: Marisa Dre e! "roofreaders: Jac#ie $harman% &ache! "'g!iese For any ('estions a)o't this te t% p!ease emai!: dre e!*'ga+ed'

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Table of Contents
"reface+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 5

0+ Introd'ction+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++6 1+ ,he transistor and in2erter++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 7

,he transistor++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 7 ,he )read)oard+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 10 ,he in2erter+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 11

2+ 4ogic gates++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 13
8istory of !ogic chips+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 13 4ogic sym)o!s++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 19 4ogica! f'nctions+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1:

3+ 4ogic simp!ification++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++16
De Morgan;s !a0s++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 16 <arna'gh maps+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 17 Circ'it design% constr'ction and de)'gging++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 23

9+ More !ogic simp!ification+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++25

Additiona! <-map gro'pings++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 25 Inp't p!acement on <-map+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2= Don;t care conditions++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2=

:+ M'!tip!e er+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++30
>ac#gro'nd on the ?m' @++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 30 Asing a m'!tip!e er to imp!ement !ogica! f'nctions++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 30

5+ ,imers and c!oc#s++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3:

,iming in digita! circ'its+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3: ::: timer+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3: ,imers+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3: C!oc#s++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 35 ,iming diagrams+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3=

=+ Memory ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++91
Memory+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 91 $& !atch+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 91 F!ip-f!ops+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 92

6+ $tate machines+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++95
Bhat is a state machineC++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 95 $tate transition diagrams+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 95 $tate machine design++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 9= De)o'nced s0itches++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ :1

7+ More state machines++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++:3

8o0 many )its of memory does a state machine needC++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ :3 Bhat are 'n'sed statesC+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ :3

10+ Bhat;s ne tC+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++50 Appendi A: Chip pino'ts+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++51 Appendi >: &esistors and capacitors+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++5:
&esistors++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 5: Capacitors+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 55

Appendi C: 4a) note)oo#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 5= Appendi D: >oo!ean a!ge)ra++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++56 Appendi E: E('ipment !ist++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 57

Digita! trainer+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 57 =900 series fami!ies++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 57 Style Guidelines 3 A -!o)a! ,e t

Appendi F: $o!'tions ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ =0

Chapter 1 re2ie0 e Chapter 2 re2ie0 e Chapter 3 re2ie0 e Chapter 9 re2ie0 e Chapter : re2ie0 e Chapter 5 re2ie0 e Chapter = re2ie0 e Chapter 6 re2ie0 e Chapter 7 re2ie0 e ercises++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ =0 ercises++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ =1 ercises++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ =9 ercises+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 60 ercises+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 63 ercises+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 67 ercises+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 72 ercises+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 7: ercises+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 7=

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A)o't the a'thor and re2ie0ers Author: James Feher

Jim c'rrent!y teaches Comp'ter $cience at Mc<endree Ani2ersity in 4e)anon% I!!inois% A$A+ 8e is a h'ge openso'rce soft0are proponent+ 8is research foc'ses on the 'se of open so'rce soft0are in the areas of hard0are% programming and net0or#ing+ 8is ho))ies inc!'de triath!on% hi#ing% camping and the 'se of a!ternati2e energy+ 8e !i2es 0ith his 0ife and three #ids in $t+ 4o'is% Misso'ri 0here he )'i!t and contin'es to perfect a so!ar hot 0ater heating system for his home+

Reviewer: Andrew Van Camp

"rofessor Dan Camp is a retired e!ectronics professor+ In addition% he has e tensi2e e perience 0or#ing and cons'!ting in ind'stry+ 8e c'rrent!y resides in centra! Misso'ri 0here he contin'es his cons'!ting for ind'stry+

Reviewer: Kumud Bhandari

<'m'd grad'ated from Mc<endree Ani2ersity 0ith degrees in comp'ter science and mathematics+ 8e has interned at the Ani2ersity of ,e as and the Massach'setts Instit'te of ,echno!ogy+ 8e c'rrent!y is emp!oyed as a researcher 0ith Argonne Eationa! 4a)oratory+

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Preface
,his !a) man'a! pro2ides an introd'ction to digita! !ogic% starting 0ith simp!e gates and )'i!ding 'p to state machines+ $t'dents sho'!d ha2e a so!id 'nderstanding of a!ge)ra as 0e!! as a r'dimentary 'nderstanding of )asic e!ectricity inc!'ding 2o!tage% c'rrent% resistance% capacitance% ind'ctance and ho0 they re!ate to direct c'rrent circ'its+ 4a)s 0i!! )e )'i!t 'ti!i1ing the fo!!o0ing hard0are:
)read)oards 0ith associated items re('ired s'ch as 0ire% 0ire strippers and c'tters some )asic discrete components s'ch as transistors% resistors and capacitors )asic =900 series !ogic chips ::: timer

Discrete components 0i!! )e inc!'ded on!y 0hen necessary% 0ith most of the !a)s 'sing the standard =900 series !ogic chips+ ,hese items are common!y a2ai!a)!e and can )e o)tained re!ati2e!y ine pensi2e!y+ 4a)s 0i!! inc!'de !earning o).ecti2es% re!e2ant theory% re2ie0 pro)!ems% and s'ggested proced're+ In addition to the !a)s% se2era! appendices of )ac#gro'nd materia! are pro2ided+

Format for each chapter

Each chapter is a com)ination of theory fo!!o0ed )y re2ie0 e ercises to )e comp!eted as traditiona! home0or# assignments+ F'!! so!'tions to a!! of the re2ie0 e ercises are a2ai!a)!e in the !ast appendi + "roced'res for !a)s then fo!!o0 that a!!o0 the st'dent to imp!ement the concepts in a hands on manner+ ,he materia!s re('ired for the !a)s 0ere se!ected d'e to their ready a2ai!a)i!ity at modest cost+ Bhi!e st'dents 0o'!d gain from .'st reading and comp!eting the re2ie0 e ercises% it is recommended that the proced'res )e comp!eted as 0e!!+ In addition to pro2iding another means re-enforcing the materia!% it he!ps to de2e!op rea! 0or!d de)'gging and design s#i!!s+ ,his man'a! concentrates on the )asic )'i!ding )!oc#s of digita! e!ectronics: !ogic gates and memory+ It foc'ses on these items from the gro'nd 'p+ ,he reader 0i!! first see ho0 !ogic gates can )e constr'cted from transistors and then ho0 digita! !ogic f'nctions are constr'cted 'sing those gates+ ,he concept of memory is then introd'ced thro'gh the constr'ction of an $& !atch and then a D f!ip-f!op+ A c!oc# is created to )e 'sed in a )asic state machine design that aims to com)ine !ogic circ'its 0ith memory+

ar!et audience
,his te t 0i!! )e geared to0ard comp'ter science st'dentsF ho0e2er it 0o'!d )e appropriate for any st'dents 0ho ha2e the necessary )ac#gro'nd in a!ge)ra and e!ementary DC e!ectronics+ Comp'ter science st'dents !earn s#i!!s in ana!ysis% design and de)'gging+ ,hese s#i!!s are a!so 'sed in the virtual 0or!d of programming% 0here no physica! de2ices are e2er in2o!2ed+ >y re('iring the assem)!y and demonstration of act'a! circ'its% st'dents 0i!! not on!y !earn a)o't digita! !ogic% )'t a)o't the intricacies and diffic'!ties that arise 0hen physica!!y imp!ementing their designs as 0e!!+

Glo"al e#t $ro%ect

Education is the most powerful weapon you can use to change the world - Nelson Mandela ,he goa! of this te t is to a!!o0 more st'dents to gain access to this materia! )y p')!ishing it in the Creati2e Commons as 0e!! as specifying ine pensi2e materia!s to )e 'sed in the !a)s+ For this reason the a'thor chose to 0or# 0ith the -!o)a! ,e t pro.ect to de2e!op this te t+ ,he -!o)a! ,e t "ro.ect 0i!! create open content e!ectronic te t)oo#s that 0i!! )e free!y a2ai!a)!e from a 0e)site+ Distri)'tion 0i!! a!so )e possi)!e 2ia paper% CD% or DDD+ ,he

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Preface goa! of the -!o)a! ,e t "ro.ect initia!!y is to foc's on content de2e!opment and Be) distri)'tion% and 0or# 0ith re!e2ant a'thorities to faci!itate dissemination )y other means 0hen )and0idth is 'na2ai!a)!e or inade('ate+ ,he goa! is to ma#e te t)oo#s a2ai!a)!e to the many 0ho cannot afford them+

Ac&nowled!ments
A 0or# s'ch as this 0o'!d not )e possi)!e 0itho't the he!p of many+ First% I 0o'!d !i#e to than# the -!o)a! ,e t "ro.ect for their 2ision of pro2iding e!ectronic te t)oo#s for free to e2eryone+ Marisa Dre e!% Associate Editor at the -!o)a! ,e t "ro.ect pro2ided co'nt!ess s'ggestions and he!pf'! hints for the doc'ment and for the creation of the doc'ment 'sing GpenGffice+ Andre0 Dan Camp II% retired professor of e!ectronics pro2ided e ce!!ent s'ggestions for technica! re2ie0 of the content+ <'m'd >handari% c'rrent!y a research aide at Argonne Eationa! 4a)oratory% a!so pro2ided technica! re2ie0 of the materia!+ My st'dents E2an Dan$coy#% $amantha >arnes% and >en Hor# a!! pro2ided he!pf'! corrections and re2ie0 as 0e!! as co'nt!ess diagrams fo'nd in the doc'ment+ I 0o'!d !i#e to than# a!! of the co'nt!ess open-so'rce de2e!opers 0ho prod'ced s'ch fine soft0are as -EAI4in' % GpenGffice% -imp% and Dia 0hich 0ere a!! 'sed to create this doc'ment+ I am gratef'! to Mc<endree Ani2ersity for pro2iding s'pport in the form of a sa))atica! to a!!o0 me to comp!ete this 0or#+ And I certain!y 0ish to than# $andy 0ho pro2ided e ce!!ent re2ie0 s'ggestions% s'pport and an e treme!y patient ear 0hen I ran into tro')!e trying to incorporate a ne0 feat're from GpenGffice or attempted to edit a partic'!ar!y tric#y graphic+

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0 Introduction
It is near!y impossi)!e to find a part of society that has not )een to'ched )y digita! e!ectronics+ G)2io's app!ications s'ch as comp'ters% te!e2isions% digita! 2ideo reorders and co'nt!ess other cons'mer e!ectronics 0o'!d not )e possi)!e 0itho't them+ ,he Internet is r'n on a system of comp'ters and ro'ting e('ipment )'i!t 0ith digita! e!ectronics+ Het e2en o'tside of some of these o)2io's app!ications 0e find that o'r cars and 'ti!itarian home app!iances s'ch as micro0a2es% 0ashers% dryers% coffee ma#ers and e2en refrigerators are a!! increasing!y )eing designed 0ith digita! e!ectronic contro!s+ Ho' !i#e!y carry some sort of de2ice designed 0ith them 0ith yo' near!y a!! yo'r 0a#ing ho'rs 0hether it is a 0atch% ce!! phone% M"3 p!ayer or "DA+ Indeed% digita! e!ectronics pro2ide the fo'ndation 'pon 0hich 0e )'i!d the infrastr'ct're of modern society+ Ho' no do')t ha2e heard stories a)o't some of the first comp'ters+ Machines )'i!t 0ith mechanica! re!ays and 2ac''m t')es that fi!!ed entire rooms+ In the 1790s John >ardeen% Ba!ter >rattain and Bi!!iam $hoc#!ey de2e!oped the first transistorF it a!!o0ed comp'ters to )e )'i!t cheaper% sma!!er and more re!ia)!e than e2er )efore+ ,he integrated circ'it% a sing!e pac#age 0ith se2era! transistors a!ong 0ith other circ'it components% 0as de2e!oped in the !ate 17:0s )y Jac# <i!)y at ,e as Instr'ments+ ,his he!ped to f'rther ad2ance the digita! re2o!'tion+ Ad2ances then )ecame so common that in the 1750s -ordon Moore% co-fo'nder of Inte! Corporation% proposed his famo's !a0 stating that the capacity of comp'ters 0e 'se 0o'!d do')!e e2ery t0o years+ ,his o)ser2ation has he!d 'p since then% e2en )eing amended to do')!ing e2ery eighteen months+ ,he ('ad core microprocessors of today contain mi!!ions of components% )'t the )asic )'i!ding )!oc#s are digita! !ogic f'nctions com)ined 0ith memory+ Despite the fact that many of these de2ices are tremendo's!y comp!e and re('ire 2ast amo'nts of engineering in their design% they a!! share the ')i('ito's )it as their f'ndamenta! 'nit of data+ In essence it a!! starts 0ith ,&AE and FA4$E or 0 and 1+ And so the ne t chapter starts 0ith the simp!est of !ogic de2ices% the in2erter% )'i!t 0ith a sing!e transistor+ Ho' then contin'e yo'r .o'rney into the 0or!d of digita! e!ectronics )y e amining the EAED and EG& gates+ &emem)er% the digita! re2o!'tion 0o'!d not )e possi)!e 0itho't these simp!e de2ices+

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! The transistor and in"erter

4earning o).ecti2es:
Ase the digita! trainer and )read)oard+ Assem)!e a circ'it+ >'i!d a !ogic circ'it 0ith discrete components+

The transistor
A transistor is a three-termina! de2ice that can )e 'sed as an amp!ifier or as a s0itch+ Bhen the transistor is 'sed as an amp!ifier% it is 0or#ing in ana!og mode+ Bhen it is )eing 'sed as an e!ectronic s0itch% it is f'nctioning in digita! mode+ ,he transistor 0i!! on!y )e 'sed in digita! mode in these !a)s% 0hich means the transistor 0i!! either )e on or off+ ,he terms gro'nd% !o0% 1ero% 1ero 2o!ts% open s0itch% and dar# !amp are a!! e('i2a!ent to the )oo!ean 2a!'e fa!se+ 4i#e0ise fi2e 2o!ts% high% one% c!osed s0itch% and !it !amp J!ight-emitting diode% 4EDK% are e('i2a!ent to the )oo!ean 2a!'e tr'e+ Be 0i!! 'se fa!se JF or 0K and tr'e J, or 1K 0hen spea#ing of the !ogica! states in this man'a!+ Modern comp'ters contain mi!!ions of transistors com)ined together in digita! mode to create ad2anced circ'its+ ,ransistors are three pin de2ices that are simi!ar to 2a!2es for contro!!ing e!ectricity+ ,he amo'nt of c'rrent that can f!o0 )et0een the co!!ector and emitter is a f'nction of the c'rrent f!o0ing thro'gh the )ase of the transistor+ If no c'rrent is f!o0ing thro'gh the )ase of the transistor% no c'rrent 0i!! f!o0 thro'gh the co!!ector and emitter+ Bith the transistor operating in digita! mode% it 0i!! )e config'red to carry the ma im'm Jif onK or minim'm Jif offK amo'nt of E hi)it 1+1: Common E"E transistors c'rrent from the co!!ector to the emitter that the circ'it 0i!! a!!o0+ ,he transistor 'sed in this !a)% the pn2222 or 2n2222% is an E"E% )ipo!ar .'nction transistor 0hich is sometimes referred to as a >J,+ Gther types of transistors e ist% and 0hi!e they differ in ho0 they f'nction% they are 'sed in a simi!ar manner in digita! circ'its+ In this !a)% a sing!e transistor 0i!! )e 'sed to create an in2erter+ ,he princip!es 'sed to )'i!d this in2erter co'!d )e app!ied to other circ'its 0ith other types of transistors+ "ino'ts of the t0o types of transistors most !i#e!y to )e 'sed in these !a)s are sho0n in E hi)it 1+1+

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1. The transistor and inverter

E hi)it 1+2: >read)oard

E hi)it 1+3: Common connections

The breadboard
In order to )'i!d the circ'it% a digita! design #it that contains a po0er s'pp!y% s0itches for inp't% !ight emitting diodes J4EDsK% and a )read)oard 0i!! )e 'sed+ Ma#e s're to fo!!o0 yo'r instr'ctor;s safety instr'ctions 0hen assem)!ing% de)'gging% and o)ser2ing yo'r circ'it+ Ho' may a!so need other items for yo'r !a) s'ch as: !ogic chips% 0ire% 0ire c'tters% a transistor% etc+ E hi)it 1+2 sho0s a common )read)oard% 0hi!e E hi)it 1+3 sho0s ho0 each set of pins are tied together e!ectronica!!y+ E hi)it 1+9 sho0s a fair!y comp!e circ'it )'i!t on a )read)oard+ For these !a)s% the highest 2o!tage 'sed in yo'r designs 0i!! )e fi2e 2o!ts or L:D and the !o0est 0i!! )e 0D or gro'nd+ A fe0 0ords of ca'tion regarding the 'se of the )read)oard:
<eep the po0er off 0hen 0iring the circ'it+ Ma#e s're to #eep things neat% as yo' can te!! from E hi)it 1+9% it is easy for designs to get comp!e and as a

res'!t )ecome diffic'!t to de)'g+

Do not strip more ins'!ation off of the 0ires 'sed than is necessary+ ,his can ca'se 0ires that are !ogica!!y

at different !e2e!s to accidenta!!y to'ch each other+ ,his creates a short circ'it+
Do not p'sh the 0ires too far into each ho!e in the )read)oard as this can ca'se t0o different pro)!ems+ ,he 0ire can )e p'shed so far that on!y the ins'!ation of the 0ire comes into contact 0ith the

)read)oard% ca'sing an open circ'it+

,oo m'ch 0ire is p'shed into the ho!eF it c'r!s 'nder and ends 'p to'ching another component at a

different !ogica! !e2e!+ ,his ca'ses a short circ'it+

Ase the !onger o'ter ro0s for L:D on one side and gro'nd on the other side+ Bire po0er to the circ'it first 'sing a common co!or Jsay redK for L:D and another J)!ac#K for gro'nd+ A!0ays ma#e s're to ha2e a c!ear!y doc'mented circ'it diagram )efore yo' start 0iring the circ'it+

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E hi)it 1+9: Comp!e circ'it

E hi)it 1+:: In2erter circ'it

The in"erter
,he in2erter% sometimes referred to as a EG, gate% is a simp!e digita! circ'it re('iring one transistor and t0o resistors+ ,he circ'it sho'!d )e connected as in E hi)it 1+:+ Ma#e s're to start 0ith a neat diagram in yo'r !a) note)oo# )efore yo' start constr'cting yo'r circ'itM ,he inp't is connected to a s0itch and the o'tp't connected to an 4ED+ ,he t0o resistors are c'rrent !imiting resistors and are si1ed to ins're that the circ'it operates in digita! mode+ If the in2erter circ'it is a!tered s!ight!y 0ith the addition of another transistor p!aced in series 0ith the c'rrent one% it res'!ts in one more inp't and the creation of a EAED gate+ 4i#e0ise% if another transistor is added in para!!e! 0ith the transistor in the in2erter circ'it a EG& gate can )e )'i!t+ ,hese t0o gates are disc'ssed at greater !ength in the ne t chapter+

&e2ie0 e ercises
1+ $#etch yo'r )read)oard+ Ma#e s're to indicate 0hich portions of the )oard are e!ectrica!!y connected in common+ 2+ Constr'ct a tr'th ta)!e for an in2erter 0ith x )eing the inp't and !x )eing the o'tp't+ 3+ Asing the co!or codes% determine the 2a!'e of each of the resistors+ 8int: Ho' may need to re2ie0 Appendi > if yo' are 'nfami!iar 0ith 'sing resistors+ JaK red% orange% red J)K )ro0n% )!ac#% orange JcK orange% orange% orange JdK )ro0n% )!ac#% green 9+ Bhat is the sym)o! 'sed for e!ectrica! gro'nd or 1ero 2o!tsC :+ Constr'ct a tr'th ta)!e for a EAED gate+ 5+ Constr'ct a tr'th ta)!e for a EG& gate+

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1. The transistor and inverter

"roced're
1+ Brite the pre!a) in yo'r !a) note)oo# for a!! the circ'its re('ired in the steps that fo!!o0+ 2+ G)tain instr'ctor appro2a! for yo'r pre!a)+ 3+ Dra0 a diagram of the in2erter circ'it+ 9+ Bith the po0er off on yo'r digita! trainer% constr'ct yo'r in2erter+ Apon comp!etion of the circ'it% yo' may 0ish to ha2e yo'r instr'ctor e amine it )efore t'rning the po0er on+ :+ =+ ,'rn po0er on for yo'r circ'it and 2erify the proper operation of the in2erter+ Asing a =909 series !ogic chip% connect one of the in2erters to demonstrate its operation+ Eote that 5+ Demonstrate the proper operation of the in2erter for yo'r instr'ctor+ Appendi A contains descriptions of the =900 series chips 'sed in the !a)s% inc!'ding the =909 in2erter chip+

Gptiona! e ercises
1+ Dra0 a diagram of a EAED in2erter circ'it 'sing t0o E"E transistors+ 2+ Constr'ct the EAED circ'it+ 3+ Derify proper operation of the EAED gate+ 9+ Demonstrate the proper operation of the EAED for yo'r instr'ctor+

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# Logic gates
4earning o).ecti2es:
Ase =900 series chips in designing digita! !ogic f'nctions+ Dra0 comp!ete circ'it diagrams+ Constr'ct and de)'g digita! !ogic circ'its 'sing =900 series chips+

$istory of logic chi%s

4ogic gates co'!d )e constr'cted from transistors and resistors .'st as the in2erter 0as constr'cted in the !ast !a)+ 8o0e2er% 'sing discrete transistors to )'i!d !ogic gates can )e time cons'ming and prone to pro)!ems as increasing the n'm)er of connections a!so increases the possi)!e points of fai!'re+ >efore the ad2ent of the transistor% and today in certain ind'stria! app!ications% !ogic gates are created 'sing mechanica! re!ays+ Mechanica! de2ices s'ffer from simi!ar pro)!ems a!ong 0ith the added comp!ication that s'ch de2ices genera!!y cannot )e s0itched from one state to another ('ic#!y eno'gh for modern comp'ter app!ications+ ,he introd'ction of the integrated circ'it in the !ate 17:0s aimed at p!acing many indi2id'a! circ'it components in a sing!e pac#age that had a!! of the connections se!f-contained in si!icon+ ,his re2o!'tioni1ed the comp'ting ind'stry and has !ed to C"As today that contain mi!!ions of components in a sing!e chip+ Ho' 0i!! 'se =900 series !ogic chips in this man'a!+ ,his series of chips has )een man'fact'red since the 1750s+ ,hese chips 0ere 'sed to design and )'i!d comp'ters d'ring that timeF ho0e2er% they are rare!y 'sed in comp'ters )'i!t today+ Despite this% they sti!! ha2e many 'ses Jin addition to .'st teaching st'dents digita! !ogicK+ ,hey are sti!! prod'ced% easy to o)tain and are fair!y ine pensi2e+ ,he chips come in 2ario's pac#ages% )'t the pac#age 'sed in these !a)s is a d'a! in-!ine pac#age% other0ise #no0 as a DI" as sho0n in E hi)it 2+1+ In order to determine the po!arity of the chip% a notch is p't on one side of the chip+ From a top 2ie0% pin one is on the !eft of the notch 0ith other pins n'm)ered se('entia!!y in a co'nter c!oc#0ise manner+ Chips may a!so ha2e a dot p!aced near pin one+ "ino'ts of the chips that 0i!! )e 'sed in the !a)s can )e fo'nd in Appendi A+ Chips in the =900 fami!y are constr'cted 'sing a 2ariety of different E hi)it 2+1: =900 EAED DI"

circ'it config'rations that a!! ha2e different properties+ $ome 'ti!i1e >J, and others% fie!d effect transistors JFE,sK+ ,he different series JC% 8C% 4% $% 4$% etc+ 0ithin the =900 fami!yK are designed 0ith s'ch considerations as the need for !o0 po0er cons'mption% s0itching speed% or re!ia)i!ity 'nder stressf'! en2ironments that might )e inc'rred in mi!itary app!ications+ Cons'!t Appendi E for fami!ies that are appropriate for these !a)s+

Style Guidelines

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2. Logic gates

Logic symbols
As mentioned in the pre2io's !a)% EAED and EG& gates can )e constr'cted 0ith fe0er components than AED and G& gates+ For this reason% the in2erter% EAED and EG& ma#e 'p fo'r of the se2en chips 'sed in a!! of the !a)s+ $ym)o!s 'sed to represent the EAED% EG&% AED% G& and in2erter or EG, are pro2ided a!ong 0ith the tr'th ta)!es for the EAED and EG&+ ,he tr'th ta)!es ha2e ?0@ representing fa!se and @1@ representing tr'e+ A circ'it that can )e 'sed to create a EAED gate 'sing t0o transistors is sho0n in E hi)it 2+=+ Circ'it config'rations for EAED gates pro2ided )y the =900 series chips% 0hi!e !ogica!!y e('i2a!ent% 2ary from this design+

E hi)it 2+2: EAED

E hi)it 2+3: EG&

E hi)it 2+9: In2erter

A 0 0 1 1

B 0 1 0 1

Y 1 1 1 0

A 0 0 1 1

B 0 1 0 1

Y 1 0 0 0
E hi)it 2+5: G& E hi)it 2+:: AED

,a)!e 1: EAED ta)!e

,a)!e 2: EG& ta)!e

E hi)it 2+6: A; AED > Eotice that on!y the sma!! circ!e is 'sed to indicate the in2ersion of the AED to prod'ce the EAED instead of 'sing the f'!! in2erter sym)o! in E hi)it 2+2+ ,his shorthand is often 'sed at the inp't of a gate% sho0n in E hi)it 2+6 0hich is e('i2a!ent to JA; AED >K+

E hi)it 2+=: EAED circ'it $ince the EAED gate is 'sed more often% ho0 do yo' o)tain a simp!e AED or G& gateC Gne 0ay 0o'!d o)2io's!y )e to simp!y com)ine a EAED gate a!ong 0ith an in2erter as in E hi)it 2+7+ Bhi!e this 0or#s% as each chip contains more than one gate% if an e tra EAED is a2ai!a)!e% it may )e more ad2antageo's to 'se a spare gate rather than to 'se an entire!y ne0 chip as in E hi)it 2+10+

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,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

E hi)it 2+7: EAED in2erter yie!ds AED

E hi)it 2+10: EAED EAED to yie!d AED

Logical functions
E hi)it 2+11 demonstrates ho0 to imp!ement a simp!e !ogica! e pression 'sing the gates pro2ided+ Ma#e s're to 'se on!y those gates that are pro2ided in yo'r #it 0hen designing yo'r circ'it+ ,his diagram imp!ements the f'nction fJA%>%CK N A> L >C+ $ince there are three inp'ts to this f'nction% there are eight possi)!e !ogica! inp't conditions as sho0n in the tr'th ta)!e+

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

f 0 0 0 1 0 0 1 1
E hi)it 2+11: A> L >C

,a)!e 3: A> L >C Bhen )'i!ding a !ogica! circ'it% it is important to doc'ment the circ'it diagram as sho0n a)o2e+ 8o0e2er% e2en this diagram co'!d )e made c!earer for those attempting to )'i!d and de)'g the circ'it+ E hi)it 2+12 yie!ds a m'ch more detai!ed description of ho0 the circ'it sho'!d )e )'i!t+ Ho' sho'!d inc!'de a diagram for e2ery circ'it that yo' )'i!d in yo'r !a) note)oo# and yo' sho'!d fo!!o0 the format in E hi)it 2+12+ 4et 's e amine the type of information contained here+ First% chips are !a)e!ed as IC1% IC2 and IC3+ ,hen a !egend is inc!'ded that specifies the type of chip for each of the IC or integrated circ'its+ ,he IC n'm)ers sho'!d appear in the order that they 0i!! appear in yo'r )read)oard from !eft to right or top to )ottom% depending 'pon ho0 the )read)oard is config'red in yo'r digita! trainer+ $econd% the pins 'sed for each connection on the chip are a!so gi2en% 0hich ma#es connecting the circ'it possi)!e 0itho't ha2ing to contin'a!!y cons'!t the datasheet for that !ogic chip+ ,hird% the s0itches and 4EDs are !a)e!ed in the order that they are 'sed for the respecti2e inp'ts and o'tp'ts+ A!! of this Style Guidelines E hi)it 2+12: Detai!ed 0iring diagram for A>L>C 1: A -!o)a! ,e t

2. Logic gates ma#es it m'ch easier to constr'ct and demonstrate the circ'it+ >'t a)o2e a!!% the greatest )enefit comes if the circ'it does not 0or# and needs to )e de)'ggedM In this case% 0ith a!! of the pins c!ear!y !a)e!ed on yo'r diagram% it is m'ch easier for someone to e amine yo'r circ'it% compare it to yo'r diagram% trace the 2ario's connections and hopef'!!y find and correct any pro)!ems in the circ'it+ 4A> EG,E>GG< ,I": In addition to the circ'it diagram% a!0ays p't a tr'th ta)!e in yo'r !a) note)oo# to ma#e it easier to de)'g and test the operation of yo'r circ'it+ ,his circ'it 0o'!d re('ire three different =900 series !ogic chips and ten different connections% yet if designed 0ith indi2id'a! transistors 'sing the in2erter from the !ast !a)% as 0e!! as the EAED circ'it sho0n in E hi)it 2+=% this 0o'!d ta#e nine different transistors% fifteen resistors% and many more connections than if .'st the chips 0ere 'sed+ It is no 0onder that the decrease in comp!e ity of digita! circ'its that fo!!o0ed the introd'ction of the =900 series chips !ed to a re2o!'tion in the comp'ting ind'stryM 4et 's e amine one more simp!e circ'it+ ,his one is 'sed to imp!ement an e c!'si2e or JOG&K% 0hich is represented )y the sym)o! in !ogica! e pressions+ ,he tr'th ta)!e for A OG& > fo!!o0s a!ong 0ith the gate 'sed to represent it in circ'it diagrams+ As no OG& chip is pro2ided in the #it% in order to imp!ement this circ'it% the OG& m'st )e )'i!t )y e amining the tr'th ta)!e to find the res'!ting !ogica! f'nction% A;> L A>;+ ,he circ'it diagram for the OG& is sho0n in E hi)it 2+19+ &emem)er% a diagram s'ch as this sho'!d )e inc!'ded in yo'r !a) man'a! to ease constr'ction and de)'gging of the circ'it+

A 0 0 1 1

B 0 1 0 1

0 1 1 0
E hi)it 2+13: OG&

,a)!e 9: OG& ta)!e

E hi)it 2+19: Circ'it diagram for OG&

Be 0i!! disc'ss ho0 to )'i!d more comp!icated circ'its in the ne t chapter% as 0e!! as ho0 to !ogica!!y simp!ify the f'nctions 0ith >oo!ean a!ge)ra+ >oth circ'its designed in this chapter can )e simp!ified significant!y 0ith the 'se of De Morgan;s !a0% a!so disc'ssed in the ne t chapter+

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,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

&e2ie0 e ercises
1+ If a !ogic f'nction has three inp'ts% ho0 many ro0s m'st the tr'th ta)!e ha2e to contain a!! possi)!e statesC J'stify yo'r ans0er+ 2+ &epeat the !ast pro)!em for fi2e inp'ts+ 3+ For the fo!!o0ing f'nctions% constr'ct a tr'th ta)!e and dra0 a circ'it diagram+ JaK yJA%>K N JA>K; L >; J)K yJA%>%CK N JA L >K; C JcK yJA%>%CK N JACK; L >C JdK yJA%>%CK N JA >KC; JeK yJA%>K N A; L > JfK yJA%>%CK N JJAL>K;J>LCK;K; 9+ For 3JeK of the pre2io's e ercise% design the circ'it 'sing =900 series chips !isted in Appendi A+ 4a)e! the pino'ts on the circ'it diagram+ Ma#e s're to !a)e! a!! of the pino'ts% .'st as in E hi)it 2+19+ :+ &epeat e ercise 9 'sing 3JfK+

"roced're
1+ Brite the pre!a) in yo'r !a) note)oo# for a!! circ'its re('ired in the steps that fo!!o0+ 2+ G)tain instr'ctor appro2a! for yo'r pre!a)+ 3+ Assem)!e one sing!e EAED gate from a =900 chip and 2erify its operation+ 9+ Assem)!e one sing!e EG& gate from a =902 chip and 2erify its operation+ :+ >'i!d the circ'it re('ired for E ercise 9 from the re2ie0 e ercises+ Ma#e s're to ha2e yo'r instr'ctor 2erify that yo'r circ'it 0or#s correct!y )efore mo2ing on+ 5+ >'i!d the circ'it re('ired for E ercise : from the re2ie0 e ercises+

Gptiona! proced're
1+ Design% constr'ct% and 2erify the operation of the circ'it from E ercise : 'sing on!y EAED gates+

Style Guidelines

1=

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,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

& Logic sim%lification

4earning o).ecti2es:
Ase red'ction techni('es to o)tain minima! f'nctiona! representations+ Design minima! three and fo'r inp't !ogica! f'nctions+ >'i!d and de)'g three and fo'r inp't !ogica! f'nctions+

De 'organ(s laws
As yo' o)ser2ed in the pre2io's !a)% managing the n'm)er of connections Jor 0iresK in yo'r circ'it can )ecome a cha!!enge+ ,his cha!!enge seems to increase e ponentia!!y as the n'm)er of components in the circ'it increases+ In order to #eep yo'r )read)oard as neat as possi)!e and yo'r design as simp!ified as possi)!e% it is often ad2antageo's to spend time e amining the !ogica! f'nction for 0ays to red'ce the comp!e ity of the fina! design+ &ed'cing the n'm)er of gates in a circ'it 0i!! genera!!y !ead to a red'ction in the n'm)er of connections% res'!ting in a simp!er circ'it+ Designs 0ith fe0er connections and parts ha2e fe0er possi)!e points of fai!'re+ 4ess comp!e circ'its are genera!!y easier and cheaper to )'i!d and de)'g+ In this chapter% techni('es 0i!! )e introd'ced that can he!p to imp!ement comp!e circ'its in the !east comp!e manner possi)!e+ It is often possi)!e to imp!ement !ogica! f'nctions correct!y in many different 0ays+ ,he first step in o)taining a !ogica!!y minima! e pression sho'!d )e a c!ear 'nderstanding of the r'!es of >oo!ean a!ge)ra !isted in Appendi D+ De Morgan;s !a0s in partic'!ar can )e 2ery he!pf'! 0hen attempting to simp!ify circ'it design+ De Morgan;s !a0s are !isted )e!o0+ (AB)' = A' + B' (A+B)' = A'B' -i2en these t0o e('ations% it is easy to see the a!ternate sym)o!s that are sometimes 'sed for the AED and G& gates !isted in and + App!ying De Morgan;s !a0s to the f'nctions !isted yie!ds the fo!!o0ing+ JA; L >;K; N JA>;K; N A> JA;>;K; N JJA L >K;K; N A L >

E hi)it 3+1: A!ternate AED sym)o!

E hi)it 3+2: A!ternate G& sym)o!

An e amp!e of 'sing De Morgan;s !a0s for simp!ification can )e fo'nd )y e amining the !ogica! f'nction: A> L >C from the pre2io's chapter+ ,his f'nction can act'a!!y )e imp!emented 0ith .'st three EAED gates and one =900 chip+ E amining the e('ation A> L >C )e!o0 and app!ying De Morgan;s !a0 demonstrates that the e pression can )e imp!emented 0ith on!y EAED gates+ A> L >C N J JA> L >CK; K ; N J JA>K; J>CK; K; 'ou"le (e!ative 'e )or!an*s law

Eotice that the first e pression e act!y matches the f'nction that 0as )'i!t in the pre2io's chapter 'sing t0o EAEDs% one EG& and three in2erters+ ,he ne0 circ'it sho0n in E hi)it 3+3 imp!ements the same e pression 0ith .'st three EAED gates+ ,his res'!ts in a design 'sing on!y one =900 series chip and fe0er connections that sti!! Style Guidelines 16 A -!o)a! ,e t

3. Logic simplification yie!ds the same res'!t+ Designs 0ith fe0er chips and 0ires genera!!y ta#e !ess time to )'i!d% res'!ting in !ess e pensi2e% more ro)'st circ'its+ $imi!ar!y% the circ'it that imp!ements the OG& from the !ast chapter co'!d )e )'i!t 0ith .'st EAED gates% ho0e2er as fi2e gates 0o'!d )e re('ired% it sti!! 0o'!d 'se t0o chips% one =900 and a =909+

)arnaugh ma%s
<arna'gh maps or <-maps for short% pro2ide another means of simp!ifying and optimi1ing !ogica! e pressions+ ,his is a graphica! techni('e that 'ti!i1es a s'm of prod'ct J$G"K form+ $G" forms com)ine terms that ha2e )een E hi)it 3+3: A> L >C JEAED$ on!yK

AEDed together that then get G&ed together+ ,his format !ends itse!f to the 'se of De Morgan;s !a0 0hich a!!o0s the fina! res'!t to )e )'i!t 0ith on!y EAED gates+ ,he <-map is )est 'sed 0ith !ogica! f'nctions 0ith fo'r or !ess inp't 2aria)!es+ As the techni('e genera!!y )ecomes 'n0ie!dy 0ith more than fo'r inp'ts% other means of optimi1ation are genera!!y 'sed for e pressions of this comp!e ity+ Bhi!e it can )e more instr'cti2e for st'dents to 'se >oo!ean a!ge)ra red'ction techni('es% 0hen minimi1ing gate circ'itF it is !ess o)2io's for st'dents to recogni1e 0hen they ha2e reached the simp!est circ'it config'ration+ Gne of the ad2antages of 'sing <-maps for red'ction is that it is easier to see 0hen a circ'it has )een f'!!y simp!ified+ Another ad2antage is that 'sing <-maps !eads to a more str'ct'red process for minimi1ation+ In order to 'se a <-map% the tr'th ta)!e for a !ogica! e pression is transferred to a <-map grid+ ,he grid for t0o% three% and fo'r inp't e pressions are pro2ided in the ta)!es )e!o0+ Each ce!! corresponds to one ro0 in a tr'th ta)!e or one gi2en state in the !ogica! e pression+ ,he order of the items in the grid is not random at a!!F they are set so that any ad.acent ce!! differs in 2a!'e )y the change in on!y one 2aria)!e+ >eca'se of this% items can )e gro'ped together easi!y in rectang'!ar )!oc#s of t0o% fo'r% and eight to find the minima! n'm)er of gro'pings that can co2er the entire e pression+ Eote that diagona! ce!!s re('ire that the 2a!'e of more than t0o inp'ts change% and that they a!so do not form rectang!es+

A'B' A'B AB
00 01 11

AB'
10

A'
0

A
1

A'B' A'B AB
00 01 11

AB'
10

C'D'
00 01 11

B'
0 1

C'
0

C'D CD CD'
10

C
1

,a)!e 5: 2 inp't <-map

,a)!e =: 3 inp't <-map

,a)!e :: 9 inp't <-map E amine the e pression fJA%>%CK N A>C L A>C; L A;>C L A;>C;+ As !isted% it re('ires fo'r three-inp't AED gates% one fo'r-inp't G& gate and se2era! in2erters+ ,he tr'th ta)!e is copied o2er to the eight ce!! <-map )e!o0+ Eotice the s('are of ones in the center of the <-map+ ,hese ce!!s a!! share the fact that they are tr'e 0hen > is tr'e+ And indeed% the e pressions sho0n )e!o0 are e('i2a!ent+ 17

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 f 0 0 1 1 0 0 1 1 E hi)it 3+9: <-map of fJA%>%CK Distri)'ti2e "roperty C L C; is a!0ays tr'e Distri)'ti2e "roperty A L A; is a!0ays tr'e

,a)!e 6: fJA%>%CK

A>C L A>C; L A;>C L A;>C; N A>JC L C;K L A;>JC L C;K N A> L A;> N JA L A;K> N>

Gf co'rse% imp!ementing the !ogica! e pression > is m'ch simp!er than the pre2io's e pressionM A!tho'gh r'!es of !ogic app!ied a)o2e yie!d the same res'!t% it is often m'ch easier to note the gro'pings that res'!t in minima! e pressions 'sing the graphica! representation of the <-map+ 4et 's e amine the e('ation gJA%>%C%DK gi2en in the tr'th ta)!e in ,a)!e = 0ith the associated <-map+ ,he e pression contains three different terms: A;>;% AC% and A>C;D circ!ed in E hi)it 3+:+ 8o0e2er% this is not the minima! e pression )eca'se not a!! of the !argest possi)!e gro'pings are inc!'ded+ In order to o)tain the !argest gro'pings% it is often necessary to o2er!ap some of the terms+ ,his .'st ca'ses certain terms to )e inc!'ded in more than one gro'ping as sho0n in E hi)it 3+5+ Eotice term A>CD 0hich is act'a!!y inc!'ded in t0o different gro'pings% A>D and AC% 0hich is perfect!y accepta)!e+ Asing the ne0 gro'pings% 0e o)tain the minima! $G" e pression gJA%>%C%DK N A;>; L AC L A>D+ ,his e pression contains the same n'm)er of gro'pings or prod'cts% )'t one !ess term in one of the prod'cts+ In this case A>C;D from E hi)it 3+: is rep!aced 0ith A>D in E hi)it 3+5 yie!ding a simp!er e pression+ Bhi!e other techni('es e ist for finding minima! e pressions% 0ith some practice% the <-map can )e 'sed effecti2e!y for e pressions 0ith fo'r or !ess inp'ts+ Eot se!ecting the !argest gro'ping is a 2ery common error to those .'st )eginning to 'se <-maps+ &emem)er% a!0ays se!ect the !argest gro'ping possi)!e% e2en if it res'!ts in some terms )eing do')!e co2ered+ 4arger gro'pings res'!t in simp!er e pressions+

Style Guidelines

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3. Logic simplification

A B C D g
0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
E hi)it 3+:: <-map of gJA%>%C%DK

0 1

0 0 0 0 1 1 1 1 0 0

0 0 0 0 0 0 1 0 1 0 1 1 1 1 1 1 0 1 1 1 1
In s'mmary% the proced're for 'sing <-maps to find minima! !ogica! e pressions is gi2en )e!o0+ 1+ Constr'ct the <-map corresponding to the tr'th ta)!e+ 2+ Circ!e any 1 that is EG, ad.acent Jiso!atedK to any other 1+ 3+ Find any 1 that is ad.acent to only one other+ ,hen circ!e these pairs% e2en if one in the pair has a!ready )een circ!ed+ 9+ Circ!e any gro'p of eight JoctetK% e2en if a 1 in the gro'p has a!ready )een circ!ed+ :+ Circ!e any gro'p of fo'r J('adK that contains one or more one 1 that is not a!ready circ!ed+ 5+ Ma#e s're that e2ery 1 is circ!ed+ =+ Form the G& s'm of the terms generated )y each gro'ping+

0 0 0 0 1 1 1 1 0 1

,a)!e 7: gJA%>%C%DK

E hi)it 3+5: <-map of gJA%>%C%DK

,he fo!!o0ing e amp!e goes thro'gh a!! the steps in order to find the minima! e pression for hJA%>%C%DK+ First% the tr'th ta)!e gi2en in ,a)!e 6 is transcri)ed to fit into the <-map gi2en in ,a)!e :+

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,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

A'B' A'B AB

AB'
10

A'B' A'B AB
00 01 11

AB'
10

A B C D g
0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 C'D'
00 01 11

00

01

11

C'D'
00 01 11

0 1 0 0

1 1 1 0

1 1 0 0

0 1 0 1

C'D'
00 01 11

0 1 0 0

1 1 1 0

1 1 0 0

0 1 0 1

C'D CD CD'
10

C'D CD CD'
10

0 0

0 0 1 0 1 1 1 1 0 0

,a)!e 11: hJ0% %y%1K

,a)!e 13: $tep 2 In step 2% a)o2e% the 1 in the )ottom right is shaded+ In step 3% to the !eft% the pair of t0o 1s in the second co!'mn is

0 0 0 0 0 0 1 0 1 0 1 1 1 1 1 1 0 1

A'B' A'B AB
00 01 11

AB'
10

shaded+ Eote that the )ottom item A;>CD dictates that this gro'p is circ!ed+ ,he top item% A;>C;D has many different ad.acent e!ements% )'t the first 1 on!y has one ad.acent e!ement+ For step 9% no gro'ps of eight e ist% so there is no ta)!e+ For step :% t0o gro'ps of fo'r e ist% C;D and >C;+

0 0 1 0 1 1 1 1 1 0 0 0

0 1 0 0

1 1 1 0

1 1 0 0

0 1 0 1

C'D CD CD'
10

,a)!e 10: hJA%>%C%DK

,a)!e 12: $tep 3

A'B' A'B AB
00 01 11

AB'
10

C'D'
00

0 1 0 0

1 1 1 0

1 1 0 0

0 1 0 1

C'D
01

CD
11

CD'
10

,a)!e 19: $tep : Eote that )oth of these gro'pings co2er e!ements a!ready co2ered from step 2 and that )oth share the gro'p of t0o% >C;D+ ,his o2er!ap is shaded in green+ ,his is not on!y perfect!y accepta)!e% )'t re('ired to o)tain the minima! e pression+ Eo0% a!! of the 1s are co2ered% yie!ding the minima! so!'tion+ hJA%>%C%DK N A>;CD; L A;>D L >C; L C;D

Style Guidelines

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3. Logic simplification

Circuit design* construction and debugging

Bhi!e these techni('es are 'sef'! in minimi1ing the !ogica! e pression% '!timate!y the circ'its sti!! need to )e constr'cted+ As the comp!e ity of the circ'its increases% it is important to note some of the techni('es that can )e 'sef'! in )'i!ding a comp!ete 0or#ing circ'it+ DE$I-E ,I": ,he time spent in the design stage can pay huge di2idends !aterM Mista#es made at the )eginning of the design phase carry thro'gh the entire process and can cons'me co'nt!ess ho'rs trying to de)'g the fina! prod'ct+
$tart )y ma#ing s're that the circ'it minimi1ation 0as correct and copied in yo'r !a) note)oo#+ ,he tr'th

ta)!e is he!pf'! 0hen testing the fina! circ'it+ >'i!ding the 0rong circ'it ser2es no p'rpose at a!!+
Derify that the pino'ts se!ected are proper for each gate and chipF these are he!pf'! 0hen de)'gging as 0e!!

as 0hen )'i!ding the circ'it+ Again% time spent here he!ps c't do0n on the constr'ction and de)'gging !ater+
&emem)er the tips gi2en in the chapter ?,he transistor and the in2erter@ regarding the 'se of the

)read)oard+
<eep connecting 0ires neat!y and a2oid 'nnecessari!y !ong !oops of 0ire% yet do not spend e cessi2e time

c'tting 0ires that are e#actly the proper !ength )et0een spans+ It may fee! !i#e a 0or# of art% )'t in the end yo' 0ant a neat circ'it that 0or#s proper!y+ If you !" !u"# does no# $o % & o&e ly'
Attempt to reason o't the pro)!em+ Does the circ'it act re!ia)!yC Does it a!0ays prod'ce the same 0rong res'!tC If so% then the error is !i#e!y in the !ogic+ If it yie!ds different res'!ts at different times% a !oose connection is 2ery !i#e!y+ If t0o o'tp't !ines are

connected together J0hich sho'!d ne2er )e doneK% it can a!so res'!t in 'npredicta)!e o'tp'ts+
,est each component of the circ'it independent!y+ For e amp!e% if yo' ha2e the e pression A>; L A>CD L

A>C; )'i!t 0ith EAED gates and in2erters% first test that the inp't and o'tp't of JA>;K; is 0or#ing correct!y+ ,hen mo2e onto each s'cceeding term+
Derify the circ'it has po0er and gro'nd to a!! of the appropriate pins for each chip+ Derify that a!! of the pins are connected proper!y+ Ma#e s're that they fo!!o0 0hat is specified in yo'r circ'it diagrams+ Ma#e s're that none of the o'tp't pins are tied together+ If each of the o'tp't pins 0ere to o)tain a

different 2a!'e% this co'!d res'!t in a !ogic high )eing tied direct!y to a !ogic !o0 !e2e!+ At )est% this can res'!t in an indeterminate 2a!'e+ ,his 0i!! res'!t in f'rther pro)!ems if this o'tp't is then 'sed as an inp't for another gate+
&emem)er that often things do not 0or# the first time 0hen yo' )'i!d them+

DE>A--IE- ,I": Do no# allo$ you self #o ge# f us# a#ed! ,his is easier said than done% )'t getting 'pset does not ser2e any p'rpose in effecti2e tro')!eshooting+ If you ha(e done all of #he a)o(e and #he !" !u"# s#"ll does no# $o %'
&et'rn to the design phase and 2erify that yo'r minimi1ation and pino'ts are correct+

23

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

$ometimes errors come from the components or e('ipment themse!2es+ Errors s'ch as those !isted )e!o0

can occ'r% )'t are very rare+ ,hese sho'!d )e considered as a !ast resort and other ca'ses of error sho'!d )e in2estigated )efore !oo#ing for the fo!!o0ing errors:
A pin on a DI" can )ecome )ent and c'r! 'nder the chip so that it does not get inserted into the

)read)oard+ ,his is diffic'!t to see 0itho't ta#ing the chip o't and e amining its !egs+
In genera!% so!id state de2ices are 2ery re!ia)!e 0hen operated 'nder proper temperat're ranges% )'t

2ery occasiona!!y a chip may )e fa'!ty+

Connecting 0ires can )e sp!it inside of the ins'!ation+ Bhen this occ'rs% the ins'!ation 0i!! ca'se the

0ire to !oo# as tho'gh it is intact% )'t if the copper is in t0o pieces inside the ins'!ation% c'rrent 0i!! not f!o0 and the 0ire 0i!! act'a!!y )e open+
Fa'!ty test e('ipment can ad2erse!y effect the circ'it )eing tested and !ead one to )e!ie2e a circ'it is

ma!f'nctioning 0hen it is not% or gi2e yo' other fa!se information that !eads yo' do0n the 0rong path in yo'r reasoning+
As# for he!p from fe!!o0 c!assmates and yo'r instr'ctor+ ,a#e a )rea# and come )ac# to the pro)!em+ Eo one 0or#s at their )est 0hen they are tota!!y aggra2ated+

&e2ie0 e ercises
1+ Design a 9-inp't EAED gate 'sing t0o 2-inp't EAED gates and one 2-inp't EG& gate+ 8int: Ase DeMorgan;s !a0+ 2+ Bhat are the possi)!e gro'pings in a 9-inp't <-mapC $#etch their shapes+ 3+ Constr'ct a tr'th ta)!e for the fo!!o0ing f'nctions: JaK fJA%>%CK N A> L A;>C; L A>;C J)K gJA%>%CK N A;C L A>C L A>; JcK hJA%>%C%DK N A;>C; L JA >KC L A;>;C;D L A>CD JdK .JA%>%C%DK N A;C;D; L C;D L CD 9+ Constr'ct the <-map for each of the f'nctions from the pre2io's pro)!em and determine the minima! e pression for each+ :+ For 3J)K% design the circ'it for the minima! $G" e pression fo'nd in pro)!em 9 'sing .'st EAED gates and in2erters+ 4a)e! the pino'ts on the circ'it diagram+ 5+ For 3JcK% design the circ'it for the minima! $G" e pression fo'nd in pro)!em 9 'sing .'st EAED gates and in2erters+ 4a)e! the pino'ts on the circ'it diagram+ =+ JaK -i2en each of the <-maps% determine the minima! e pression associated 0ith it+ J)K

A'
0

A
1

A'B' A'B AB
00 01 11

AB'
10

B'
0 1

1 1

1 0

C'
0 1

1 0

1 1

1 0

1 0

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3. Logic simplification JcK JdK

A'B' A'B AB
00 01 11

AB'
10

A'B' A'B AB
00 01 11

AB'
10

C'D'
00

1 1 0 0

1 1 0 0

1 1 1 1

1 0 1 1

C'D'
00 01 11

0 1 0 1

0 1 1 1

0 0 0 0

0 1 1 0

C'D
01

C'D CD CD'
10

CD
11

CD'
10

"roced're
1+ Brite the pre!a) in yo'r !a) note)oo# for a!! the circ'its re('ired in the steps that fo!!o0+ 2+ G)tain instr'ctor appro2a! for yo'r pre!a)+ 3+ >'i!d the circ'it re('ired for E ercise : from the re2ie0 e ercises+ JaK Ma#e s're to test each of the portions of the e pression independent!y+ Meaning% test the o'tp't of each of the first !e2e! EAED gates to 2erify that each 0or#s )efore testing the fina! o'tp't+ J)K Demonstrate the 0or#ing circ'it for yo'r instr'ctor+ 9+ &epeat the steps from the !ast proced're for E ercise 5 of the re2ie0 e ercises+

2:

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

+ 'ore logic sim%lification

4earning 0).ecti2es:
&e2ie0 a!! possi)!e <-map gro'pings+ Ase ?don;t care@ conditions in minimi1ation+

,dditional )-ma% grou%ings

$ome of the rectang'!ar gro'pings a!!o0ed for <arna'gh maps% s'ch as the one in E hi)it 9+1% are not o)2io's+ Ce!!s on )orders act'a!!y are ad.acent to ce!!s on the opposite )order% 0hich prod'ce gro'pings that may not appear contin'o's+ ,his gro'ping of t0o ce!!s act'a!!y forms a rectang!e represented )y >;C;% e2en tho'gh this rectang!e is sp!it+

E hi)it 9+1: <-map gro'ping ,he possi)i!ities for non-o)2io's gro'ps increase for <-maps 0ith fo'r-inp't f'nctions+ E hi)it 9+2 sho0s >;D% a fo'r ce!! s('are gro'ping that is sp!it on the t0o side )orders+ In E hi)it 9+3% the eight ce!! rectang'!ar gro'ping D; is sho0n+ Gne of the most non-o)2io's fo'r ce!! gro'pings that contains a!! fo'r corners is sho0n in E hi)it 9+9+ ,he interested reader can 2erify that the minima! e pressions for E hi)it 9+2% 9+3 and 9+9 are >;DLA;DLA;>;C% D;LA>;LA;C; and >;D;LA;>DLA;CD respectf'!!y+

E hi)it 9+2: 9-e!ement gro'p

E hi)it 9+3: 6-e!ement gro'p

E hi)it 9+9: Fo'r corner gro'p

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4. More logic simplification

In%ut %lacement on )-ma%

A!! of the <-maps sho0n so far ha2e had the inp't 2aria)!es A and > set a!ong the top 0ith the inp't 2aria)!es C and D a!ong the side+ ,his does not need to )e the case% )'t it is the con2ention 'sed here+ In addition% the inp'ts ha2e 'sed the gray code 00 -P 01 -P 11 -P 10% 0hich does not need to )e the case either+ For e amp!e% the inp't se('ence co'!d ha2e )een 00P10-P11-P01 0hi!e sti!! on!y changing one inp't at a time+ A!tho'gh a!tering these con2entions 0i!! sti!! !ead to the e act same minima! e pressions% it is disco'raged )eca'se 0hen 2erifying res'!ts% it can often !ead to conf'sion+ >y a!tering the con2ention% yo' co'!d ca'se those trying to assist yo' to spend e tra time 0hen e amining yo'r 0or#+ ,he fo!!o0ing e amp!e i!!'strates ho0 the same representation 0i!! )e o)tained despite E hi)it 9+:: 6-inp't <-map gro'ping

the ordering of the inp't 2aria)!es+ In E hi)it 9+: the same f'nction is represented as in E hi)it 9+3+ In this case% the region high!ighted for D; does not span t0o )o'ndaries% 0hi!e the gro'ping for A;C; does in this format+ Again% it can )e sho0n that the same minima! e pression is o)tained: D; L A;> L A;C;+

Don(t care conditions

Bhi!e a!! inp't cases for a !ogica! f'nction m'st )e considered% in an act'a! design it often occ'rs that certain cases ne2er e ist+ For instance% a partic'!ar co'nter that cyc!es thro'gh the states 1ero thro'gh fi2e 0o'!d ne2er reach states si J110K and se2en J111K+ In s'ch cases% it can )e ad2antageo's to fi!! the spots 0ith a don;t care condition JdK+ ,he don;t care can then )e inc!'ded 0ith a gro'ping if it he!ps to minimi1e the fina! !ogica! representation% other0ise it can )e treated as fa!se+ Consider the e amp!e in E hi)it 9+5+ If on!y the ones are gro'ped% the minima! e pression is C;D; L A;>C; L >D;+ 8o0e2er% if the don;t care conditions are a!!o0ed to )e gro'ped 0ith ones% the res'!ting minima! e pression is > L C;D;+ &emem)er that the presence of a don;t care condition does not re('ire that this ce!! )e co2ered in the fina! o'tp't+ E hi)it 9+= demonstrates this case+ Eote% t0o of the don;t cares are inc!'ded to yie!d a minima! representation of C;+ ,he don;t care a!ong the )ottom is not inc!'ded at a!!+

E hi)it 9+=: Don;t care not co2ered

E hi)it 9+5: Don;t care conditions

2=

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

&e2ie0 e ercises
1+ -i2en each of the <-maps% determine the minima! $G" e pression+ d represents a don;t care condition+ JaK J)K

A'B' A'B AB
00 01 11

AB'
10

A'B' A'B AB
00 01 11

AB'
10

C'
0

d 1

0 0

1 0

1 d

C'
0

0 1

0 d

1 d

1 1

C
1

C
1

JcK

JdK

A'B' A'B AB AB'

00 01 11 10

A'B' A'B AB
00 01 11

AB'
10

C'D'
00

0 0 1 1

0 0 0 0

0 1 1 0

1 1 1 1

C'D'
00

1 0 0 1

1 1 1 1

0 0 0 0

1 0 0 1

C'D
01

C'D
01

CD
11

CD
11

CD'
10

CD'
10

JeK

JfK

A'B' A'B AB
00 01 11

AB'
10

A'B' A'B AB
00 01 11

AB'
10

C'
0

1 0

1 1

0 1

1 0

C'D'
00

1 1 0 1

1 1 0 1

0 1 0 0

0 1 0 0

C
1

C'D
01

CD
11

CD'
10

2+ For the f'nctions !isted )e!o0% constr'ct a <-map and determine the minima! $G" e pression+ JaK fJa%)%cK N a;);c; L a;)c; L a)c; L a)c J)KgJa%)%cK N a);c; L a)c; L a)c L don;t caresJa;)c L a);cK JcK #Ja%)%c%dK N a)c;d L a);c;d L a;)c;d L a;);cd; L don;t caresJa;);cdL a;)cd L a);cd L a)cdK JdKmJa%)%c%dK N a;);cd; L a;)cd; L a)c;d; L a)cd; L a);c;d; L a);cd; L don;t caresJa;)c;d L a)c;dK

"roced're
1+ Brite the pre!a) in yo'r !a) note)oo# for a!! the circ'its re('ired in the steps that fo!!o0+ 2+ G)tain instr'ctor appro2a! for yo'r pre!a)+

Style Guidelines

26

A -!o)a! ,e t

4. More logic simplification 3+ >'i!d the circ'it re('ired for E ercise 2J)K from the re2ie0 e ercises+ 9+ Demonstrate the 0or#ing circ'it for yo'r instr'ctor+ :+ &epeat the steps from the !ast proced're for E ercise 2JcK from the re2ie0 e ercises+

27

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

. 'ulti%lexer
4earning o).ecti2e:
Ase the m'!tip!e er to imp!ement comp!e !ogica! f'nctions+

/ac0ground on the 1mux2

A m'!tip!e er% often .'st ca!!ed a m' % is a de2ice that can se!ect its o'tp't from a n'm)er of inp'ts+ ,his de2ice is 'sef'! in comp'ter systems that 'se a )'s architect're% 0here se2era! de2ices share the same comm'nication path+ A 2-to-1 m'!tip!e er is sho0n in E hi)it :+1+ In this case the t0o inp'ts are D0 and D1+ If the se!ect !ine is !o0% then the o'tp't 0i!! ref!ect the state of D0+ 4i#e0ise% if the se!ect !ine is high% the o'tp't is the state of D1+ 8ence% the o'tp't is s0itched )et0een t0o different de2ices connected to D0 and D1 'sing the se!ect !ine+ In this 0ay% on!y one de2ice 0i!! )e acti2e or connected to the )'s at any gi2en time+

E hi)it :+1: 2-to-1 m'!tip!e er

Bith an increase in the n'm)er of se!ect !ines% m'!tip!e ers a!!o0 for more than .'st t0o inp't !ines+ If t0o se!ect !ines are 'sed% then the o'tp't can )e se!ected from fo'r different inp'ts forming a 9-to-1 m' + ,he =91:1 pro2ided in yo'r #it is an 6-to-1 m' that 'ses three se!ect !ines to chose from 6 different inp't !ines+ A diagram of the =91:1 chip is gi2en in Appendi A+ ,he 6-to-1 m'!tip!e er can )e 'sed to ta#e a )yte of para!!e! data on the inp't !ines and determine 0hich of the inp't !ines to disp!ay at the o'tp't+ ,his is 'sef'! 0ith )'s architect'res in order to con2ert the para!!e! data that most often comes in )ytes into a seria! stream of )its+

3sing a multi%lexer to im%lement logical functions

Another 'se for the m' is to imp!ement fair!y comp!icated !ogic f'nctions 0itho't the aid of other !ogic gates+ As an e amp!e% e amine the fo!!o0ing f'nction a!ong 0ith its <-map% and the res'!ting minima! $G" e pression+ gJa%)%cK N a;);c; L a;)c L a);c; L a);c L a)c; N a;)c L );c; L ac; L a); In order to imp!ement the circ'it of this f'nction for e2en the minima! $G" representation% fi2e EAED gates are re('ired+ 8o0e2er% a sing!e m' can )e 'sed to imp!ement the same e pression+ ,he #ey is to 'se the inp't 2aria)!es for the f'nction as the inp't for each se!ect !ine and set the data !ines to the 2a!'e for each of the corresponding o'tp'ts+ Eote that the 2a!'e of data !ines D0% D3% D9% D:% and D5% 0hich a!so are fo'nd on pins 9% 1% 1:% 19% and 13 are set to high 0ith the remaining data !ines set !o0+ In this manner% any three inp't !ogica! f'nctions Style Guidelines 30 A -!o)a! ,e t

5. Multiplexer can )e )'i!t 0ith a sing!e m' + Eote that as mentioned pre2io's!y% the stro)e pin is tied !o0 and the order of the inp'ts from the f'nction differ from the order of the inp't !ines for the =91:1 chip+

A'B' A'B AB
00 01 11

AB'
10

C'
0

1 0

0 1

1 0

1 1

C
1

,a)!e 1:: gJa%)%cK

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

f 1 0 0 1 1 1 1 0
E hi)it :+2: Circ'it for gJa%)%cK

,a)!e 15: gJa%)%cK Bhen 'sed in this manner% the =91:1 is often referred to as a )oo!ean f'nction generator+ ,his circ'it co'!d )e e2en more f!e i)!e if the data inp't !ines% D0 thro'gh D=% co'!d )e changed+ ,he f'nction that the m'!tip!e er imp!emented co'!d )e changed 0hi!e the circ'it is r'nning 0ith the 'se of memory chips+ ,his change stores temporary 2a!'es for the inp't !ines to create a tr'!y programma)!e )oo!ean f'nction generator+ Bhen 'sing the =91:1 m'!tip!e er: J1K Ma#e s're to proper!y se!ect the stro)e !ine+ J2K Eote that 2a!'es chosen for A% >% and C may differ from those gi2en in the tr'th ta)!e in Appendi A+ Appendi A ass'mes that C is the most significant inp't !ine% 0hich may not )e the case in yo'r design+ J'st as this method of 'sing an 6-to-1 m' can )e 'sed to imp!ement any 3-inp't f'nction 0ith .'st one chip% any 9-inp't f'nction can )e )'i!t 0ith a 15-to-1 m' + 8o0e2er% the #it pro2ided 0ith this !a) on!y contains the 6-to1 m' + ,his can present a pro)!em 0hen a comp!e fo'r inp't f'nction 0o'!d re('ire se2era! different =900 series chips to imp!ement% s'ch as the f'nction hJa%)%c%dK fo'nd in the <-map and tr'th ta)!e that fo!!o0+ ,0o different minima! $G" e pressions e ist for this f'nction+ $ee )e!o0+ hJa%)%c%dK N a;)c; L a;);c L acd; L a);c;d L a;c*d* hJa%)%c%dK N a;)c; L a;);c L acd; L a);c;d L a;"d* 31

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense Either of the terms at the end of each e pression co'!d )e 'sed to o)tain a minima! e pression+ Het% either 0o'!d re('ire fo'r 3-inp't EAED gates% one 9-inp't EAED gate and one :-inp't EAED gate% ass'ming that yo'r #it e2en pro2ided EAED gates 0ith fo'r or fi2e inp'ts+ It may not )e o)2io's ho0 to 'se the m'!tip!e er in cases s'ch as this to imp!ement the f'nction+ Gne approach 0o'!d )e to 'se t0o m' chips a!ong 0ith some additiona! gates+ Gne tric# is to 'se t0o 6-to-1 m'!tip!e ers a!ong 0ith one 2-to-1 m' as sho0n in E hi)it :+1+ Each ha!f of the f'nction is imp!emented 0ith an 6-to-1 m' and the o'tp't of each is se!ected 'sing the remaining inp't as the se!ect !ine for the 2-to-1 m' + 4'c#i!y% a simp!e tric# can )e 'sed 0ith an 6-to-1 m' + First ta#e the f'nction gi2en in the <-map for hJa%)%c%dK prod'ce the tr'th ta)!e% )'t add one co!'mn for the m'!tip!e er inp't of each data e!ement+

a')' a')
00 01

a)
11

a)'
10

a 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

! 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

d 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

h(a*)*!*d) 0 1 0 0 1 1 0 1 0 1 1 0 1 1 0 0

In&u# D0Nd D0Nd D1N0 D1N0 D2N1 D2N1 D3Nd D3Nd D9Nd D9Nd D:Nd; D:Nd; D5N1 D5N1 D=N0 D=N0

!'d'
00 01 11

1 0 1 1

1 1 0 0

0 0 0 1

0 1 0 1

!'d !d !d'
10

,a)!e 1=: hJa%)%c%dK Each of the t0o ro0s in the si th co!'mn no0 represent one of the inp't !ines+ Instead of the inp't !ines ta#ing .'st tr'e or fa!se to imp!ement the tr'th ta)!e direct!y% the inp't !ines 0i!! ta#e the 2a!'e of tr'e% fa!se% d% or d;+ In this 0ay% on!y one m'!tip!e er needs to )e 'sed a!ong 0ith possi)!y one in2erter gate+ As a% )% and c are 'sed to se!ect the data !ine% each set of t0o ro0s that share the same inp't 2a!'es for a% )% and c are gro'ped together in the ta)!e+ ,hen )y comparing the o'tp't 2a!'e of h for these t0o ro0s% it can )e determined 0hat 2a!'e the data !ine sho'!d ta#e+ For e amp!e% since h matches inp't d for the first t0o ro0s% the inp't 2a!'e for D0 sho'!d )e tied to inp't d+ ,he circ'it that imp!ements hJa%)%c%dK is gi2en in E hi)it :+3+ It is ass'med that the in2erse of the inp't d is a2ai!a)!e some0here in the circ'it% if not% an in2erter 0o'!d need to )e added to this circ'it+

,a)!e 16: hJa%)%c%dK

Style Guidelines

32

A -!o)a! ,e t

5. Multiplexer

E hi)it :+3: hJa%)%c%dK imp!emented 0ith 6-to-1 m' As the m' can imp!ement !ogica! f'nctions direct!y from the tr'th ta)!e 0itho't the need for any !ogic

minimi1ation% it is often tempting to 'se the m' to imp!ement e2ery f'nction and simp!y s#ip the minimi1ation techni('es descri)ed ear!ier+ &esist this temptationM Gften the minima! $G" imp!ementation 0i!! re('ire fe0 gates res'!ting in a simp!e design 0itho't a m' + In addition% 0hen different f'nctions are re('ired for a gi2en circ'it% if on!y m'!tip!e ers 0ere 'sed% a m' 0o'!d )e needed for each and e2ery f'nction+ 8o0e2er% the minima! $G" e pressions for the different f'nctions 0i!! sometimes share common !ogica! terms+ E amine the t0o f'nctions )e!o0 that are re('ired for a gi2en circ'it+ fJ %y%1K N ;y1 gJ %y%1K N 1; L ;y1 ,hey share the term ;y1% and this part 0o'!d on!y need to )e )'i!t once and co'!d )e 'sed for )oth f'nctions% sa2ing gates+ $haring of terms in this manner is not possi)!e 0hen 'sing the m' to imp!ement f'nctions+ $o in order to ins're that the simp!est circ'it is designed to imp!ement the f'nction% the !ogic minimi1ation techni('es descri)ed ear!ier sho'!d )e e amined first )efore resorting to the m' to imp!ement a f'nction+

&e2ie0 e ercises
1+ Constr'ct the tr'th ta)!e and <-map for each of the fo!!o0ing f'nctions and determine the minima! $G" e pression+

33

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense JaK f1Ja%)%cK N a;);c; L a;)c; L a;)c L a);c; J)K f2Ja%)%cK N a;);c L a;)c L a)c; L a);c JcK f3Ja%)%c%dK N a;);c;d; L a;)cd L a)cd L a);c;d; L a);c;d JdK f9Ja%)%c%dK Na;);c;d; L a;)c;d L a)cd L a;);cd; L a;);cd L a;)cd; L a);c;d 2+ Design the imp!ementation of e pression 1J)K 'sing an 6-to-1 m' + 3+ Design the circ'it that 0i!! imp!ement 1JdK 'sing an 6-to-1 m' chip a!ong 0ith any necessary circ'itry+ 9+ E amine the fo!!o0ing fo'r-inp't f'nctions and design a circ'it that 0i!! imp!ement each+ JaK g1Ja%)%c%dK N a;);c;d L a)cd L a;)cd L a;)c;d L a);c;d L a;);cd L a)c;d L a);cd J)K g2Ja%)%c%dK N a;)c;d L a;);cd; L a);cd JcK g3Ja%)%c%dK N a)c;d; L a)c;d L a)cd L a)cd; L a;)c;d L a;)cd JdK g9Ja%)%c%dK N a;)c;d; L a)c;d; L a)cd; L a);cd; L a;)c;d L a)c;d L a)cd L a);cd

"roced're
1+ Brite the pre!a) in yo'r !a) note)oo# for a!! the circ'its re('ired in the steps that fo!!o0+ 2+ G)tain instr'ctor appro2a! for yo'r pre!a)+ 3+ >'i!d the circ'it re('ired for E ercise 2 from the re2ie0 e ercises+ Demonstrate the 0or#ing circ'it for yo'r instr'ctor+ 9+ &epeat the steps from the !ast proced're for E ercise 3 from the re2ie0 e ercises+

Style Guidelines

39

A -!o)a! ,e t

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

4 Timers and cloc0s

4earning o).ecti2es:
&e2ie0 re!ation )et0een time and fre('ency+ Constr'ct timer and c!oc# circ'its+ "rod'ce a timing digram for a circ'it+

Timing in digital circuits

,iming circ'its are often re('ired for 2ario's app!ications+ Gne may need to meas're the !ength of time that a gi2en s0itch has )een on or off+ As 0i!! )e seen in f't're !a)s% for more comp!icated circ'its% a c!oc# is often necessary to synchroni1e the 2ario's components+ Bhi!e many different 0ays e ist to )'i!d timing circ'its% the ::: timer chip has pro2en to )e an ind'stry standard for this p'rpose+

... timer
,he ::: timer chip 0as first man'fact'red in the ear!y 17=0s and contin'es to )e 'sed in e!ectronic de2ices+ ,he detai!ed circ'it diagram seen in Appendi A for this integrated circ'it contains t0o diodes% many resistors and o2er t0enty transistors+ A!! of this is contained in one sma!! d'a! in!ine pac#age that can )e 'sed in timing and c!oc#ing circ'its+ It is important to note that propagation de!ays ca'sed )y the time it ta#es for signa!s to tra2e! thro'gh the circ'it components pre2ent it from )eing 'sed in circ'its re('iring fast s0itching times+ In this case% fast is considered a fe0 Qseconds+ ,he propagation de!ay 2aries s!ight!y depending 'pon the 2ersion of the ::: )eing 'sed+ ,his !imitation pre2ents the ::: from reaching speeds necessary for modern comp'ter systems+ 8o0e2er% many app!ications ha2e !ess rigoro's re('irements for 0hich the ::: timer has pro2en to )e the component of choice+ D'e to mass prod'ction% this chip is 0ide!y a2ai!a)!e at a modest price+

Timers
A timing circ'it 'sing the ::: timer is fo'nd in E hi)it 5+1+ ,his circ'it is a!so ca!!ed a one-shot )eca'se it 0i!! 0or# once for e2ery time it is triggered proper!y+ After )eing triggered% it t'rns on for the specified time and then ret'rns to its sta)!e off state+ It is a!so often said to )e operating in monosta)!e mode )eca'se it on!y has one sta)!e state% 0hen its o'tp't is !o0% gro'nd or off+ ,he circ'it is triggered 0ith a 2o!tage )e!o0 J1I3KDcc JDcc is the s'pp!y 2o!tage for the circ'itK% at 0hich time the capacitor !a)e!ed C )egins charging thro'gh the resistor !a)e!ed &+ At the time 0hen the 2o!tage on the capacitor reaches J2I3KDcc% the o'tp't 0i!! t'rn !o0+ ,he 2o!tage across the capacitor is gi2en )e!o0+ $ee Appendi > for more information regarding resistors and capacitors+ E hi)it 5+1: ,imer circ'it DJtK N DccJ 1 R e-JtIrcKK Style Guidelines 3: A -!o)a! ,e t

6. Timers and cloc s $etting DJtK e('a! to J2I3KDcc and so!2ing for t yie!ds the time 0hen the o'tp't 0i!! go !o0 Jass'me three digits of acc'racyK+ t = 1+10J&CK Eote that the 2a!'es for resistors and capacitors often 2ary 0ith a to!erance of : per cent and 10 per cent respecti2e!y+ 8ence% the time of the timer may not e act!y match the ca!c'!ated 2a!'e+ Bhen it is critica! for the app!ication to ha2e a 2ery specific time% either the components 'sed m'st )e meas'red to ins're that they match the time needed or a 2aria)!e resistor can )e 'sed so that it can )e ad.'sted once the circ'it is )'i!t+

Cloc0s
J'st as the dr'mmer in a )and he!ps to #eep the rest of the mem)ers synchroni1ed% so does the c!oc# in a circ'it+ A c!oc# is 'sed to synchroni1e a circ'it that contains different components that ha2e different propagation de!ays+ $ynchroni1ation is re('ired )eca'se signa! changes ta#e time to tra2e! thro'gh a circ'it+ Interna! ind'ctance and capacitance fo'nd in the 0ires of the circ'it and the components themse!2es ca'se de!ays+ In order to ins're that each transition or change has f'!!y propagated thro'gh the circ'it% the c!oc# can on!y s0itch as fast as it ta#es the s!o0est part of the circ'it to f'!!y register each change+ Modern processors ha2e c!oc#s that operate in the gigahert1 range and are )'i!t 0ith the 'se of crysta!s+ ,he ::: timer chip cannot )e c!oc#ed that fast d'e to the interna! propagation de!ay 0ithin the transistors in the chip% )'t it can pro2ide a re!ia)!e c!oc# p'!se for app!ications that do not re('ire that speed+

E hi)it 5+2: C!oc# 0a2eform C!oc# speeds are gi2en in terms of fre('ency 0hich 'ses the 'nit hert1F this stands for cyc!es per second+ $o if a c!oc# is said to ha2e a fre('ency of 200 megahert1% it transitions from !ogic high to !ogic !o0 200%000%000 times in one secondM Another meas're often associated 0ith a c!oc# is its period% 0hich is the time it ta#es for the f'!! c!oc# cyc!e+ ,he period of the 200 megahert1 c!oc# is : nanoseconds+ , N 1If Mathematica!!y% period J,K and fre('ency JfK are re!ated in2erse!y+ ,he c!oc# 0a2eform gi2en in E hi)it 5+2 i!!'strates an idea!i1ed 0a2eform+ In rea!ity the transitions from !o0 to high or high to !o0 ta#e some time and are not instantaneo's as those sho0n+ As another e amp!e% a : gigahert1 c!oc# has a period of 1I:%000%000%000 seconds% 0hich is 0+0000000002 seconds or 0+2 nanoseconds+ ,he c!oc#s )'i!t for these !a)s 0i!! )e m'ch s!o0er than this+ ,he fastest c!oc# 0i!! ha2e a period of one second+

35

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense E hi)it 5+3 sho0s a c!oc# circ'it 'sing the ::: timer+ Bhen config'red in this manner% it is said that the timer is operating in asta)!e mode+ ,his means that there is no sta)!e state for the circ'itF it .'st contin'es to osci!!ate% going from !o0 to high and )ac# again+ In this case% the trigger is tied to the 2o!tage across the capacitor% so that the circ'it is triggered )y itse!f+ ,he capacitor is charged thro'gh the series com)ination of &1 and &2 and discharged thro'gh &2+ ,he capacitor charges to 2I3SDcc and then discharges to 1I3SDcc repeated!y+ Asing the same method gi2en in the pre2io's section% the times to charge and discharge the capacitor a!ong 0ith the e('ations for the period and fre('ency are !isted )e!o0+ t1 N 0+573J&1 L &2KC t2 N 0+573J&2KC , N t1 L t2 N 0+573J&1 L 2S&2KC f N 1I, N 1+99IJJ&1 L 2S&2KCK char!e time dischar!e time period fre+uency E hi)it 5+3: C!oc# Circ'it

Eote that the acc'racy of the 2a!'es of the resistors and capacitors 0i!! affect the act'a! 2a!'es for the fre('ency of the c!oc#+ A!so% this c!oc# 0i!! not ha2e a symmetric 0a2eform as it 0i!! )e charging JonK for a !onger time than it 0i!! )e discharging JoffK+ Bhen meas'ring the fre('ency of the c!oc#% co'nt the time for ten f'!! c!oc# p'!ses and then di2ide this n'm)er )y ten to determine the period+ ,his 0i!! red'ce the effect of timing errors introd'ced )y those ta#ing the meas'rements+

Timing diagrams
,he graph of the !ogica! transition for a circ'it is gi2en in a timing diagram+ ,iming diagrams pro2ide a 2is'a! trace of the circ'it f'nctiona!ity+ ,hey can a!so )e he!pf'! in determining the ma im'm possi)!e de!ay for a gi2en circ'it 0hich can then )e 'sed to determine the fastest fre('ency in 0hich the circ'it can )e c!oc#ed+ ,he diagrams disp!ay each 2a!'e in one of three different states: !ogic high% !ogic !o0% and indeterminate+ ,he indeterminate state 0o'!d occ'r 0hen a gi2en state cannot )e g'aranteed to )e either high or !o0+ Indeterminate states are 's'a!!y sho0n as gray areas that span the entire region from !o0 to high for the d'ration of the indeterminate period+ ,he transition edges are often not sho0n to )e tota!!y 2ertica!% as they are in E hi)it 5+2+ ,his is to i!!'strate the point that changes in o'tp't are not instantaneo's d'e to de!ays ca'sed )y transition times as 0e!! as interna! ind'ctance and capacitance in the circ'its+ ,he timing diagram sho0n in E hi)it 5+: is for the circ'it fo'nd in E hi)it 5+9+ ,his circ'it has three e tra points !isted: A% >% and C to determine the intermediate states of each of the gates for a gi2en transition+ In this case% 2a!'es for D0 is ass'med to )e !ogic high and D1 is ass'med to )e !ogic !o0 0ith the $E4EC, !ine ma#ing a transition from !ogic !o0 to !ogic high+ A is the o'tp't of the in2erter% > the o'tp't of the top AED gate% and C the o'tp't of the !o0er AED gate+ ,he circ'it is ass'med to )e in a sta)!e state 0ith the inp'ts $E4EC,% D0% and D1 at !ogic !o0% high% and !o0 prior to time 1ero+ Ass'me that the man'fact'rer specifies that each gate 0i!! ha2e a ma im'm de!ay of 10+0 nanoseconds+ ,his may 2ary depending 'pon the !ogic fami!y 'sed% so the data sheet sho'!d )e cons'!ted for 2erification 0hen determining the ma im'm de!ay for a gi2en circ'it+ Eotice that once the $E4EC,

Style Guidelines

3=

A -!o)a! ,e t

6. Timers and cloc s !ine is )ro'ght !o0% A% >% and the G'tp't a!! ass'me an intermediate 2a!'e as there is no g'arantee of ho0 fast the transition 0i!! occ'r+ Gnce at 10+0 nanoseconds% the o'tp't of the in2erter can )e 2erified to ha2e gone !o0 and the state for A is !isted as !o0+ ,his transition 2a!'e then ripp!es thro'gh the other gates as the top AED gate no0 ta#es another 10+0 nanoseconds to ins're that its o'tp't has changed from high to !o0+ G'tp't E hi)it 5+9: 2 1 M'!tip!e er

changes may occ'r faster than the times !isted% ho0e2er as that cannot )e g'aranteed% the s!o0est time m'st )e 'sed to determine the fastest fre('ency in 0hich a circ'it can )e c!oc#ed+ If this circ'it 0ere to )e c!oc#ed% since the ma im'm de!ay for the entire circ'it is 30+0 nanoseconds% this 0o'!d a!so )e the sma!!est a!!o0a)!e 2a!'e for the period of the c!oc#% 0hich 0o'!d yie!d a ma im'm fre('ency of 33+3 Mhert1+ In these !a)s% the circ'its 0i!! )e c!oc#ed at a s!o0 eno'gh rate that de!ays on the order of nanoseconds 0i!! not impact the circ'its+ 8o0e2er% for circ'its 0here speed is essentia!% detai!ed ana!ysis s'ch as this is critica! to ins're that the circ'it is c!oc#ed as fast as possi)!e 0hi!e sti!! a!!o0ing eno'gh time for the circ'it to sta)i!i1e+

E hi)it 5+:: ,iming diagram

Acc'racy of ans0ers
As this chapter in2o!2es ans0ers that go )eyond the simp!e )inary% tr'e or fa!se format% a )rief disc'ssion of the acc'racy of the n'm)ers fo!!o0s+ Bhen ans0ers are pro2ided% it is )eneficia! to #no0 ho0 acc'rate those ans0ers are+ ,he precision of any meas'rement is dependent 'pon the acc'racy of the de2ice that is 'sed to perform the meas'rement+ For e amp!e% one 0o'!d not e pect to o)tain meas'rements 0ithin tho'sandths of a second 'sing an ordinary 0rist0atch or 0ithin tho'sandths of a mi!!imeter 'sing a standard r'!er+ Gnce the acc'racy of the meas'rements 'sed is 'nderstood% it is important to remem)er the r'!es that app!y to the n'm)er of significant digits for any ca!c'!ation+ 36

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

,rai!ing 1eros are significant to the n'm)er+ Ase a!! digits 0hen performing ca!c'!ations and ro'nd on!y for the fina! ans0er+ Bhen n'm)ers are m'!tip!ied or di2ided% the fina! ans0er has the same n'm)er of significant digits as the

n'm)er 0ith the sma!!est amo'nt orf significant digits in the ca!c'!ation+
In this )oo#% the form'!as are pro2ided 'sing three digits of acc'racy+ It may )e the case that fe0er digits

can )e o)tained for a gi2en meas'rement or that the components 'sed may on!y )e #no0n 0ithin one digit of acc'racy+ In these cases% the fina! ans0ers sho'!d )e ro'nded according!y+ As mentioned% the to!erances of the components 0i!! ca'se de2iation of the meas'red ans0er from the theoretica! ans0er+ ,he to!erance of the resistors 'sed in these !a)s is : per cent 0hi!e the capacitors ha2e a to!erance of 10 per cent+ ,his means that for a 1000 ohm resistor% that resistor is g'aranteed to )e )et0een 7:0 and 10:0 ohms+ 1000 R 0+0:J1000K T act'a! 2a!'e T 1000 L 0+0:J1000K 4i#e0ise% a 1 mircofarad capacitor is g'aranteed to )e )et0een 0+7 UF and 1+1 UF 1 - +1J1K T act'a! 2a!'e T 1 L +1J1K ,his may ca'se the meas'red ans0er to differ ('ite a )it from the ans0er ca!c'!ated 'sing the form'!as+ In addition% 0hen the 2a!'es of the resistors and capacitors are m'!tip!ied together% as is the case 0ith the form'!as a)o2e for the timer and c!oc#% these to!erances are compo'nded+ For e amp!e% ass'me that a 100%000 ohm resistor is com)ined 0ith a 100 F capacitor to prod'ce a time of 10+1 seconds+ t = 1+10J&CK N 1+10S100%000S0+0001 N 11+0 seconds+ 8o0e2er% if 0e ta#e the 0orst case for each 2a!'e% 0e can see that the ans0er 0i!! act'a!!y )e 0ithin 1: per cent+ 1+10J7:%000KJ0+00007K T act'a! 2a!'e T 1+10J10:%000KJ0+00011K 7+91 T act'a! 2a!'e T 12+= For this reason% it sho'!d not )e ass'med that the fina! 2a!'es for the c!oc# and timer 0i!! match e act!y the 2a!'es ca!c'!ated theoretica!!y+ ,he to!erances of the components 'sed 0i!! often mean that the theoretica! 2a!'e of the c!oc# or timer may on!y ha2e one significant digit of acc'racy+ Bhen the acc'racy of the timer or c!oc# is important% either components m'st )e meas'red )efore )eing 'sed to ins're their 2a!'es% or components 0ith sma!!er to!erances sho'!d )e 'sed J0hich is more cost!yK% or resistors 0ith ad.'sta)!e 2a!'es JpotentiometersK can )e 'sed and ad.'sted after the circ'its are )'i!t+ Gf co'rse ad.'sting the potentiometers is time cons'ming and th's cost!y+

&e2ie0 e ercises
1+ Bhat is the period in seconds of the c!oc# 0ith the gi2en fre('enciesC a+ 5+00 -hert1 )+ 10 Mhert1 c+ 5000 &"M JEG,E: 50 seconds are in each min'teK 2+ For the gi2en period% determine the fre('ency of the c!oc# in 8ert1 a+ 10+o sec )+ 0+0:00 nanoseconds c+ 1+00 mi!!iseconds

Style Guidelines

37

A -!o)a! ,e t

6. Timers and cloc s 3+ Ass'me de!ay for each !ogic gate is 10+0 nanoseconds for the circ'it in E hi)it 3+3 and that inp't 2a!'es of A is !o0 and > and C are a!! at !ogic high+ Dra0 a timing diagram for a transition at time 1ero that ta#es inp't for C from !ogic high to !ogic !o0+ 4ist inp't A% >% C% and G'tp't as 0e!! as 2a!'es for pins 3% 5% and 10+ 9+ If the de!ay for each !ogic gate is 10+0 nanoseconds% 0hat is the ma im'm fre('ency that the circ'it from E hi)it 2+19 can )e re!ia)!y c!oc#ed in order to ins're proper operationC :+ A 100 F capacitor is 'sed to )'i!d timers+ ,hree timers are to )e )'i!t 0ith times of 1% : and 10 seconds+ a+ Bhat resistors sho'!d )e chosen to o)tain the times pro2idedC )+ Ass'ming that yo' are !imited to choosing the 2a!'es pro2ided in the !a)% 0hich resistors sho'!d )e chosen to come as c!ose to the desired 2a!'es as possi)!eC &eca!! that 0hen resistors are added in series% the tota! resistance is the s'm of the resistors+ c+ Dra0 a schematic of the :-second timer+ d+ -i2en that capacitors ha2e a to!erance of L -10 per cent and resistors ha2e a to!erance of L -: per cent% 0hat range of 2a!'es co'!d yo' e pect for yo'r timerC 5+ A 100 F capacitor is 'sed to )'i!d c!oc#s+ ,0o c!oc#s are to )e )'i!t 0ith periods of 1 and : seconds+ a+ Asing 2a!'es of resistors pro2ided in yo'r !a)% pic# t0o resistors that yie!d periods as c!ose to those desired as possi)!e+ )+ Bhat is the time on and time off for each of the c!oc#s d'ring one periodC c+ Dra0 a schematic of the :-second c!oc#+

"roced're
1+ Brite the pre!a) in yo'r !a) note)oo# for a!! the circ'its re('ired in the steps that fo!!o0+ Inc!'de a!! necessary e('ations and ca!c'!ations+ 2+ G)tain instr'ctor appro2a! for yo'r pre!a)+ 3+ >'i!d and test the :-second timer from E ercise : a)o2e + a+ 8o0 different is the meas'red 2a!'e from the ca!c'!ated 2a!'eC )+ Demonstrate the timer for yo'r instr'ctor+ 9+ &epeat "roced're 3 for the 10-second timer from E ercise : a)o2e+ :+ >'i!d and test the 1 second c!oc# from E ercise 5+ a+ 8o0 different is the meas'red 2a!'e from the ca!c'!ated 2a!'eC )+ Demonstrate the c!oc# for yo'r instr'ctor+ 5+ &epeat "roced're : for the : second c!oc# from E ercise 5 a)o2e+

90

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

5 'emory
4earning o).ecti2es:
&e2ie0 differences )et0een !ogic circ'its and persistent memory+ &e2ie0 properties for the $-& !atch and D f!ip-f!op+ Constr'ct a circ'it 'sing a f!ip-f!op+

'emory
Ho' ha2e often heard the phrase: ?In order to #no0 0here yo' are going% yo' need to #no0 0here yo' ha2e )een+@ Bhi!e a!! the circ'its disc'ssed in pre2io's chapters are 2ery 'sef'!% many app!ications ('ite simp!y cannot )e imp!emented 0itho't the 'se of memory to ?remem)er 0here they ha2e )een@+ Modern comp'ter systems emp!oy a 0ide array of different memory storage methods that ha2e different properties+ Eon-2o!ati!e memory 'sed for secondary storage s'ch as hard dri2es% CD-&GM dri2es% or so!id state memory Ji+e+ an $ec're Digita! or $D cardK retains its 2a!'e after po0er is sh't off+ Do!ati!e% dynamic random access memory J&AMK !oses its 2a!'e 0hen po0er is sh't off and a!so m'st ha2e its 2a!'es contin'a!!y refreshed 0ith e terna! circ'itry+ $tatic% 2o!ati!e random access memory s'ch as that fo'nd in cache memory and C"A registers cannot retain its 2a!'e 0hen po0er is not pro2ided% yet it does not need to )e refreshed+ ,his chapter 0i!! foc's 'pon the static% 2o!ati!e% e!ectronic memory !isted !ast+ A!! of the !ogic circ'its )'i!t in the pre2io's sections are #no0n as !o+)"na#o "al log"! circ'its+ ,hey depend on!y 'pon the state of their inp'ts at any gi2en time and do not ta#e into acco'nt anything that has happened in the past+ Gften it is necessary for the o'tp't of a circ'it to ta#e past 2a!'es into acco'nt+ 4ogica! circ'its that ta#e past o'tp't 2a!'es a!ong 0ith present inp'ts into acco'nt to comp'te the o'tp't 2a!'es are #no0n as se,uen#"al log"! circ'its+ In order to determine the ne t state of an o'tp't% the pre2io's state m'st )e #no0n+ Memory is 'sed to store the history of the stateJsK of a digita! circ'it for 'se in se('entia! circ'its+ An e amp!e of a se('entia! !ogic circ'it 0o'!d )e a co'nter+ A comp'ter is nothing more than an ad2anced se('entia! !ogic circ'it 0ith memory to store data% programs% and references to the state of programs c'rrent!y )eing r'n+

67 latch
,0o EG& gates can )e config'red 'sing feed)ac# to prod'ce one )it of memory+ ,he config'ration gi2en in E hi)it =+1 is #no0n as an $& !atch+ ,he $% $E, and &% &E$E, are the inp'ts and the V o'tp't is pro2ided a!ong 0ith its in2erse+ ,he $ inp't is 'sed to set or t'rn on the !atch )y setting the o'tp't V high and in2erse !o0+ $imi!ar!y% the & inp't is 'sed to reset or t'rn off the !atch )y resetting the o'tp't to !o0 and the in2erse to high+ Gnce the !atch is set% V remains at a !ogic high 0hi!e )oth inp't !ines are off+ $imi!ar!y% once the !atch is reset% the V o'tp't 0i!! )e set to !ogic !o0 and 0i!! remain that 0ay 0hi!e )oth inp't !ines are off+ In this 0ay% the !atch can store one )it of information indefinite!y% or at !east as !ong as it has po0er s'pp!ied to it+ ,he EG& $& !atch has acti2e high inp'ts% meaning that if either inp't is )ro'ght high% it 0i!! force a corresponding o'tp't condition+ Eote that setting )oth inp't 2a!'es high m'st )e a2oided in order to retain the o'tp't 2a!'es as opposite to each other+ 4atches can a!so )e )'i!t 'sing EAED gates% )'t the set and reset !ines operate in a s!ight!y different manner 'nder this config'ration+ ,he transitions for these !atches are e amined in more detai! in the e ercises+ Style Guidelines 91 A -!o)a! ,e t

!. Memor"

0 0 1 1

. 0 1 0 1

/ V Jdoes not changeK 0 1 state not 'sed

E hi)it =+1: $& !atch

,a)!e 17: EG& $& !atch

,he EAED )ased $& !atch is an acti2e !o0 de2ice 0ith a defa'!t state of !ogic high for )oth $ and & inp'ts+ ,he $ and & inp't 2a!'es are )ro'ght !o0 to change the state+ J'st as the EG& )ased $& !atch sho'!d not ha2e )oth inp't 2a!'es t'rned high sim'!taneo's!y% the $ and & for a EAED )ased $& !atch sho'!d not )e )ro'ght !o0 at the same time+

0 0 1 1

. 0 1 0 1

/ state not 'sed 1 0 V Jdoes not changeK

E hi)it =+2: $& !atch

,a)!e 20: EAED $& !atch

Fli%-flo%s
A f!ip-f!op is a !atch that has )een modified to 0or# 0ith the 'se of a c!oc#+ C!oc#s are 'sed to synchroni1e the timing for different components in a circ'it+ ,he o'tp't of the f!ip-f!op 0i!! on!y change 0hen the c!oc# signa! is in a gi2en state% s'ch as high+ E hi)it =+3 is a D f!ip-f!op that 0i!! on!y change 0hen the c!oc#% C in the fig're% is high+ $ome f!ip-f!ops are designed to e amine the inp'ts 0hen the edge of the c!oc# ma#es a transition from !o0 to high% ca!!ed rising or positi2e edge triggered f!ip-f!ops+ $imi!ar!y% negati2e edge triggered f!ip-f!ops can )e designed that on!y e amine inp'ts 0hen the c!oc# ma#es a high to !o0 transition+ ,he time in 0hich the inp'ts can affect a change on the o'tp't is red'ced 0ith a rising or fa!!ing edge triggered de2ice+ ,he speed 0ith 0hich a f!ip-f!op can )e c!oc#ed is determined )y the ma im'm de!ay from the gates that are 'sed to constr'ct the de2ice+ For this reason% the inp't to the gate sho'!d )e sta)!e prior to the c!oc# transition and the time )efore the ne t c!oc# p'!se sho'!d !ast !ong eno'gh for the o'tp't state to sta)i!i1e+ Man'fact're specifications for the de2ice )eing 'sed sho'!d )e cons'!ted to determine the ma im'm c!oc# speed+ 92 E hi)it =+3: D f!ip-f!op

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense $ince these !a)s on!y 'se c!oc#s 0ith periods no faster than 1 second% the circ'its designed ne2er approach the !imits of the ma im'm c!oc# speed+ E hi)it =+9 'ses t0o D f!ip-f!ops+ ,he o'tp't of the first is 'sed as the inp't of the second creating a master-s!a2e arrangement+ ,his res'!ts in a positi2e edge triggered f!ip-f!op+

E hi)it =+9: "ositi2e edge triggered D f!ip-f!op Circ'itry can )e added to prod'ce J<% ,% or D f!ip-f!ops+ ,he J< f!ip-f!op% !i#e the $& !atch has t0o inp'ts% ho0e2er a!! fo'r states are 2a!id for the J< f!ip-f!op+ ,he , is #no0n as a togg!e f!ip-f!op )eca'se if the inp't is high% the state of the o'tp't togg!es+ ,his means that 0hen c!oc#ed 0ith an inp't of one and a c'rrent state of high% the o'tp't goes !o0 and if it 0as !o0% it goes high+ ,he D f!ip-f!op o'tp't fo!!o0s the 2a!'e of the inp't 0hi!e ena)!ed or 0hen c!oc#ed% other0ise it remains in the memory state+ >oth the , and D ha2e on!y one data inp't+ ,he ta)!es )e!o0 !ist the inp't of the f!ip-f!op a!ong 0ith the present state% V% and then the ne t state% V N+ ,he circ'it for a rising edge triggered D f!ip-f!op is pro2ided )e!o0+ J< f!ip-f!ops are 2ery common in many designs+ For the sa#e of simp!icity% on!y the D f!ip-f!op 0i!! )e 'sed for the designs in this te t+

0 0 0 0 0 1 1 1 1

1 / /N 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 - 'nchanged 1 - 'nchanged 0 - reset 0 - reset 1 - set 1 - set 1 - togg!e 0 - togg!e 2 0 0 1 1 / /N 0 1 0 1 0 - 'nchanged 1 - 'nchanged 1 - togg!e 0 - togg!e D / /N 0 0 1 1 0 1 0 1 0 - off 0 - off 1 - on 1 - on

,a)!e 21: J< f!ip-f!op

,a)!e 22: , f!ip-f!op

,a)!e 23: D f!ip-f!op

E hi)it =+: sho0s the sym)o!ic representation of the D f!ip-f!op 'sed for circ'it diagrams+ ,he rectang!e sho0n is common!y 'sed for !atches and f!ip-f!ops+ A!so note the )'))!e in front of the C4EA& !ine to indicate that the de2ice can )e set to !o0 or ?c!eared@ 0hen this !ine is set !o0F for norma! operation the C4EA& sho'!d )e !eft high+

Style Guidelines

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!. Memor" $ome de2ices a!so come 0ith a "&E$E, !ine that can )e 'sed to set or t'rn on the o'tp't in m'ch the same manner+ ,hese !ines can )e 'sed to !oad the f!ip-f!ops 0ith specific 2a!'es% especia!!y 0hen the 'nit is first po0ered on+ ,he c!oc# !ine has a sma!! triang!e that denotes that the de2ice is triggered 0ith a rising edge+ Fa!!ing edge-triggered de2ices 0i!! ha2e a sma!! )'))!e preceding the triang!e+ For these !a)s% the =91=:% 0hich pro2ides fo'r rising edge triggered D f!ip-f!ops on a sing!e chip% is recommended+ $chematics of the =91=: can )e fo'nd in Appendi A+

&e2ie0 e ercises
1+ Ase the $& !atch from E hi)it =+1+ Ass'ming the 2a!'es in the ta)!e

E hi)it =+:: D f!ip-f!op sym)o!

represent 2a!'es that ha2e .'st occ'rred% determine the sta)!e 2a!'es for the o'tp'ts VE and VE;+ &eca!! that the EG& gate is an acti2e high gate% meaning any time either of the inp't 2a!'es is high the o'tp't is !o0+ ,he first% fo'rth% and si th ro0s of the ta)!e are done for yo'+ ,he tr'th ta)!e for the EG& is pro2ided+ 2+ As an e amp!e% o'tp't for the first ro0 is traced: a+ $ is 0 and V; is 1% therefore VE stays 0+ )+ & is 0 and VE is 0% therefore VE ; stays 1 c+ $ta)!e )eca'se V and V; retain 2a!'es+ 3+ For the fo'rth ro0% the o'tp'ts togg!e: a+ & is 1% so VE; m'st )e 0+ )+ $ is 0 and VE is 0% so VE ; is 1+ c+ $ta)!e+ & is 1% V is 0 and not affected )y V;+ Bith $ and V 0% V; stays 9 ,racing the si th ro0 yie!ds the fo!!o0ing: a+ $ is 1% so VE; m'st )e 0+ )+ & is 0 and VE; is 0% so VE is 1+ c+ $ta)!e as $ is 1% VE; stays 0+ Bith & and VE; 0% VE stays 1+,o start tracing% reca!! that if any of the inp't 2a!'es to a EG& are 1% the o'tp't m'st )e 0+ :+ &epeat e ercise 1 0ith the !atch from E hi)it =+2 )y determining the sta)!e states of a!! 6 ro0s of the tr'th ta)!e from the pre2io's pro)!em+ Bhi!e 2a!'es for VE and VE ; are pro2ided in ro0s 1% 9 and 5 for the !ast pro)!em% yo' m'st 0or# a!! 6 ro0s for this pro)!em+ &emem)er that the EAED gate has an o'tp't of 1 if either of the inp't 2a!'es of the gate is 0+ 5+ Asing the D f!ip-f!op )e!o0% determine the sta)!e o'tp't of each of the EAED gates !a)e!ed 1 thro'gh 9 0hen the 2a!'es for D% C% and V first occ'r+ ,he fo!!o0ing trace for the first ro0 ser2es as an e amp!e+ a+ &emem)er the EAED is an acti2e !o0 de2ice% meaning the o'tp't 0i!! )e 1 if either inp't is 0 J!o0K+ )+ D and C are 0% so EAED1 and EAED2 0i!! )e 1+ c+ EAED3 is 0 and EAED2 is 1% ma#ing EAED9 1+ d+ EAED1 is 1 and EAED9 is 1% so EAED3 0i!! stay 0+ e+ $ta)!e as neither EAED3 or EAED9 change state+

A 0 0 1 1 B 0 1 0 1
N4.

. / /' /N 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 3 3 0 3 1 3 3

/N' 1 3 3 1 3 0 3 3

0 0 0 0 1 1 1 1

1 0 0 0

99

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense D 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 / /' 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 3 3 3 3 3 3 3 5 1 3 3 3 3 3 3 3 67/N 0 3 3 3 3 3 3 3 87/N' 1 3 3 3 3 3 3 3

=+

Ase the data gi2en for the =91=: in Appendi A to determine the 2a!'e of the o'tp't V after a rising c!oc# edge has )een recei2ed )y the c!oc# pin+

"roced're
1+ Brite the pre!a) in yo'r !a) note)oo# for a!! the circ'its re('ired in the steps that fo!!o0+ Inc!'de a!! necessary e('ations and ca!c'!ations+ 2+ G)tain instr'ctor appro2a! for yo'r pre!a)+ 3+ Constr'ct an $& !atch 'sing EG& gates+ Derify its operation and demonstrate the circ'it for yo'r instr'ctor+ 9+ Constr'ct one )it of memory 'sing one D f!ip-f!op from a =91=: chip+ Derify its operation and demonstrate the circ'it for yo'r instr'ctor+

Style Guidelines

9:

A -!o)a! ,e t

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

8 6tate machines
4earning o).ecti2es:
Constr'ct state transition diagrams+ &e!ate the n'm)er of memory )its re('ired for a gi2en state machine+ >'i!d fo'r-state state machines+

9hat is a state machine:

A state machine% often referred to as a finite state machine is a se('entia! !ogic circ'it that has a finite n'm)er of defined states that can )e represented+ A state machine re('ires the 'se of memory to store the state of the machine+ Com)inatoria! !ogic is 'sed to com)ine the 2a!'es of the present state a!ong 0ith inp'ts to the system to determine the ne t state of the system+ An e amp!e of a simp!e state machine co'!d )e a co'nter that co'nts from from 0 to 1 to 2 to 3 and )ac# to 0+ In this case% the state machine does not ha2e any inp't at a!!% it 'ses the past state and increments the 2a!'e of e2ery c!oc# cyc!e+ An e amp!e of a comp!e state machine 0o'!d )e a comp'ter+ In this case% the comp'ter can ha2e many different inp'ts and has many different states+ Inp't data can come from the #ey)oard% net0or#% mo'se% memory% etc+% 0hi!e the state 0o'!d norma!!y )e associated 0ith the address in memory of the program )eing r'n+ In this te t% the state machines 0i!! )e !i#e the co'nter .'st descri)ed )'t certain!y nothing as comp!e as a comp'ter+ $tate machines are 'sed in more than .'st comp'ters+ Any process that can )e defined 0ith a gi2en predicta)!e a!gorithm can often )e represented )y an e!ectronic state machine+ For e amp!e% a coffee 2ending machine co'!d )e a'tomated 0ith a state machine+ ,he states 0o'!d )e: 0aiting for correct change% se!ect options s'ch as cream or s'gar% drop c'p% dispense coffee% and dispense options+ Inp'ts co'!d inc!'de the cream )'tton% s'gar )'tton% correct change indicator% and a timer to determine ho0 !ong to fi!! the c'p 0ith coffee+

6tate transition diagrams

A state transition diagram is a graphica! representation of the state machine+ E hi)it 6+1 sho0s the state transition diagram for a co'nter that starts at 0 and goes 'p thro'gh 3 and then )ac# again to 0+ ,his machine has no inp't% transitioning from one state to the ne t at e2ery c!oc# p'!se+ Each state is mar#ed 0ith a circ!e that contains the 2a!'e of the state+ ,he arro0s represent the transitions from one state to the ne t+ ,he state machine sho0n in E hi)it 6+2+a is a!so a fo'r state co'nter% )'t it 'ses one inp't+ ,he inp't% !a)e!ed % determines 0hether the co'nter contin'es to increment the co'nt+ Bhen e('a!s 0% the co'nter co'nts and 0hen e('a!s 1% it remains in the c'rrent state+ ,he con2ention fo!!o0ed here is as fo!!o0s: state 2a!'es are !isted inside of each state )'))!e and inp't 2a!'es that determine the transition are !isted ne t to each arro0+ If the state E hi)it 6+1: Fo'r state co'nter

Style Guidelines

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#. $tate machines 0i!! transition regard!ess of any inp't% then no inp't 0i!! )e !isted ne t to that arro0+ A timing diagram for this fo'r state co'nter is gi2en in E hi)it 6+2+)+ ,his ass'mes that the fina! circ'it is c!oc#ed at 1+00 seconds and that the rising edge triggered f!ip-f!ops are 'sed+ Eote that the 2a!'es of each )it% D1% the most significant )it% and D0% the !east significant )it% on!y change on the rising edge of the c!oc#% 0hi!e the inp't is free to change at any time+ ,his diagram ser2es a s!ight!y different p'rpose than the timing diagram sho0n in a pre2io's chapter+ Bhi!e the pre2io's diagram 0as 'sed to determine ma im'm possi)!e de!ays for a circ'it% this one is 'sed to i!!'strate the tra2ersa! of the machine thro'gh the 2ario's states+ ,he timing diagram% !i#e the state diagram can )e he!pf'! 0hen attempting to 2erify the operation of a constr'cted circ'it+ E hi)it 6+2+a: Fo'r state co'nter 0ith inp't

E hi)it 6+2+): ,iming diagram for fo'r state co'nter

6tate machine design

In order to design a state machine one 0o'!d need to recogni1e the inp'ts of the system% the states% and ho0 it transitions from one state to the ne t+ ,his is graphica!!y represented 0ith a state transition diagram+ ,hen% the transition diagram sho'!d )e 'sed to create a tr'th ta)!e that has the inp'ts to the system and c'rrent state 2a!'es as inp'ts in that ta)!e+ ,he o'tp't of the tr'th ta)!e is the ne t state of the system+ Com)inatoria! !ogic is 'sed to imp!ement the f'nctions re('ired to o)tain the ne t state 2a!'es for the state machine+ A!! of the >oo!ean !ogic minimi1ation techni('es 'sed in ear!ier chapters are 'sed at this stage+ As memory is 'sed to store the states% the o'tp't or ne t state that res'!ts from the tr'th ta)!e is 'sed as the inp't to the f!ip-f!op storing the state 2a!'es+ 9=

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense Fina!!y% the f!ip-f!ops 0i!! need to )e c!oc#ed+ In these !a)s 0e 0ant to o)ser2e the states% so the c!oc# 'sed has a s!o0 period% s'ch as 2 seconds% and a fre('ency of W hert1+

E amp!e 1: Fo'r state co'nter

,he fo!!o0ing steps o't!ine the design of a fo'r state co'nter 0ith no inp't+ ,he fo'r state co'nter is re-!a)e!ed in E hi)it 6+3 to sho0 the 2a!'es ta#en for the re('ired t0o )its of memory !a)e!ed V1 and V0+ ,he 2a!'es of V1 and V0 are gi2en as 0e!!% 0hich happen to fo!!o0 the )inary e('i2a!ent of the 2a!'e of the co'nter+ ,he ta)!e )e!o0 sho0s ho0 the present state% gi2en )y V1 and V0% transition at the ne t c!oc# signa! to the ne t state% gi2en )y V 1E and V0E+

/1 0 0 1 1

/0 0 1 0 1

/1N 0 1 1 0

/0N 1 0 1 0
E hi)it 6+3: Fo'r state co'nter 0ith states

,a)!e 29: ,r'th ta)!e ,he ne t step is to determine the f'nctions that represent 2a!'es of the ne t state% V 1E and V0E+ As these f'nctions on!y ha2e t0o 2aria)!es% they are fair!y easy to determine 0itho't the 'se of comp!e )oo!ean a!ge)ra or <-maps+ V0E is .'st the in2erse of V0+ V 1E is the E c!'si2e G& of the t0o inp'ts+ As the !ogic #it does not contain an E c!'si2e G& gate% the e('i2a!ent !ogic 'sing AED and G& gates is gi2en a!ong 0ith the e('i2a!ent !ogic 'sing EAED gates on!y+ ,he res'!ting circ'it is sho0n in E hi)it 6+9+ V0NJV1%V0KN V0; V1NJV1%V0K N V1 V0 N V1V0; L V1;V0 N JJV1V0;K;JV1;V0K;K; Eo0% in order to create a f'!!y f'nctiona! circ'it% memory needs to )e inc!'ded+ In this case% t0o D f!ip-f!ops from a =91=: chip 0i!! )e 'sed+ >eca'se the =91=: chip pro2ides the o'tp't V as 0e!! as its in2erse% the design can )e simp!ified )y e!iminating the in2erters from the diagram in E hi)it 6+9+ ,he f'!! schematic of the circ'it is sho0n in E hi)it 6+: a!ong 0ith pino'ts for each chip+ A s0itch can )e 'sed to c!oc# the circ'it for test p'rposes+ A c!oc#% s'ch as one designed 0ith a ::: timer from the pre2io's chapter% sho'!d )e 'sed in any fina! design+ E hi)it 6+9: Co'nter 4ogic

Style Guidelines

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#. $tate machines

E hi)it 6+:: Co'nter Circ'it

E amp!e 2: Fo'r state co'nter 0ith inp't

,he fo'r state co'nter gi2en in E hi)it 6+2+a introd'ces a comp!e ity )y adding an e terna! inp't+ ,he state transition diagram is redra0n in E hi)it 6+5 0ith the states !a)e!ed in )inary% V1 )eing the most significant )it+ ,he tr'th ta)!e 'sing the three items as inp't: % V1 and V0 % and the o'tp't gi2en )y the ne t state 2a!'es V1E and V0E is gi2en in ,a)!e 2:+

x 0 0 0 0 1 1 1 1
E hi)it 6+5: Fo'r state co'nter 0ith inp't

/1 0 0 1 1 0 0 1 1

/0 0 1 0 1 0 1 0 1

/1N 0 1 1 0 0 0 1 1

/0N 1 0 1 0 0 1 0 1

,a)!e 2:: Co'nter tr'th ta)!e

,he 2a!'es of the o'tp'ts for V 1E and V0E are then !isted in <-maps to determine the minima! $G" e pressions+ E('i2a!ent e pressions 'sing on!y EAED gates are gi2en+

97

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

/1'/0'
00

/1'/0
01

/1/0
11

/1/0'
10

V1N

;V1;V0 L V1 L V1V0;

x'
0 1

0 0

1 0

0 1

1 1

N JJ ;V1;V0K; J V1K; JV1V0;K; K;

,a)!e 25: V1NJ %V1%V0K

/1'/0'
00

/1'/0
01

/1/0
11

/1/0'
10

V0N

V0 L ;V0;

x'
0

1 0

0 1

0 1

1 0

N JJ V0K; J ;V0;K;K;

x
1

,a)!e 2=: V0NJ %V1%V0K

E hi)it 6+=: Circ'it diagram for fo'r state co'nter 0ith inp't ,he !ogic is then imp!emented 'sing the =900 series chips% as sho0n in E hi)it 6+=+ ,he o'tp't of the !ogic is 'sed to feed the inp't of each D f!ip-f!op and the o'tp't of each f!ip-f!op is 'sed as inp't for the !ogic+ Eote that the C4EA& !ine for the =91=: m'st )e tied to Dcc+ ,he C4EA& !ine can )e 'sed on po0er 'p to c!ear or set the f!ip-f!op 2a!'e to !ogic 1ero+ 8o0e2er% if the !ine is #ept !o0% the 2a!'e of the f!ip-f!op 0i!! a!0ays remain at !ogic !o0+ ,he C4EA& can )e !eft to f!oat% ho0e2er this ma#es the f!ip-f!op s'scepti)!e to f!'ct'ations in e!ectrica! noise+ ,he 'se of the C4EA& !ine 0i!! )e disc'ssed in more detai! in the ne t chapter+ For no0 the C4EA& 0i!! .'st )e tied to !ogic Style Guidelines :0 A -!o)a! ,e t

#. $tate machines high+ For testing p'rposes% a s0itch can )e 'sed for the c!oc#+ 8o0e2er% ma#e s're to read the ne t section regarding de)o'nced s0itches )efore 'sing a s0itch for this p'rpose+

Debounced switches
Gne 0ord of ca'tion is in order 0hen 'sing s0itches as the c!oc# so'rce+ As a s0itch is a mechanica! de2ice% they can s'ffer from )o'nce+ >o'nce occ'rs 0hen the meta! contacts stri#e each other and ?)o'nce@ )efore they come to rest+ Bhen this occ'rs% it can !oo# !i#e the s0itch changes state m'!tip!e times e2en tho'gh it has on!y gone from open to c!osed+ $0itches come in a 2ariety of config'rations+ ,0o common 2ersions are the sing!e po!e do')!e thro0% $"D, or the sing!e po!e sing!e thro0% $"$, sho0n )e!o0+

E hi)it 6+7: $"$, s0itch E hi)it 6+6: $"D, s0itch Different approaches e ist for ?de)o'ncing@ s0itches+ $oft0are can )e 'sed to test the o'tp't of the s0itch and ins're that on!y one change is registered% instead of the m'!tip!e changes that can occ'r 0ith )o'ncing+ ,0o common hard0are approaches are pro2ided for )oth types of s0itch+ ,he 2a!'es for resistors and capacitors sho0n sho'!d )e chosen so that the time is as !ong as the system )o'nce is e pected to !ast+ Da!'es of 100<X for the resistors and 0+1UF for the capacitor 0o'!d pro2ide a p'!se of 1+1 msec% 0hich sho'!d )e s'fficient to de)o'nce the s0itch in E hi)it 6+11+ Gf co'rse other circ'its can )e 'sed to de)o'nce s0itches and ad.'stments may need to )e made to the 2a!'es of the components to s'it the app!ication+ ,he !ogic #it pro2ided sho'!d ha2e at !east t0o de)o'nced s0itches+ E hi)it 6+10: De)o'nced $"D, s0itch

E hi)it 6+11: De)o'nced $"$, s0itch

:1

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

&e2ie0 e ercises
1+ 8o0 co'!d 'sing a reg'!ar s0itch as the c!oc# so'rce affect the operation of the co'nterC 2+ Dra0 a timing diagram for the machine that 'ses the state transition diagram fo'nd in E hi)it 6+3+ Ass'me that the machine 0i!! 'se a c!oc# 0ith a period of 1+00 seconds% that the f!ip-f!ops 'sed for the design are rising edge triggered and that the machine is in state 01 prior to time 1ero and that the machine goes thro'gh 9 c!oc# p'!ses+ 3+ Dra0 the state diagram for a fo'r state co'nter 0ith one inp't 0here the co'nter co'nts 'p in )inary 0hen the inp't is !o0 and co'nts in re2erse 0hen the inp't is high+ 9+ 8o0 many D f!ip-f!ops are re('ired for the co'nter from E ercise 3C :+ Determine the !ogic re('ired for the inp't of the fo'r state co'nter from pro)!em 3 and dra0 a circ'it diagram 0ith pino'ts+ 5+ Dra0 the state diagram for a three-state state machine that co'nts from 00 01 10 00 etc+ as !ong as the inp't is !o0+ Bhen the inp't is high% the co'nter does not co'nt and stays at its c'rrent state+ =+ 8o0 many D f!ip-f!ops are necessary for the co'nter from the pre2io's pro)!emC Are a!! of the possi)!e states for the f!ip-f!ops 'sedC If not 0hich ones are notC

"roced're
1+ Brite the pre!a) in yo'r !a) note)oo# for a!! the circ'its re('ired in the steps that fo!!o0+ Inc!'de a!! necessary e('ations and ca!c'!ations+ 2+ G)tain instr'ctor appro2a! for yo'r pre!a)+ 3+ >'i!d and demonstrate the s'ccessf'! operation of the fo'r state co'nter fo'nd in E hi)it 6+:+ Attempt to c!oc# the circ'it 0ith )oth a reg'!ar s0itch and de)o'nced s0itch+ Eote the difference in performance+ 9+ >'i!d and demonstrate the s'ccessf'! operation of the fo'r state co'nter from E ercise : of the re2ie0 e ercises+

Gptiona!
1+ >'i!d and demonstrate the s'ccessf'! operation of the fo'r state co'nter from E ercise 5 +

Style Guidelines

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A -!o)a! ,e t

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

; 'ore state machines

4earning o).ecti2es:
&e!ate n'm)er of states to re('ired amo'nt of memory+ Ins're state machines do not enter i!!ega! states+

$ow many bits of memory does a state machine need:

,he amo'nt of memory or n'm)er of f!ip-f!ops re('ired for a state machine is direct!y re!ated to the n'm)er of states in the state transition diagram+ ,he n'm)er of possi)!e states that can )e represented increases )y a po0er of t0o for each ne0 )it of memory added+ Gne )it of memory can represent 2 1 or t0o states% t0o )its can represent 'p to 22 or fo'r different states% and three )its 'p to 2 3 or eight different states+ ,o red'ce the comp!e ity of the design% 'se the fe0est n'm)er of f!ip-f!ops that 0o'!d sti!! accomp!ish the tas# s'ccessf'!!y+ If the design re('ired a n'm)er of states that is not a po0er of t0o% then the sma!!est n'm)er of )its raised to the po0er of t0o that is greater than the n'm)er of states re('ired sho'!d )e 'sed+ As an e amp!e% if three states 0ere re('ired% t0o )its 0o'!d )e needed% or if si states 0ere re('ired% three )its 0o'!d )e needed+ E'm)er of states Y 2n'm)er of )its

9hat are unused states:

A machine that 2isits the fo!!o0ing states in the order !isted% 000 001 011 111 110 100 000% 0i!! re('ire three )its of memory+ Bhat )ecomes of the 'n'sed states% 010 and 101C $e2era! approaches are common 0hen dea!ing 0ith the 'n'sed states+ Eote that any !ega! state mo2es to another !ega! state% ne2er 2isiting the 'n'sed states+ >eca'se the 'n'sed states are ne2er 2isited% these co'!d )e considered as don;t care conditions in the <-maps for the inp't to the f!ip-f!ops+ ,his can red'ce the comp!e ity of the design+ In addition% "&E$E, and C4EA& !ines for f!ip-f!ops can )e 'sed to ins're not on!y that the state machine enters a !ega! state 0hen po0ering on% )'t it a!so ins'res that it po0ers 'p in a specific initia! state+

Asing "&E$E, and C4EA& pins

As the system po0ers 'p% !ogic !e2e!s cannot a!0ays )e g'aranteed+ Bhat if d'ring this time% the system happened to enter one of the 'n'sed statesC Depending 'pon the !ogic that 0as 'sed% the system may then transition into one of the !ega! states% or it may get st'c# indefinite!y in one of the i!!ega! states+ In order to g'arantee that the system does not enter an i!!ega! state as the system po0ers 'p% the C4EA& !ines can )e he!d !o0 temporari!y to ins're that the memory )its are set to 1ero or !ogic !o0 on po0er 'p+ E hi)it 7+1 has an &C circ'it that can )e 'sed to po0er on to #eep the C4EA& !ine !o0 !ong eno'gh to ins're that the )its are set to 1ero+ Bhen po0er is first t'rned on% the capacitor 0i!! )e 'ncharged and m'st charge thro'gh the resistor+ If the time constant% &C% is set at se2era! c!oc# cyc!es% then the state machine 0i!! )e g'aranteed to start 0ith a!! of E hi)it 7+1: &C for "o0er Gn

Style Guidelines

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%. More state machines the memory )its at 1ero+ ,he =91=: ('ad D f!ip-f!op in the !ogic #it does not offer a "&E$E, pin+ 8o0e2er the same type of &C circ'it can )e 'sed for other f!ip-f!ops that do+

Assigning 'n'sed states to the system

"o0ering 'p is not the on!y time the machine can enter an 'n'sed state+ At times !arge transient spi#es can occ'r d'ring storms or 0hen po0ering on or off other e('ipment that can ca'se !ogic !e2e!s to change 'npredicta)!y+ In cases s'ch as this% the machine can sti!! enter a state that 0as not p!anned+ E2en the &C circ'it connected to C4EA& or "&E$E, pins cannot resc'e the state machine in this case+ ,o address this% the designer sho'!d add the additiona! states to the state transition diagram and simp!y ha2e them transition to a !ega! state+ In this 0ay% e2en if for some reason a circ'it enters an i!!ega! state% it 0i!! ('ic#!y shift to one that is a!!o0ed+ Adding the e tra states as 0e!! as the &C circ'it does indeed comp!icate the circ'it% ho0e2er for a fina! design that 0i!! )e 'sed in prod'ction% it pro2ides ass'rance that the circ'it 0i!! perform re!ia)!y e2en 0hen the 'ne pected occ'rs+

E amp!e 1: ,hree state co'nter

,he three state co'nter in E hi)it 7+2 co'nts 'p 0hen the inp't is high and co'nts do0n 0hen the inp't is !o0+ ,0o f!ipf!ops 0i!! )e needed to imp!ement this machine 0hich means that fo'r states can )e represented )y those t0o )its+ ,he state 11 is not 'sed in this design+ Bhat 0o'!d happen if for some reason% the machine 0o'!d enter the state 11C ,he effect of entering this 'n'sed or i!!ega! state cannot )e #no0n 'nti! the circ'it imp!ementation is fina!i1ed+ Instead of 0aiting to see 0hat happens after the design is comp!eted% it is )est to incorporate this state ear!y on in the design phase+ ,0o approaches 0i!! )e in2estigated+ ,he first 0i!! shift the state 11 to the !ega! 00 state on the ne t c!oc# cyc!e+ ,he ne t approach 0i!! )e to p!ace don;t care conditions for the state 11 and then e amine the ne t state that 0o'!d fo!!o0 depending 'pon the simp!est design that res'!ts from 'sing the don;t care conditions+ E hi)it 7+2: 3 state co'nter

Approach 1: 11 00
,he res'!ting state transition diagram ass'ming that state 11 transitions to 00 on the ne t c!oc# cyc!e is gi2en in E hi)it 7+3+ In a!! of the cases that fo!!o0% 'n'sed states 0i!! )e sho0n as dotted circ!es in the state transition diagram+ $ince state 11 0i!! mo2e to state 00 regard!ess of the inp't 2a!'e% it is not 0ritten on the diagram+ From the <-maps gi2en )e!o0% the ne t state 2a!'es for V1 and V0 are !isted as V1E and V0E+ It is !eft as an e ercise for the reader to determine the circ'itry re('ired to imp!ement this state machine+ E hi)it 7+3: 3 state co'nter 0ith 'n'sed state

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,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

/1'/0' /1'/0 /1/0

00 01 11

/1/0'
10

/1'/0' /1'/0 /1/0

00 01 11

/1/0'
10

x'
0 1

1 0

0 1

0 0

0 0

x'
0 1

0 1

0 0

0 0

1 0

,a)!e 26: V1EJ %V1%V0K N V1E N ; V1;V0; L V1;V0

,a)!e 27: V0EJ %V1%V0K N V1;V0; L ;V1V0;

Approach 2: Asing don;t care conditions

,he ne t approach instead p!aces don;t care conditions for the state 11 as seen in the <-maps )e!o0+ >y se!ecting the minima! e pressions% the ne t states for V1 and V0 can )e fo'nd+ ,he res'!ting e pressions can )e fo'nd to )e !ess comp!e than those from the first approach+

/1'/0' /1'/0 /1/0

00 01 11

/1/0'
10

/1'/0' /1'/0 /1/0

00 01 11

/1/0'
10

x'
0 1

1 0

0 1

d dS

0 0

x'
0

0 1

0 0

dSS d

1 0

x
1

,a)!e 30: V1EJ %V1%V0K N V1;V0; L ;V0 ,he res'!ting state transition diagram is gi2en in E hi)it 7+9+a+ Asing the don;t care conditions does simp!ify the !ogic+ Eotice that the 'n'sed state no0 goes to t0o different states depending 'pon the 2a!'e of the inp't+ ,he don;t care condition !a)e!ed as dS% 0hich is V1V0 is gro'ped 0ith the term V1;V0+ ,his res'!ts in a simp!er gro'ping% V0% )'t it does no0 ca'se the machine to is a !ogic high+ $imi!ar!y% transition from 11 to 10 0hen the inp't

,a)!e 31: V0EJ %V1%V0K N V1;V0; L ;V1

the term dSS no0 ca'ses the state 11 to transition to 01+ ,he remaining don;t cares are not contained in a gro'p% so the they 0i!! transition to 0 at the ne t state+ It is !eft to the designer to caref'!!y e amine the re('irements of the fina! circ'it to determine if indeed these are don;t care conditions+ If so% then the transition diagram sho'!d )e 'pdated to ref!ect their 'se in the !ogic simp!ification+ A samp!e timing diagram that starts on the 'n'sed state 11 and cyc!es thro'gh this ne0 diagram in E hi)it 7+9+a is gi2en in E hi)it 7+9+)+ Eotice that the first transition at time 0 is to the state 01+ From there the co'nter co'nts in re2erse as the inp't is !o0% transitioning at time 1 to state 00% at time 2 to state 10% and then )ac# to state 01 at time 3+ $ome0here )et0een time 3 and 9 inp't co'nts 'p+ ,his ass'mes that the circ'it 0i!! 'se rising edge triggered f!ip-f!ops+ goes high% )'t the state does not change 'nti! the ne t rising c!oc# edge at time 9+ From that point on% 0ith the inp't high% the co'nter E hi)it 7+9+a: 3 state co'nter 0ith don;t cares

Style Guidelines

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%. More state machines

E hi)it 7+9+): ,iming diagram for 3 state co'nter

E amp!e 2: Fi2e state machine

,he fi2e state machine sho0n in E hi)it 7+: has t0o different !oops+ Gne of the !oops transitions )et0een 000 and 111 0hi!e the other goes from 001 to 010 to 100+ ,his !ea2es three possi)!e states that are 'n'sed+ ,he tr'th ta)!e that fo!!o0s 'ses don;t care conditions for 'n'sed states 011% 101% and 110 gi2en as d1% d2% and d3 respecti2e!y+ ,he res'!ting <-maps that fo!!o0 can )e 'sed to determine the minima! e pressions+ If the 'n'sed states 0ere to immediate!y go to ne t state 000% then the minima! e pressions can )e sho0n as those !isted )e!o0+ It is !eft as an e ercise to dra0 the ne0 state transition diagram for this design+

E hi)it 7+:: Fi2e state co'nter

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,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense V2E N ;V2;V0; L V2;V1V0; V1E N ;V2;V1;V0; L V2;V1;V0 V0E N V1;V0; Eo0% if the don;t care conditions are 'sed in the design for the minima! e pressions% the comp!e ity of the res'!ts is red'ced+ V2E N ;V2;V0; L V2;V1 V1E N ;V2;V1;V0; L V2;V0 V0E N V1;V0; ,he res'!ts for V1E V2E ha2e t0o e('a!!y minima! forms+ ,he state transition diagram that 'ses the first minima! form is gi2en in the E hi)it 7+5+ Eotice that the 'n'sed state 011 goes to the !ega! state 100 if the inp't is !ogic high and another 'n'sed state% 110 0hen the inp't is a !ogic !o0+ ,o trace 0here the e terna! states 0i!! go% e amine d1 0hich corresponds to 'n'sed state 011+ For V 2E% d1 is part of gro'p V2;V1+ V2E 0i!! )e 1 regard!ess of the inp't at the ne t state+ d1 is on!y gro'ped if is 1 for V1E and not at a!! in V0E+ or ;V2;V0; L V1V0; or ;V2;V1;V0; L V1;V0

x
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

/5
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

/1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

/0 /5N /1N /0N

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 d1 0 d2 d3 0 0 0 1 d1 0 d2 d3 0 1 0 0 d1 0 d2 d3 0 0 1 0 d1 0 d2 d3 0 1 0 0 d1 1 d2 d3 0 1 0 0 d1 1 d2 d3 0

,a)!e 32: ,r'th ta)!e for : state machine It is !eft to the designer of the machine to determine if these transitions are accepta)!e gi2en the specifications for the prod'ct+

/1'/0' /1'/0
00 01

/1/0
11

/1/0'
10

/1'/0' /1'/0 /1/0

00 01 11

/1/0'
10

x'/5'
00

1 0 0 0

0 d2 d2 0

d1 0 0 d1

1 d3 d3 1

x'/5'
00

1 0 0 0

0 d2 d2 1

d1 0 0 d1

0 d3 d3 0

x'/5
01

x'/5
01

x/5
11

x/5
11

x/5'
10

x/5'
10

,a)!e 33: /5N

,a)!e 39: /1N

/1'/0' /1'/0
00 01

/1/0
11

/1/0'
10

x'/5'
00

1 1 1 1

0 d2 d2 0

d1 0 0 d1

0 d3 d3 0

x'/5
01

x/5
11

x/5'
10

,a)!e 3:: /0N

Style Guidelines

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%. More state machines It sho'!d )e noted that a!! of the designs sho0n in this te t ha2e 'sed on!y the D f!ip-f!op+ 8o0e2er% it can often )e the case that another type can res'!t in a simp!er design+ J< f!ip-f!ops can )e 'sed to prod'ce ripp!e co'nters 0ith minima! e tra circ'itry+ ,he J< f!ip-f!op does ha2e t0o inp'ts% so the res'!ting !ogic minimi1ation m'st )e done for )oth the J and the < inp't% do')!ing the n'm)er of <-maps re('ired+ In order to red'ce the re('ired n'm)er of parts for the !ogic #it% on!y the D f!ip-f!op 0as 'sed+ Designers sho'!d )ecome fami!iar 'sing a!! of the different types of f!ip-f!ops so that they can )e ass'red that they ha2e chosen the one that tr'!y res'!ts in a minima! design+

E hi)it 7+5: Fi2e state co'nter 0ith 'n'sed states

&e2ie0 e ercises
1+ A state machine re('ires = different states+ 8o0 many f!ip-f!ops are re('ired for this machineC JaK If a machine has no e terna! inp'ts% 0hat si1e is the <-map for one of the re('ired inp'tsC J)K If the machine has one e terna! o'tp't% ho0 !arge is the <-map for one of the f!ip-f!op inp'tsC JcK If the design 0ere to 'se J< instead of D f!ip-f!ops% ho0 many ne t state inp'ts m'st )e determinedC 2+ &epeat E ercise 1 for a state machine 0ith 19 states+ 3+ Dra0 si c!oc# p'!ses of the timing diagram for the machine that 'ses the state transition diagram fo'nd in E hi)it 7+5+ Ass'me that the c!oc# for the machine has a period of 1+00 seconds% that the machine is in state 011 prior to time 1ero and that inp't is #ept at !ogic high the entire time+ 9+ A state machine tra2erses the states !isted in this order 000 001 011 111 110 100 000+ ,here is no e terna! inp't+ JaK Dra0 the state transition diagram for this machine+ J)K Bhat are the 'n'sed statesC JcK Modify the diagram if the 'n'sed states transition to 000+

:6

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense JdK Ass'ming a state machine 0ere to )e )'i!t 'sing D f!ip-f!ops% determine the 2a!'e of the ne t state for each of the f!ip-f!ops+ :+ ,he t0o )it se('ence 00 01 11 10 00 is a -ray code+ -ray codes on!y ha2e one )it change for each transition+ JaK $#etch the state transition diagram for the 3 )it -ray code: 000 001 011 010 110 111 101 100 000 +++ + J)K Ass'ming a state machine 0ere to )e )'i!t 'sing D f!ip-f!ops% determine the 2a!'e of the ne t state for each of the f!ip-f!ops+ 5+ A t0o )it co'nter is to )e )'i!t that 0i!! co'nt for0ard% 00 01 10 11 00% 0hen a !ogica! inp't is set high and co'nts in re2erse order 0hen it is !o0+ a+ Dra0 the state transition diagram for this state machine+ )+ Ass'ming a state machine 0as to )e )'i!t 'sing D f!ip-f!ops% determine the 2a!'e of the ne t state for each of the f!ip-f!ops+ =+ A t0o )it co'nter is to )e )'i!t that 0i!! co'nt for0ard% 00 01 10 11 00% 0hen a !ogica! inp't is set high and as a -ray code 0hen it is !o0 J00 01 11 10 00K+ JaK Dra0 the state transition diagram for this state machine+ J)K Ass'ming a state machine 0as to )e )'i!t 'sing D f!ip-f!ops% determine the 2a!'e of the ne t state for each of the f!ip-f!ops+

"roced're
1+ Brite the pre!a) in yo'r !a) note)oo# for a!! the circ'its re('ired and the steps that fo!!o0+ Inc!'de a!! necessary e('ations and ca!c'!ations+ 2+ G)tain instr'ctor appro2a! for yo'r pre!a)+ 3+ Ho'r instr'ctor 0i!! pic# one or more state machines from the 2ario's e amp!es from the re2ie0 e ercises for yo' to )'i!d and demonstrate+

Style Guidelines

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,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

!0 9hat(s next:
8opef'!!y% this introd'ction has 0hetted yo'r appetite for this fascinating s').ect+ Modern techno!ogy simp!y 0o'!d not )e possi)!e 0itho't the ad2ances and app!ications of this s').ect in the 0or!d in 0hich 0e !i2e+ A!! of the se('entia! circ'its sho0n in the chapters ?$tate machines@ and ?More state machines@ are synchrono's% meaning they 'se a c!oc#+ 8o0e2er% se('entia! circ'its designed 0itho't c!oc#s% #no0n as asynchrono's circ'its% can )e designed+ As the c!oc# can often insert added de!ay for the faster components in the circ'it% asynchrono's circ'its can 's'a!!y )e designed that 0i!! respond e2en faster than synchrono's circ'its+ ,iming iss'es )ecome critica! in this case% and the res'!ting timing ana!ysis can )ecome so comp!icated that asynchrono's circ'its are often not chosen o2er their synchrono's co'nterparts+ 8o0e2er% for circ'its that re('ire the fastest speed possi)!e% often asynchrono's circ'its are considered+ In addition% 0hi!e the circ'its designed in these !a)s a!! 'sed discrete components% for circ'its that are 'sed in app!ications today% near!y a!! of the components are fa)ricated on a sing!e chip+ Either "rogramma)!e 4ogic De2ices J"4DsK can )e 'sed to fit entire state machines on a sing!e chip or c'stom chips can )e fa)ricated for a specific tas#+ Dery !arge-sca!e integration JD4$IK techni('es are 'sed to design entire systems on a sing!e chipF a C"A 0ith cache memory and a graphics processing 'nit 0o'!d )e an e amp!e+ Comp!e ities that re('ire additiona! ana!ysis are 0hen the si1e of the transistors is decreased% speeds of the circ'its are increased% and the desired po0er cons'mption is !o0ered+ 8ard0are description !ang'ages s'ch as Deri!og can e2en )e 'sed to synthesi1e and test circ'it performance 2irt'a!!y in soft0are )efore constr'cting a sing!e de2ice+ Any one of these areas can pro2ide a 0ea!th of cha!!enging pro)!ems to tac#!e+ It is the hope of this a'thor that the fo'ndation gained from this te t 0i!! pro2e 'sef'! as yo' 'se techno!ogy and design app!ications that re('ire digita! !ogic+

Style Guidelines

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,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

,%%endix ,< Chi% %inouts

E hi)it A+1: =900

E hi)it A+2: =902

E hi)it A+3: =909

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&ppendix &' (hip pinouts

E hi)it A+9: =910

E hi)it A+:: =91:1

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,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

E hi)it A+5: =91=:

Style Guidelines

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A -!o)a! ,e t

&ppendix &' (hip pinouts

555 Timer

E hi)it A+=: ::: timer

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,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

,%%endix /< 7esistors and ca%acitors

7esistors
&esistors are e!ectronic components that o)ey Ghm;s !a0: Do!tage across a resistor is e('a! to the c'rrent thro'gh the resistor times the resistance of the de2ice+ 9=I:. &esistance is meas'red in ohms J ) . C'rrent and 2o!tage are re!ated )y the resistance of the o).ect% if 2o!tage is #ept constant and resistance rises% c'rrent 0i!! fa!!+ 4i#e0ise if resistance decreases% more c'rrent 0i!! f!o0% meaning the meas're of the c'rrent 0i!! rise+ Bhi!e many de2ices ha2e resistance% inc!'ding the 0ire 'sed in these !a)s% the on!y resistance that 0e 0i!! )e concerned 0ith in this man'a! is the resistance attri)'ted to act'a! resistors+ Man'fact'red resistors come in 2ario's forms% ho0e2er those 'sed here 0i!! )e standard Z 0att resistors that fo!!o0 the con2entiona! co!or code that descri)es their 2a!'e+

COLOR VALUE MNEMONIC Black Brown Red Orange Yellow Green 0 1 2 3 4 5 ! $ & ) Better Be Right Or Your Great Big Venture Goes West

E hi)it >+1: $amp!e &esistor Each resistor has fo'r co!ored stripes as sho0n in the fig're a)o2e+ Each stripe corresponds to a n'm)er as sho0n in ,a)!e 35+ ,he form'!a for the 2a!'e of each resistor is !isted )e!o0+ ;ene "! <o +ula' A B Bhich for this case yie!ds: 2 0 x 10C 103 or 20%000 X+

Bl e V"ole# Gra% '("#e

,a)!e 35: Co!or Codes

,he first t0o stripes indicate the n'merica! 2a!'e of the resistance% the third the e ponent of ten 0hich 0i!! )e m'!tip!ied )y the n'm)ers from the first t0o stripes% and the fo'rth a to!erance of the resistor+ ,he diagram a)o2e i!!'strates ho0 the first three stripes are 'sed to ca!c'!ate the 2a!'e of the resistor as 0e!! as the diagram )e!o0+ ,he mnemonic is often s'ggested as a means of remem)ering the co!or

Style Guidelines

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A -!o)a! ,e t

&ppendix )' *esistors and capacitors code+ ,he to!erances 0i!! not )e 'ti!i1ed in this !a) man'a!+ Another e amp!e is pro2ided in E hi)it >+2+ App!ying the form'!a to o)tain the 2a!'e for this resistor is !eft as an e ercise for the reader+

E hi)it >+2: 100%000 Ghm &esistor

Ca%acitors
In direct c'rrent circ'its% capacitors can )e tho'ght of as charge storage de2ices+ E!ectro!ytic capacitors 0i!! )e 'sed in these !a)s+ E!ectro!ytic capacitors appear to !oo# !i#e a tiny a!'min'm can 0ith t0o 0ires+ >e ca'tio's 0hen connecting the e!ectro!ytic capacitors as they ha2e a po!arity+ Ins're that the negati2e termina! of the capacitor is connected proper!y or the capacitor can ma!f'nction and in some cases e p!odeM ,he 'nit of meas'rement for capacitors is the Farad+ Capacitors 0ith higher Farad meas'rements can store more charge at a gi2en 2o!tage+ E hi)it >+3: Capacitors

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,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

,%%endix C< Lab noteboo0

,he !a) note)oo# sho'!d )e a )o'nd note)oo#% m'ch !i#e a standard composition note)oo#+ ,he !a) note)oo# is 'sed to doc'ment the e periment or !a) proced're+ Eote)oo#s can ser2e many p'rposes: for the a'thor to re2ie0 the materia!% for someone e!se to rep!icate the proced're% or e2en as a !ega! doc'ment for 'se in patent or co'rt proceedings+ ,he note)oo# for these e periments 0i!! )e informa!% in that the st'dent 0i!! hand 0rite a!! of the content in the note)oo#+ Do not misinterpret the meaning of informa!% )eca'se the 0or# sho'!d sti!! )e neat% !egi)!e% 0e!! organi1ed% and comp!ete+ Bhat fo!!o0s are some g'ide!ines that sho'!d )e 'sed to doc'ment the !a)s from this te t+ Gf co'rse yo'r instr'ctor may add or de!ete from this !ist+ ,he !a) note)oo# sho'!d:
)e )o'nd ha2e t0o to three pages at the front dedicated to a ta)!e of contents ha2e n'm)ered pages to 'se in the ta)!e of contents Jyo' may n'm)er them yo'rse!fK

Each !a) sho'!d contain:

name of !a) yo'r name partnerJsK nameJsK date )rief o).ecti2e of !a) Jno more than t0o sentencesK e('ipment !ist re('ired pre-!a) inc!'ding: any necessary diagrams any necessary e('ations and ca!c'!ations appro2a! of instr'ctor )efore yo' )egin the !a) e ercise res'!ts and o)ser2ations conc!'sion

Ma#e s're that yo':

Do not erase any items+ Cross them o't and redo the 0or#+ Brite on!y on the right side of each page+ ,his !ea2es yo' room to inc!'de any corrections+

Bhi!e fo!!o0ing these g'ide!ines certain!y ma#es it easier for yo'r instr'ctor to re2ie0 yo'r 0or#% that is not its main p'rpose+ <eep in mind% someone sho'!d )e a)!e to 'nderstand 0hat yo' did and e2en rep!icate yo'r 0or# gi2en yo'r !a) note)oo#+ Ho'r !a) note)oo# can )e a he!pf'! doc'ment for yo'+ In ind'stry% it can a!so )e a he!pf'! doc'ment for others+

Style Guidelines

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,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

,%%endix D< /oolean algebra

Co++u#a#"(e la$' LyNyL yNy Asso!"a#"(e la$' L Jy L 1K N J L yK L 1 Jy1K N J yK1 D"s# ")u#"(e !a0: Jy L 1K N y L 1 L Jy1K N J L yKJ L 1K A)so &#"on' L J yK N J L yK N De Mo gan's la$' J L yK; N ;y; J yK; N ; L y; 4#he la$s and & o&e #"es' J ;K; N L1N1 J K0 N 0 L0N J K1 N L ;N1 J K ;N0 J K N L N

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,%%endix E< E=ui%ment list

V'antity 1 2 2 2 2 2 9 9 2 3 3 2 2 1 1 Item Digita! ,rainer pn2222 transistors 1<X 1I9 0att resistors 33<X 1I9 0att resistors 9+=<X 1I9 0att resistors 100<X 1I9 0att resistors =900 =902 =909 =910 =91:1 =91=: ::: timer 100 Farad capacitor 0+01 Farad capacitor V'ad 2 inp't EAED% see note regarding =900 series chips V'ad 2 inp't EG& 5 in2erters 3% 3 inp't EAED 6 inp't m'!tip!e er V'ad D f!ip-f!op 0ith C4EA& Description $ee detai!ed description )e!o0+ Gther genera! p'rpose npn transistors may )e s')stit'ted+

Digital trainer
A digita! trainer is a sing!e p'rpose 'nit that contains se2era! feat'res that faci!itate the constr'ction and testing of digita! circ'its+ Digita! trainers can )e constr'cted% )'t can )e fo'nd as a 'nit for a reasona)!e price+ A digita! trainer sho'!d inc!'de:
A )read)oard A :D po0er s'pp!y 0hich reg'!ates 0ithin [0+2:D of :D 6 4EDs that are 0ired to t'rn on 0ith !ogic 1 and off 0ith !ogic 0 5 $"D, s0itches that are 0ired to !ogic high J:DK or !ogic !o0 J0DK 2 $"D, de)o'nced s0itches Jcons'!t E hi)it 6+10 if constr'cting a digita! trainerK

5+00 series families

$e2era! of the =900 series fami!ies are accepta)!e for 'se 0ith these !a)s+ ,he 4$ J4o0 "o0ered $chott#yK% A4$ JAd2anced 4o0 "o0ered $chott#yK or 8C J8igh speed CMG$K are a!! 0ide!y a2ai!a)!e% re!ati2e!y ine pensi2e and 0i!! a!! perform accepta)!y+

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,%%endix F< 6olutions

Cha%ter ! re"iew exercises
2+ E hi)it 1+3 contains the diagram i!!'strating the common!y connected pins on the )read)oard+ 3+ x 0 1 x! 1 0

9+ &esistor co!or codes are e p!ained in detai! in Appendi >+

a+

)+

c+

d+

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&ppendix +' $olutions

:+ ,he gro'nd sym)o! is gi2en here+

5+ ,he EAED is the opposite of the AED gate+ ,he f'nction has t0o different 2aria)!es% each 0ith t0o distinct ans0ers J,-1 or F-0K% so there sho'!d )e fo'r J2 2K different possi)i!ities for the f'nction+

A 0 0 1 1
=+

B 0 1 0 1

(AB)' 1 1 1 0

A 0 0 1 1

B 0 1 0 1

(A+B)' 1 0 0 0

Cha%ter # re"iew exercises

1+ A !ogic f'nction 0ith three inp'ts has eight ro0s )eca'se each of the three inp'ts has t0o possi)i!ities+ Jn'm)er of possi)!e o'tcomes for each inp'tKJn'm)er of inp'tsK N 23 2+ A f'nction 0ith fi2e inp'ts 0i!! ha2e 2: or 32 different ro0s+ 3+ ,r'th ta)!es fo!!o0+ It is often easier to o)tain the fina! res'!t if some of the intermediate 2a!'es that might )e necessary are o)tained first+ For e amp!e% in 3+a+ the third co!'mn is A>% the fo'rth JA>K; and the fifth is >;+ ,hese are then 'sed to o)tain the fina! res'!t+ A 0 a+ yJA%>K N JA>K; L >; 0 1 1 B 0 1 0 1 AB 0 0 0 1 (AB)' 1 1 1 0 B' 1 0 1 0 y 1 1 1 0

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,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

A 0 0 0 )+ yJA%>%CK N JAL>K;C 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

A+B 0 0 1 1 1 1 1 1

(A+B)' 1 1 0 0 0 0 0 0

y 0 1 0 0 0 0 0 0

A 0 0 0 c+ yJA%>%CK N JACK; L J>CK 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

A+B 0 0 1 1 1 1 1 1

(A+B)' 1 1 0 0 0 0 0 0

y 0 1 0 0 0 0 0 0

It may not a!0ays )e necessary to 0rite e2ery intermediate step+ In this case% JACK; is 0ritten direct!y instead of first 0riting JACK and then the in2erse+ If yo' find this conf'sing% ma#e s're not to s#ip steps !i#e this+ Eote that many different f'nctions can yie!d the same res'!t+ For e amp!e% JA>;CK; is e('i2a!ent to the f'nction a)o2e+

A 0 0 0
d+ yJA%>%CK N JA>KC;

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

AB 0 0 1 1 1 1 0 0

C' 1 0 1 0 1 0 1 0

y 0 0 1 0 1 0 0 0

0 1 1 1 1

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&ppendix +' $olutions

A 0
e+ yJA%>K N A; L >

B 0 1 0 1

A' 1 1 0 0

y 1 1 0 1

0 1 1

f+ yJA%>%CK N JJAL>K;J>LCK;K; A B C A+B B+C (A+B)' (B+C)' (A+B)'(B+C)' y

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 1 1 1 1 1 1

0 1 1 1 0 1 1 1

1 1 0 0 0 0 0 0

1 0 0 0 1 0 0 0

1 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1

Another e amp!e of a !ogic f'nction 0ith a different e('i2a!ent% JA L > L CK+

9+ $o!'tion 0ith pino't )e!o0+

:+ $o!'tion 0ith pino't )e!o0+ It is optiona! to !a)e! Dcc and -nd on the diagram+ Most often for a chip% the Dcc is the 'pper most right pin and the -nd is the )ottom !eft% ho0e2er the chip pino't sho'!d a!0ays )e cons'!ted+

5+

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Cha%ter & re"iew exercises

1+

JA>K; L JCDK; K;JA>K;; JCDK;; JA>KJCDK A>CD Grigina! Circ'it De Morgan;s !a0 Do')!e negati2es cance! "arenthesis not necessary 2+ $ing!etons ha2e on!y one e!ement+ Do')!es are 2 1 rectang!es+ -ro'ps of fo'r ta#e t0o forms% a 9 1 rectang!e or a 2 2 s('are+ Fina!!y gro'ps of eight ta#e the form of 9 2 rectang!es+ &ectang!es and s('ares can )e sp!it across )ordersF f'rther i!!'strations of this can )e fo'nd in the ne t chapter+ E amp!e gro'pings are sho0n )e!o0+ A'B' A'B
00 01

AB
11

AB'
10

A'B' A'B AB
00 01 11

AB'
10

A'B' A'B
00 01

AB
11

AB'
10

C'D'
00 01 11

0 0 0 1

0 0 1 0

0 0 0 0

0 1 0 0

C'D'
00 01 11

0 0 1 1

0 0 0 0

0 1 0 0

0 1 0 0

C'D'
00 01 11

1 1 1 1

0 0 0 0

1 1 0 0

1 1 0 0

C'D CD CD'
10

C'D CD CD'
10

C'D CD CD'
10

,hree sing!e gro'ps

,0o 2 1 do')!e gro'pings

,0o gro'pings of fo'r

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&ppendix +' $olutions

A'B A'B AB 01 11 '

00

AB'
10

A'B' A'B
00 01

AB
11

AB'
10

A'B' A'B AB
00 01 11

AB'
10

C'D '
00 01 11

C'D'
00

1 0 0 1

0 0 0 0

0 0 0 0

1 0 0 1

C'D'
00

1 1 0 0

1 1 0 0

1 1 0 0

1 1 0 0

C'D CD CD'
10

1 0 0

0 0 0

0 0 0

1 0 0

C'D
01 11

C'D
01

CD CD'
10

CD
11

CD'
10

-ro'p spanning )o'ndary

Fo'r corner gro'p

-ro'p of eight

3+ ,r'th ta)!es fo!!o0+ A B C 0 0 0 0 0 0 a+ fJA%>%CK N A> L A;>C; L A>;C 0 1 1 1 1 1 1 0 1 1 1 0 1 1 0 1 AB 0 0 0 0 0 0 1 1 A'BC' AB'C 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 f 0 0 1 0 0 1 1 1

0 0

A B C 0 0 0 0 0 0 )+ gJA%>%CK N A;C L A>C L A>; 0 1 1 1 1 1 1 0 1 1 1 0 1 1 0 1

A'C 0 1 0 1 0 0 0 0

ABC 0 0 0 0 0 0 0 1

AB' 0 0 0 0 1 1 0 0

g 0 1 0 1 1 1 0 1

0 0

=:

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense c+ hJA%>%C%DK N A;>C; L JA >KC L A;>;C;D L A>CD A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A'BC' 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 (AB) 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 (AB)C 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 A'B'C'D 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ABCD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 h 0 1 0 0 1 1 1 1 0 0 1 1 0 0 0 1

A 0 0 0 0 0 0 0 d+ JA%>%C%DK N A;C;D; L C;D L CD 0 1 1 1 1 1 1 1 1

B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

A'C'D' 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0

C'D 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

CD 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1

= 1 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1

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&ppendix +' $olutions 9+ Minima! e pressions gi2en for each map+ Eotice that ('ite often% the terms in the origina! are not fo'nd at a!! in the minima! $G" J$'m Gf "rod'ctsK e pression+ a+ Grigina! e pression: fJA%>%CK N A> L A;>C; L A>;C Minima! e pression: fJA%>%CK N >C; L AC

)+ Grigina! e pression: gJA%>%CK N A;C L A>C L A>; Minima! e pression: gJA%>%CK N A>; L C

c+ Grigina! e pression: hJA%>%C%DK N A;>C; L JA >KC L A;>;C;D L A>CD Minima! e pression: hJA%>%C%DK N A;> L A;C;D L >CD L A>;C Minima! e pression: hJA%>%C%DK N A;> L A;C;D L ACD L A>;C More than one minima! e pression e ists+ In these cases% more than one correct ans0er e ists+

d+ Grigina! e pression: .JA%>%C%DK N A;C;D; L C;D L CD Minima! e pression: .JA%>%C%DK N D L A;C;

==

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense :+ gJA%>%CK N A>; L C ,his circ'it 0as designed 'sing on!y EAED gates+ ,his a!!o0s the circ'it to )e imp!emented 0ith .'st one chip+ DeMorgan;s !a0 0as 'sed to a2oid needing a EG& gate+ In addition% an in2erter 0as a2oided )y 'sing the remaining EAED gate !eft on the chip to in2ert inp't A+

5+ hJA%>%C%DK N A;> L A;C;D L >CD L A>;C

=+ As the !ogic #it does not contain a fo'r inp't EAED gate% com)inations of three and t0o inp't EAEDs are 'sed+ ,he fo!!o0ing .'stification sho0s that this is indeed a correct imp!ementation+ a+ Minima! e pression: A; L >; \ JA;>K; JA;C;DK; ]; ; \ J>CDK; JA>;CK; ]; ; K; \ JA;>K; JA;C;DK; ]; ;; L \ J>CDK; JA>;CK; ]; ;; \ JA;>K; JA;C;DK; ]; L \ J>CDK; JA>;CK; ]; \ JA;>K;; LJA;C;DK;;] L \ J>CDK;; L JA>;CK;; ]

A;> L A;C;D L >CD L A>;C; Style Guidelines =6 A -!o)a! ,e t

&ppendix +' $olutions )+ Minima! e pression: C; L A;> Direct imp!ementation from circ'it De Morgan;s !a0 Do')!e negati2es cance! De Morgan;s !a0

Do')!e negati2es c+ ,0o different Minima! e pressions e ist for this pro)!em+

i+ Minima! e pression: C;D; L A;C; L >C; L AC

ii+ Minima! e pression: C;D; L A;C; L A> L AC

=7

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense d+ ,hree different Minima! e pressions e ist for this pro)!em+ $ee )e!o0+

i+ Minima! e pression: A;C;D L A;>D L A;CD; L A>;D

ii+ Minima! e pression: >;C;D L A;>D L A;CD; L A>;D

iii+ Minima! e pression: A;C;D L A;>C L A;CD; L A>;D

Cha%ter + re"iew exercises

1+ Minima! $G" e pressions

a+ Minima! e pression: >; L AC;

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&ppendix +' $olutions

)+ Minima! e pression: A L C

c+ Eotice that this so!'tion has one of the gro'pings that spans the )o'ndaries J>;CK+

Minima! e pression: A>;L AD L >;C

d+ ,his e pression inc!'des the fo'r corner gro'ping J>;D;K+

Minima! e pression: >;D; L A;>

e+ ,0o different Minima! e pressions e ist for this pro)!em+

Minima! e pression: >;C; L A;C; L >C+

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,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

Minima! e pression: >;C; L A;> L >C

f+ Minima! e pression: C;D L A;D;

2+ <-maps 0ith minima! $G" e pressions

a+ Minima! e pression: A> L A;C;

)+ Eotice that not a!! don;t care conditions need to )e co2ered+

Minima! e pression: A

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&ppendix +' $olutions

c+ Minima! e pression: >D L AD L A;>;C

d+ Minima! e pression: CD; L AD;

Cha%ter . re"iew exercises

1+ <- map and minima! $G" e pressions a+ f1Ja%)%cK N a;);c; L a;)c; L a;)c L a);c; Minima! e pression: f1Ja%)%cK N a;) L );c;
a 0 0 0 0 1 1 1 1 ) 0 0 1 1 0 0 1 1 ! 0 1 0 1 0 1 0 1 f1 1 0 1 1 1 0 0 0

63

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense )+ f2Ja%)%cK N a;);c L a;)c L a)c; L a);c Minima! e pression: f2Ja%)%cK N a;c L );c La)c;
a 0 0 0 0 1 1 1 1 ) 0 0 1 1 0 0 1 1 ! 0 1 0 1 0 1 0 1 f1 0 1 0 1 0 1 1 0

c+ f3Ja%)%c%dK N a;);c;d; L a;)cd L a)cd L a);c;d; L a);c;d Minima! e pression: f3Ja%)%c%dK N );c;d; L a);c; L )cd
a 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ! 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 d 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 f6 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1

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&ppendix +' $olutions d+ f9Ja%)%c%dK N a;);c;d; L a;)c;d L a)cd L a;);cd; L a;);cd L a;)cd; L a);c;d Minima! e pression: f9Ja%)%c%dK N a;);c L a;cd; L a;);d; L a)cd L a;)c;d L a);c;d a ) ! d 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 0 1 1 0 1 1 f8 1 0 1 1 0 1 1 0 0 1 0 0 0 0 0 1 Mux In d; d; 1 1 d d d; d; d d 0 0 0 0 d d

1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 1 1 1 0 0 1 0 1 1 1 1 0 1 1

,he tr'th ta)!e a!so sho0s the inp'ts re('ired for the m'!tip!e er 0hich 0i!! )e 'sed !ater 0hen imp!ementing the f'nction 0ith a m' +

6:

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense 2+ f2Ja%)%cK N a;);c L a;)c L a)c; L a);c

3+ f9Ja%)%c%dK N a;);c;d; L a;)c;d L a)cd L a;);cd; L a;);cd L a;)cd; L a);c; E amine the tr'th ta)!e from pre2io's pro)!em to 'nderstand 0hy inp't 2a!'es are chosen+

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&ppendix +' $olutions 9+ Circ'it design a+ g1Ja%)%c%dK N a;);c;d L a)cd L a;)cd L a;)c;d L a);c;d L a;);cd L a)c;d L a);cd Minima! e pression: g1Ja%)%c%dK N d Bhen the <-map is fi!!ed o't% it can )e seen that the minima! so!'tion is simp!y d+ Eo !ogic is needed at a!!M 8opef'!!y% yo' did not try to 0rite the tr'th ta)!e and imp!ement it 0ith a m'!tip!e er+ ,his i!!'strates 0hy e2en tho'gh a m'!tip!e er can imp!ement any circ'it% the !ogic sho'!d )e ana!y1ed first+ a')'
00

a')
01

a)
11

a)'
10

!'d'
00 01 11

0 1 1 0

0 1 1 0

0 1 1 0

0 1 1 0

!'d !d !d'
10

)+ g2Ja%)%c%dK N a;)c;d L a;);cd; L a);cd For this pro)!em% first the <-map sho0s that this is the minima! e pression+ ,hen the tr'th ta)!e is constr'cted to determine the inp't 2a!'es for an 6-to-1 m' imp!ementation+
a 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ! 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 d 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 g5 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 Mux In&u# 0 0 d; d; d d 0 0 0 0 d d 0 0 0 0

a')'
00

a')
01

a)
11

a)'
10

!'d'
00

0 0 0 1

0 1 0 0

0 0 0 0

0 0 1 0

!'d
01

!d
11

!d'
10

6=

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

c+ g3Ja%)%c%dK N a)c;d; L a)c;d L a)cd L a)cd; L a;)c;d L a;)cd Minima! e pression: a) L )d ,he Minima! e pression is the co!'mn a) and the midd!e s('are )d+ ,his can )e imp!emented 0ith a sing!e =900 chip 0ith one EAED gate !eft o2er+

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A -!o)a! ,e t

&ppendix +' $olutions d+ g9Ja%)%c%dK N a;)c;d; L a)c;d; L a)cd; L a);cd; L a;)c;d L a)c;d L a)cd L a);cd Minima! e pression: )c; L ac

Cha%ter 4 re"iew exercises

1+ "eriods in seconds of the c!oc# 0ith gi2en fre('encies a+ , N 1If , N 1IJ5%000%000K N 0+00000015= sec or 15= nsec )+ , N 1IJ10%000%000K N 0+0000001 sec or 100 nsec c+ f N 5000 cyc!esImin S 1minI50sec N 100 81 , N 1I100 N 0+01 sec or 10+0 msec 2+ Fre('ency of c!oc# in 8ert1 a+ f N 1I, f N 1IJ+00001K N 100 <h1 )+ f N 1IJ0+0000000000:K N 20+0 -81 c+ f N 1IJ+001K N 1000 81

67

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense 3+ Eotice that "in 3 ne2er changes% a!tho'gh the state for "in 5 and "in 10 Jthe o'tp'tK are indeterminate 'nti! it can )e 2erified that the !ogic has s'ccessf'!!y tra2e!ed thro'gh the re('ired !ogic gates+

9+ ,he !ogic circ'it from E hi)it 2+19 has eight !ogic gates+ Many of these gates are in para!!e!% s'ch as the first t0o in2erters or the t0o EAED chips from IC1+ ,he !ongest path for the !ogic to tra2e! is 0hat determines the ma im'm fre('ency that the c!oc# can )e tra2e!ed+ $o the !ongest de!ay is: J10nsec S :K N :0 nsec f N 1I, N 1IJ0+0000000:K N 20+0 M81 :+ ,imers 0ith times of 1% :% and 10 seconds a+ &eca!! that the timer has a de!ay of: t = 1+10J&CK $o!2ing for & yie!ds: & N tIJ1+10CK ,he re('ired 2a!'es for & are fo'nd in the ta)!e% a!ong 0ith those that are easiest to o)tain 'sing the resistors from the !a) #it+ # > des" ed 1+0 sec :+0 sec 10+ sec . des" ed 7100 * 9:000 * 71000 * . fo la) 7900 *+ 92900 *+ 100000 *+ # - a!#ual 1+0 sec 9+= sec 11 sec

)+ ,he first & is o)tained )y p'tting t0o of the 9+= < resistors in series+ ,he second is )y p'tting t0o 9+=< resistors in series 0ith a 33< resistor+ Style Guidelines 70 A -!o)a! ,e t

&ppendix +' $olutions c+ ,he schematic sho'!d !oo# identica! to E hi)it 5+1 0ith the appropriate 2a!'es for & and C+ d+ 4ast% for the 2a!'es chosen% the span for the times is ca!c'!ated )e!o0+ i+ , second timer: ii+ - second timer: 1+10J0+7: S 7900KJ0+7 S 100'K T act'a! T 1+10J1+0: S 7900KJ1+1 S 100'K 1+10J0+7: S 92900KJ0+7 S 100'K T act'a! T 1+10J1+0: S 92900KJ1+1 S 100'K +67 T act'a! 2a!'e T 1+2 9+0 T act'a! 2a!'e T :+9 iii+ ,. second timer: 1+10J0+7: S 100000KJ0+7 S 100'K T act'a! T 1+10J1+0: S 100000KJ1+1 S 100'K 7+9 T act'a! 2a!'e T 13 5+ &eca!! that the period of the c!oc# is gi2en )y: , N t1 L t2 N time on L time off N 0+573J&1 L &2KC L 0+573J&2KC N 0+573J&1 L 2S&2KC a+ If &1 and &2 are )oth 9+=< resistors for the first c!oc# and &1 is 9+=< and &2 is 33< for the second% the res'!ting times are: ,J1secK N 0+573J9=00 L 9=00K0+0001 L +573J9=00K0+0001 N 0+5:1 L 0+325 N +76 seconds ,J:secK N 0+573J33000 L 9=00K0+0001 L +573J33000K0+0001 N 2+51 L 2+27 N 9+7 seconds )+ ,ime on for the 1 second c!oc# is 0+5: seconds and off is 0+33% 0hi!e time on for the : second c!oc# is 2+5 seconds and off is 2+3 seconds+ c+ ,he schematic 0i!! !oo# e act!y !i#e E hi)it 5+3 0ith the appropriate & and C 2a!'es inserted+

71

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

Cha%ter 5 re"iew exercises

1+ &eca!!% if either of the inp't 2a!'es are 1% the o'tp't of the gate is 0+ Bhi!e the o'tp't 2a!'es of V and V; may change% the inp't 2a!'es of $ and & 0i!! not for this ta)!e+ $o% for any ro0 that has $ set to 1% the corresponding 2a!'e for VE; m'st )e 0 and !i#e0ise if & is 1% V E m'st )e 0+ Asing this% some 2a!'es can immediate!y )e determined 0ith this information+ As the o'tp't 2a!'es may change% the remaining ne t state 2a!'es re('ire more e amination+ 0 0 0 0 1 1 1 1 . 0 0 1 1 0 0 1 1 / 0 1 0 1 0 1 0 1 /' 1 0 1 0 1 0 1 0 /N / / 0 0 / / 0 0 /N' / / / / 0 0 0 0

.o$ 1: V; is 1% ca'sing V to )e 0 !ea2ing V; 1+ .o$ 5' V is 1% ca'sing V; to )e 0 !ea2ing V 1For ro0s 1 and 2% the state of V and V; does not change+ .o$ 6 ? 8: VE and $ are 0% ca'sing V E ; to )e 1+ VE ; at 1 means VE is 0+For ro0s 3 and 9% the !atch is reset+ .o$ @ ? A' VE ; and & are 0% ca'sing V E to )e 1+ VE at 1 means VE; is 0+ For ro0s : and 5% the !atch is set+ .o$ B ? C' VE and VE; are not in2erse 2a!'es of each other% 0hich e p!ains 0hy these states are not 'sed for the !atch+ Fina! sta)!e 2a!'es are pro2ided in the second tr'th ta)!e+

0 0 0 0 1 1 1 1

. / /' /N
0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 . , 0 0 , , 0 0

/N'
, . , , 0 0 0 0

Style Guidelines

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&ppendix +' $olutions 2+ For the $& !atch constr'cted 0ith EAED gates% reca!! that the EAED gate 0i!! ha2e an o'tp't of 1 if either of the inp't 2a!'es is 0+ In this manner% some of the ne t state 2a!'es may )e determined immediate!y+ 0 0 0 Eo0% the remaining 'ndetermined ro0s are e amined+ 0 1 1 1 1 . 0 0 1 1 0 0 1 1 / /' 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 /N 1 1 1 1 / / / / /N ' 1 1 / / 1 1 / /

.o$s 1 ? 5: >oth VE and VE ; are 1% not in2erses of one another+,hese states are not 'sed+ .o$s 6 ? 8: VE is 1 and & is 1% so V E ; 0i!! )e 0+ ,hese are the set states+ .o$s @ ? A: VE ; is 1 and $ is 1% so V E 0i!! )e 0+ ,hese are the reset states+ .o$ B: $ and V; are 1% so V E 0i!! stay 0+ VE is 0 and & is 1% so V E ; stays 1 .o$ C: & and V are 1% so V E ; 0i!! stay 0+ VE ; is 0 and $ is 1% so VE stays 1+&o0s = and 6 are t sta)!e states 0here the o'tp't 2a!'es do not change+ 0 0 0 Fina! 2a!'es are pro2ided in the second tr'th ta)!e+ 0 1 1 1 1 . 0 0 1 1 0 0 1 1 / /' 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 /N 1 1 1 1 0 0 / / /N' 1 1 0 0 1 1 / /

3+ As the EAED gate is an acti2e !o0 gate% meaning if either inp't is 0% the o'tp't 0i!! go high% some of the 2a!'es of the ta)!e can )e determined immediate!y Jthese are )o!dedK+ EAED1 can )e determined )y D and C Jita!icK+ Bhere the 2a!'es of EAED1 and C are #no0n% the 2a!'e of EAED2 can )e determined Jhigh!ighted in ye!!o0K+ Bhere EAED1 or EAED2 are #no0n to )e 0% the corresponding gates EAED3 and EAED9 m'st )e 1 Jsho0n in !ight )!'eK+

73

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense D 0 0 0 0 1 1 1 1 C / /' 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 . . 5 1 1 0 0 1 1 1 1 67/N C C C C C C 1 1 87/N' C C 1 1 C C C C

Eo0 treat EAED1 as the $ inp't and EAED2 as the & inp't to the EAED $& !atch JEAED3 and EAED9K and 'se the 0or# from the pre2io's pro)!em+ .o$s 1 ? @: $imi!ar to ro0 = from pro)!em 2+ .o$s 5 ? A' $imi!ar to ro0 6 from pro)!em 2+ ,he states for &o0s 1% 2% : and 5 do not change+ .o$ 6: $imi!ar to ro0 : from pro)!em 2+ .o$8: $imi!ar to ro0 5 from pro)!em 2+ &o0s 3 and 9 correspond to the reset state+ .o$ B: $imi!ar to ro0 3 from pro)!em 2+ .o$ C: $imi!ar to ro0 9 from pro)!em 2+ &o0s = and 6 correspond to the set state+ D 0 0 0 0 1 1 1 1 C / /' 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 0 0 5 1 1 0 0 1 1 1 1 67/N 0 1 0 0 0 1 1 1 87/N' 1 0 1 1 1 0 0 0

Eote than 0hen C is !o0% the state of the f!ip-f!op can ne2er change+ A!so% d'e to the addition of EAED1 and EAED2% there is ne2er a time 0hen the inp'ts reach a state that sho'!d not )e 'sed% as 0ith the $& !atches that m'st a2oid certain states+ $o 0hen C is !o0% the state remains constant and 0hen C is high% the state trac#s the D inp't+ ,he fina! 2a!'es are gi2en in the second tr'th ta)!e+ 9+ Bhen the c!ear !ine is !o0% the 2a!'e of V 0i!! )e !o0 regard!ess of the state of D+ Bhen the 2a!'e of C!ear is high% the 2a!'e of V 0i!! )e e('a! to the 2a!'e of D at the time of the rising c!oc# edge+

Style Guidelines

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&ppendix +' $olutions

D 0 0 1 1

CDEA. 0 1 0 1

/ 0 0 0 1

Cha%ter 8 re"iew exercises

1+ >eca'se s0itches s'ffer from )o'nce% the circ'it co'!d interpret the )o'nces as c!oc# p'!ses as 0e!!+ ,his 0o'!d mean that the circ'it might )e c!oc#ed more than once for a gi2en f!ip of the s0itch+

2+

3+

7:

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense 9+ ,0o f!ip-f!ops are needed to represent a!! fo'r possi)!e states+

/1'/0'
00

/1'/0
01

/1/0
11

/1/0'
10

/1'/0'
00

/1'/0
01

/1/0
11

/1/0'
10

x'
:+
0 1

0 1

1 0

0 1

1 0

x'
0

1 1

0 0

0 0

1 1

x
1

/1NJx%/1%/0K

/0NJx*/1%/0K N /0'

,he minima! e pression for V1 E is V1;V0; L ;V1;V0 L V1V0 L ;V1V0 0hich is not 2ery minima!+ For this reason% the design that fo!!o0s 'ses a m'!tip!e er to imp!ement the inp't for the second f!ip-f!op+ ,he first f!ip-f!op re('ires a 2a!'e that can )e ta#en direct!y off of the f!ip-f!op itse!f V0;+ &emem)er to )e caref'! 0hen 'sing the m' % and ins're that the $e!ect C !ine is the most significant )it for the !ogica! e pression+

5+

Style Guidelines

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A -!o)a! ,e t

&ppendix +' $olutions =+ ,he state machine has 3 states so it re('ires 2 f!ip-f!ops+ 21 T 3 TN 22

,he state 11 is not 'sed+ ,he ne t chapter 0i!! disc'ss the design of systems 0ith 'n'sed states+

Cha%ter ; re"iew exercises

1+ A state machine that has = states 0i!! re('ire 3 f!ip-f!ops+ maps 0i!! )e a 9 2 rectang!e+ )+ Bith one e terna! inp't% there 0i!! )e 9 tota! inp'ts% so the <-maps 0i!! )e 9 9 s('ares+ c+ Bith J< f!ip-f!ops% as )oth the J and < are inp'ts to the f!ip-f!op% there 0o'!d no0 )e 5 ne t state inp't 2a!'es to determine+ 2+ A state machine that has 19 states 0i!! re('ire 9 f!ip-f!ops+ maps 0i!! )e a 9 9 rectang!e+ )+ Bith one e terna! inp't% there 0i!! )e : tota! inp'ts+ ,he <-maps 0i!! )e 6 9 rectang!es% 0hich are often 'n0ie!dy+ In this case% a!ternate minimi1ation techni('es sho'!d )e e p!ored+ c+ Asing a J< f!ip-f!op 0ith 19 states that re('ires 9 f!ip-f!ops% there 0o'!d )e a tota! of 6 state inp'ts+ Gne J inp't and one < inp't for each of the f!ip-f!ops+ 23 T 19 TN 29 a+ Bith no e terna! inp'ts% on!y the e isting states pro2ide inp't to determine the ne t state% so the <22 T = TN 23 a+ Bith no e terna! inp'ts% on!y the e isting states pro2ide inp't to determine the ne t state% so the <-

3+

9+ A state machine tra2erses the states !isted in this order 000 001 011 111 110 100 000+ ,here is no e terna! inp't+

7=

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense

a+

)+ Gf the 6 possi)!e states% 101 and 100 are not represented+

c+

/1'/0'
00

/1'/0
01

/1 /0
11

/1/0'
10

/1'/0'
00

/1'/0
01

/1 /0
11

/1/0'
10

/5 ' d+
0

0 0

0 0

1 1

0 1

/5 '
0

0 0

1 0

1 1

0 0

/5
1

/5
1

/5NJ/5%/1%/0K N /1/0 + /5/1

/1NJ/5%/1%/0K N /1/0 + /5'/0

/1'/0'
00

/1'/0
01

/1/0
11

/1/0'
10

/5 '
0

1 0

1 0

1 0

0 0

/5
1

/0NJ/5*/1%/0K N /5'/1' + /5'/0 :+ ,he t0o )it se('ence 00 01 11 10 00 is a -ray code+ -ray codes on!y ha2e one )it change for each transition+

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&ppendix +' $olutions

a+

/1'/0' /1'/0 /1/0 /1/0'

00 01 11 10

/1'/0' /1'/0 /1/0 /1/0'

00 01 11 10

/5 ' )+
0

0 0

0 1

0 1

1 1

/5'
0

0 0

1 0

1 0

1 1

/5
1

/5
1

/5NJ/5%/1%/0K N /1/0' + /5/0 /1'/0' /1'/0 /1/0 /1/0'

00 01 11 10

/1NJ/5%/1%/0K N /1/0' + /5'/0

/5 '
0

1 0

1 0

0 1

0 1

/5
1

/0NJ/5*/1%/0K N /5'/1' + /5/1 5+ A t0o )it co'nter is to )e )'i!t that 0i!! co'nt for0ard% 00 01 10 11 00% 0hen a !ogica! inp't is set high and co'nts in re2erse order 0hen it is !o0+

a+

77

,his )oo# is !icensed 'nder a Creati2e Commons Attri)'tion 3+0 4icense /1'/0'
00

/1'/0
01

/1/0
11

/1/0'
10

/1'/0'
00

/1'/0
01

/1 /0
11

/1/0'
10

x' )+
0 1

1 0

0 1

1 0

0 1

x'
0 1

1 1

0 0

0 0

1 1

/1NJx*/1%/0K N x'/0'/1'+x/1'/0 +x'/1/0+x'/1/0'

/0NJx*/1%/0K N /0'

=+ A t0o )it co'nter is to )e )'i!t that 0i!! co'nt for0ard% 00 01 10 11 00% 0hen a !ogica! inp't is set high and as a -ray code 0hen it is !o0 J00 01 11 10 00K+

a+

/1'/0'
00

/1'/0
01

/1 /0
11

/1/0'
10

/1'/0'
00

/1'/0
01

/1/0
11

/1/0'
10

x'
)+
0

0 0

1 1

1 0

0 1

x'
0 1

1 1

1 0

0 0

0 1

x
1

/1N(x*/1*/0) = x'/0 + /1'/0 + x/1/0

/0NJx*/1%/0K N x'/1' + x/0'

Style Guidelines

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A -!o)a! ,e t