Process Statements in VHDL

Introduction:
This document is aimed at making you understand the usage of PROCESS statement in
VHDL. You i!! ha"e to read the e#$!anations of certain termino!ogies mentioned in the
initia! $art of this document% &efore you cou!d !ook at the e#am$!es. The e#am$!es and
the e#$!anation &e!o each one of them% i!! make you understand the usage of
PROCESS statements.
1. What is a PROCESS statement ?
PROCESS statements are co!!ections of actions e#ecuted in se'uence. These actions are
ca!!ed se'uentia! statements. The ty$es of actions inc!ude assigning "a!ues to signa!s%
conditiona! e#ecution% re$eated e#ecutions etc.
2. Ho does a PROCESS or!?
Let us o&ser"e and ana!y(e as to ho a series of assignment statements ithin a
PROCESS% get e#ecuted.
"rchitecture circuit#ar o$ circuit is
%e&in
Process
'e&in
() *+ ,1-.
(1 *+ ,)-.
Wait $or 1 ns.
End /rocess.
End circuit#ar.
The ay this $rocess orks is as fo!!os. )efore the simu!ation started% the signa! "a!ues
*+ and *, stay uninitia!i(ed. They ha"e a "a!ue of -./ 0one of the 1 ty$es of std2!ogic3
&efore the start of the simu!ation.
4s soon as the simu!ation starts% the $rocess gets acti"ated. 4!! the statements are
e#ecuted in the same order in hich they are $resent. The first to statements insidede
the PROCESS are assignment statements hi!e the !ast statement is a momentary5
sus$ension statement% ca!!ed 647T statement.
0O1E8 4 $rocess must either ha"e a sensiti"ity !ist or a 647T statement. Otherise% it
i!! not get simu!ated.
7n the a&o"e e#am$!e% the PROCESS gets e#ecuted once e"ery , nano5second. 7n other
ords% the assignment statement gets e#ecuted and then the $rocess gets sus$ended for ,
nano5second $eriod. The $rocess statement re$eats itse!f on and on and on ith one nano5
second time inter"a!. That is hy 7 used to ca!! a PROCESS statement as an infinite !oo$.
)ut in this e#am$!e% the $rocess statement can &e treated as a conditiona!5infinite !oo$.
This is &ecause% the PROCESS gets re$eated on!y once ithin , nano5second $eriod 0not
once in e"ery $ico5second% not once in e"ery femto5second% on!y once in e"ery nano5
second3.
This $rocess statement kee$s !oo$ing unti! you &reak the simu!ation using a SEVER7TY
947L.RE statement or any other &reak statement.
7n this s$ecific e#am$!e% *+ and *, get reassigned the "a!ues on and on and on. The
assignment takes $!ace at a fre'uency of once e"ery , nano5second.
Let us !ook at some e#am$!es of PROCESS statements ithout sensiti"ity statements.
E2am/3e 1:
Look at this sam$!e &e!o. The fo!!oing $iece of code has assignment statement and a
sus$end5fore"er 0647T3 statement.
"rchitecture circuit#ar o$ circuit is
%e&in
Process
'e&in
() *+ ,1-.
(1 *+ ,)-.
Wait. 4 4 ait $ore5er
End /rocess.
End circuit#ar.
This $rocess gets e#ecuted for the first time. *+ and *, get assigned to their res$ecti"e
"a!ues and then the Process gets sus$ended fore"er. The fina! "a!ue of *+ and *, i!! &e
-,/ and -+/ res$ecti"e!y. These "a!ues i!! not change ti!! the end5of5simu!ation.
E2am/3e 2:
Look at this sam$!e &e!o. The fo!!oing $iece of code has : assignment statements
inters$ersed &eteen 647T statements.
"rchitecture circuit#ar o$ circuit is
%e&in
Process
'e&in
() *+ ,1-.
Wait $or 6 ns.
() *+ ,)-.
Wait $or 6ns.
End /rocess.
End circuit#ar.
4s usua! *+ and *, i!! ha"e un5initia!i(ed "a!ues at the &eginning of simu!ation. 4s
soon as the $rocess gets acti"ated% the statements i!! get e#ecuted in an order. The tota!
time s$ent ithin the $rocess i!! &e ,+ nano5seconds. *+ i!! &eha"e !ike a $eriodic
signa!. *+ i!! &e of "a!ue -,/ for the first ; nano5seconds and then i!! &e of "a!ue -+/
for the ne#t ; nano5seconds. This cyc!e gets re$eated on and on.
E2am/3e 7:
Look at this sam$!e &e!o. The fo!!oing $iece of code has : assignment statements
ithout any ait statement in &eteen them. )ut there is a 647T statement at the end of
the assignment statement.
"rchitecture circuit#ar o$ circuit is
%e&in
Process
'e&in
() *+ ,1-.
() *+ ,)-.
Wait $or 6ns.
End /rocess.
End circuit#ar.
4s usua! *+ has an un5initia!i(ed "a!ue at the &eginning of simu!ation. 4s soon as the
$rocess gets acti"ated% the statements i!! get e#ecuted in an order. *+ is &eing assigned
a "a!ue of -,/% a!though it is immediate!y o"er5ritten &y assigning a "a!ue of -+/. So at
the end of simu!ation5cyc!e one% *+ i!! ha"e a "a!ue -+/. This $rocess re$eats itse!f ith
; nano5seconds inter"a!. Hoe"er% *+ i!! ne"er get assigned to a "a!ue of -,/. 7t is
a!ays -+/.
E2am/3e 8:
Look at this sam$!e &e!o. The fo!!oing $iece of code has : assignment statements ith
a 647T statement in &eteen them.
"rchitecture circuit#ar o$ circuit is
%e&in
Process
'e&in
() *+ ,1-.
Wait . 4 4 ait $ore5er
() *+ ,)-.
Wait $or 1 ns.
End /rocess.
End circuit#ar.
*+ i!! get assigned to a "a!ue of -,/ and remains -,/ fore"er. This is &ecause the
simu!ation does not get a chance to u$date the "a!ue of *+ <= -+/.
E2am/3e 6:
Look at this sam$!e &e!o. The fo!!oing $iece of code has : assignment statements
fo!!oed &y a ait statement. The $ecu!iarity in this e#am$!e code is that the out$ut
signa! of the first assignment gets assigned to the in$ut signa! of the second assignment.
4!so make note that there is a concurrent signa! assignment statement outside the $rocess.
The signa! int gets assigned to a -,/ right aay. 7n other ords% the concurrent statement
does not ha"e any de!ay in assignment. Right from + nano5seconds of simu!ation time% int
has a "a!ue of -,/. 7t retains this "a!ue throughout the simu!ation.
"rchitecture circuit#ar o$ circuit is
Si&na3 int : std#3o&ic .
%e&in
Int *+ ,1-.
Process
'e&in
() *+ ,1-.
(1 *+ ().
Wait $or 6 ns.
End /rocess.
End circuit#ar.
7n this e#am$!e% *+ gets assigned to a "a!ue -,/ during simu!ation cyc!e5one 0duration of
simu!ation5cyc!e5one &eing ; nano5seconds3. *, tries to get assigned to *+ in simu!ation
cyc!e5one% &ut gets a "a!ue of -./ in this cyc!e. This -./ is the "a!ue of *+ in the $re"ious
simu!ation cyc!e. 7n the ne#t simu!ation cyc!e 0sim5cyc!e :3% *+ again gets re5assigned to
-,/% hi!e *, gets the "a!ue5of5*+5in5$re"ious5sim cyc!e. 7n other ords% *, no get a
"a!ue of -,/.
2. What is a sensiti5it9 3ist ?
Sensiti"ity !ist is a !ist of signa!s to hich the $rocess is sensiti"e to. 4 $rocess gets
acti"e 0or e#ecuted3 on!y hen there is an e"ent on at!east one of the signa!s in the
sensiti"ity !ist.
4!! >asynchronous in$ut? signa!s and >c!ock? signa! gets inc!uded in the sensiti"ity !ist.
7. When can I use a PROCESS statement and hen shou3d I not use a PROCESS
statement ?
.se a PROCESS statement hen you can inc!ude a!! >asynchronous in$ut? signa!s and
>c!ock? signa! in the sensiti"ity !ist.
E#am$!e8
Process
)egin
4 <= &@
) <= c@
End $rocess@
You may use concurrent statements% rather than PROCESS statements &ecause you
cannot inc!ude the signa! -&/ in the sensiti"ity !ist. This is &ecause -&/ is Aust not an in$ut
a!one. 7t is a!so an out$ut.
Correct method8
4 <= &@
) <= c@
BOTE8 ait statements are ignored &y synthesis too! and hence cannot &e used during a
design de"e!o$ment. 647T statements are handy on!y for riting test5&enches.