Hardware

Description
Languages
CMOS VLSI Design
4th Ed.
Outline
HDL Overview
Why not use C?
Concurrency
Hardware datatypes / Signal resolution
Connectivity / Hierarchy
Hardware simulation
Basic VHDL Concepts
Basic VerilogHDL Concepts
SystemC Introduction
SystemVerilog Introduction
CMOS VLSI Design
4th Ed.
HDL Overview
! Hardware Description Languages
Used to model digital systems
Can model anything from a simple gate to a
complete system
Support design hierarchy
Support Hardware Design Methodology
! Can model real hardware (synthesizable)
! Can model behavior only (e.g. for test)
! Both are non-proprietary, IEEE standards
! Behavioral and structural coding styles
CMOS VLSI Design
4th Ed.
Basic Design Methodology
Simulate RTL Model
Gate-level
Model
Synthesize
Simulate Test Bench
ASIC or FPGA
Place & Route
Timing
Model
Simulate
Requirements
Device Libraries
CMOS VLSI Design
4th Ed.
Why Not Use C or C++?
HDLs need to support characteristics of real
hardware
Concurrency
Hardware datatypes / Signal resolution
Connectivity / Hierarchy
Circuit timing
HDLs must support hardware simulation
Time
Cycle-accurate or Event-driven (for simulation
speed)
Note: C++ has been extended for hardware
SystemC
CMOS VLSI Design
4th Ed.
Basic Comparison
Verilog
! Similar to C
! Popular in commercial,
on coasts of US
! Designs contained in
modules
VHDL
! Similar to Ada
! Popular in Military,
midwest US
! Designs contained in
entity architecture
pairs
CMOS VLSI Design
4th Ed.
Concurrency
! HDLs must support concurrency
Real hardware has many circuits running at the
same time!
! Two basics problems
Describing concurrent systems
Executing (simulating) concurrent systems
CMOS VLSI Design
4th Ed.
Describing Concurrency
! Many ways to create concurrent circuits
initial/always (Verilog) and process (VHDL)
blocks
Continuous/concurrent assignment statements
Component instantiation of other modules or
entity/architectures
! These blocks/statements execute in parallel in every
VHDL/Verilog design
CMOS VLSI Design
4th Ed.
Executing Concurrency
! Simulations are done on a host computer executing
instructions sequentially
! Solution is to use time-sharing
Each process or always or initial block gets the
simulation engine, in turn, one at a time
! Similar to time-sharing on a multi-tasking OS, with
one major difference
There is no limit on the amount of time a given
process gets the simulation engine
Runs until process requests to give it up (e.g.
wait)
CMOS VLSI Design
4th Ed.
Process Rules
! If the process has a sensitivity list, the process is
assumed to have an implicit wait statement as the
last statement
Execution will continue (later) at the first
statement
! A process with a sensitivity list must not contain an
explicit wait statement
CMOS VLSI Design
4th Ed.
Sensitivity List
With Explicit List
XYZ_Lbl: process (S1, S2)
begin
S1 <= 1;
S2 <= 0 after 10 ns;
end process XYZ_Lbl;
Without Explicit List
XYZ_Lbl: process
begin
S1 <= 1;
S2 <= 0 after 10 ns;
wait on S1, S2;
end process XYZ_Lbl;
CMOS VLSI Design
4th Ed.
Incomplete Sensitivity Lists
Logic simulators use
sensitivity lists to
know when to
execute a process
Perfectly happy not
to execute proc2
when c changes
Not simulating a 3-
input AND gate
though!
What does the
synthesizer create?
12
-- complete
proc1: process (a, b, c)
begin
x <= a and b and c;
end process;
-- incomplete
proc2: process (a, b)
begin
x <= a and b and c;
end process;
CMOS VLSI Design
4th Ed.
Datatypes
! Verilog has two groups of data types
Net Type physical connection between
structural elements
Value is determined from the value of its drivers,
such as a continuous assignment or a gate output
wire/tri, wor/trior, wand/triand, trireg/tri1/tri0, supply0,
supply1
Variable (Register) Type represents an
abstract data storage element
Assigned a value in an always or initial statement,
value is saved from one assignment to the next
reg, integer, time, real, realtime
CMOS VLSI Design
4th Ed.
Datatypes
VHDL categorizes objects in to four classes
Constant an object whose value cannot be
changed
Signal an object with a past history
Variable an object with a single current value
File an object used to represent a file in the host
environment
Each object belongs to a type
Scalar (discrete and real)
Composite (arrays and records)
Access
File
CMOS VLSI Design
4th Ed.
Hierarchy
! Non-trivial designs are developed in a hierarchical
form
Complex blocks are composed of simpler blocks
VHDL Verilog
Entity and architecture Module
Function Function
Procedure Task
Package and package body Module
CMOS VLSI Design
4th Ed.
! A concurrent language allows for:
Multiple concurrent elements
An event in one element to cause activity in
another
An event is an output or state change at a
given time
Based on interconnection of the elements
ports
Logical concurrency software
True physical concurrency e.g., <= in Verilog
Hardware Simulation
CMOS VLSI Design
4th Ed.
Discrete Time Simulation
Models evaluated and state updated only at
time intervals n!
Even if there is no change on an input
Even if there is no state to be changed
Need to execute at finest time granularity
Might think of this as cycle accurate things only
happen
@(posedge clock)
You could do logic circuits this way, but either:
Lots of gate detail lost as with cycle accurate
above (no gates!)
Lots of simulation where nothing happens every
gate is executed whether an input changes or not.
CMOS VLSI Design
4th Ed.
Discrete Event Simulation
Discrete Event Simulationalso known as
Event-driven Simulation
Only execute models when inputs change
Picks up simulation efficiency due to its selective
evaluation
Discrete Event Simulation
Events changes in state at discrete times. These
cause other events to occur
Only execute something when an event has occurred
at its input
Events are maintained in time order
Time advances in discrete steps when all events for a
given time have been processed
CMOS VLSI Design
4th Ed.
Discrete Event Simulation
! Quick example
Gate A changes its output.
Only then will B and C execute
! Observations
The elements in the diagram dont need to be logic
gates
DE simulation works because there is a sparseness
to gate execution maybe only 12% of gates
change at any one time.
The overhead of the event list then pays off
A
B
C
CMOS VLSI Design
4th Ed.
Synthesis
! Translates register-transfer-level (RTL) design into
gate-level netlist
! Restrictions on coding style for RTL model
! Tool dependent
CMOS VLSI Design
4th Ed.
Basic Verilog Concepts
! Interfaces
! Behavior
! Structure
CMOS VLSI Design
4th Ed.
A Gate Level Model
! A Verilog description of an SR latch
module nandLatch
(output q, qBar,
input set, reset);
nand #2
g1 (q, qBar, set),
g2 (qBar, q, reset);
endmodule
A module is dened
name of the module
The module has ports
that are typed
primitive gates with
names and
interconnections
type and delay of
primitive gates
CMOS VLSI Design
4th Ed.
A Behavioral Model - FSM
X
Q2
Q1
Q2#
D1
Q1
D2
Q2
Z
clock
reset
reset
reset
CMOS VLSI Design
4th Ed.
Organization for FSM
! Two always blocks
One for the combinational logic next state and
output logic
One for the state register
CMOS VLSI Design
4th Ed.
module FSM (x, z, clk, reset);
input clk, reset, x;
outputz;
reg [1:2] q, d;
reg z;
endmodule
Behavioral Specification
always @(x or q)
begin
d[1] = q[1] & x | q[2] & x;
d[2] = q[1] & x | ~q[2] & x;
z = q[1] & q[2];
end
always
@(posedge clk or negedge reset)
if (~reset)
q <= 0;
else q <= d;
The sequential part
(the D flip flop)
The combinational
logic part
next state
output
CMOS VLSI Design
4th Ed.
SystemC
! C++ class library developed to support system level
design (Electronic System Level, ESL)
! Intended to cope with both hardware and software
! IEEE 1666 Standard
! Supports concurrency, hierarchy, signals, time
! Supports transaction level modeling
! Supported natively by Modelsim
CMOS VLSI Design
4th Ed.
SystemVerilog
CMOS VLSI Design
4th Ed.
Verilog-95
CMOS VLSI Design
4th Ed.
VHDL Richer Than Verilog
CMOS VLSI Design
4th Ed.
C Cant Do Hardware
CMOS VLSI Design
4th Ed.
Verilog-2001
CMOS VLSI Design
4th Ed.
Verification and Modeling
CMOS VLSI Design
4th Ed.
SystemVerilog: Unified Language
CMOS VLSI Design
4th Ed.
Constrained Random
CMOS VLSI Design
4th Ed.
Basic Constraints
CMOS VLSI Design
4th Ed.
Weighted Random Case
CMOS VLSI Design
4th Ed.
Program Block
CMOS VLSI Design
4th Ed.
Why Use Assertions?
Limitations of Directed testing
To be practical, testing has to be high level
Locating a logic error can take a lot of time
New tests may need to be written to close in on
failure
Signal relationships are complex and lower level.
Assertions target interesting signal
relationships
Like handshake signals, bus protocols etc.
Execute in parallel with Verification tests
Efficiently capture Verification IP (bus protocols etc)
Often reusable across design and/or project
CMOS VLSI Design
4th Ed.
What Assertions Can Do
! Find logic errors earlier
Detect low-level errors that functional tests miss
Explicitly indicate time when a failure occurs
Explicit hierarchical locations and signal names
! Coverage of expected or unexpected events
Assertions coverage permits uses beyond
checking
How many times an event occurs
Proof that a negative event did NOT happen
CMOS VLSI Design
4th Ed.
Assertions
CMOS VLSI Design
4th Ed.
More Concise Than VHDL
CMOS VLSI Design
4th Ed.
Assertion Based Verification
Make Assertions part of Design and Verification flows
Embed design assumptions into the design
Place protocol & functional spec checks outside (bind)
Make use of Assertion Coverage data
Consider Assertions in Test Plan
Identify key protocols and target-able blocks
Input assumptions, Output expectations
Leverage Assertion Libraries first
OVL, QVL, Checkerware
Write custom Assertions (e.g SVA)
Expertise and training
CMOS VLSI Design
4th Ed.
Assertion Characteristics
Automated checks on signal behavior &
functionality
Boolean statement that specifies the logical
relationship between a set of signals over a
specified period of time
Checks performed at user-specified intervals
(sample points)
property p_one_hot;
@(posedge Clk) disable iff(Reset)
$onehot( {var1, var2, var3} );
endproperty
rx_fsm_one_hot : assert property( p_one_hot );
CMOS VLSI Design
4th Ed.
Embedded Assertions
These are assertions embedded in procedural
code
Ideal for designers almost like active
comments
Must have write access to the source-code to
add these
Likely to be of use ONLY to simulator tools
always @ (posedge clk)
if (cond1_is_met)
if (cond2_is_met)begin
access_grant = request1 || request2;
assert(access_grant);
CMOS VLSI Design
4th Ed.
Concurrent Assertions
These are assertions outside of procedural code
Ideal for Verification - No source-code access
required.
Totally independent of design (black-box
checking)
Used by simulation and other tools
property p_one_hot;
@(posedge Clk) disable iff(Reset)
$onehot( {var1, var2, var3} );
endproperty
rx_fsm_one_hot : assert property( p_one_hot );
CMOS VLSI Design
4th Ed.
Debugging Assertions
Assertions are compact code structures
Challenging to write, even moreso to debug
Need good tools to help visualize the assertion
Questa has powerful visualization and debug tools
Analysis pane
Lists all assertions at current hierarchical level and their
stats.
Waveform View of assertion and its signals
Clear indication of status: active/inactive/pass/fail
Thread View
decomposes assertions clause by clause for easy debug
CMOS VLSI Design
4th Ed.
Assertion Summary
Limited visibility to signals within SOCs
One contributor to the Verification gap
Assertion Based Verification is a solution
Questa supports Assertion Based Verification
Industry leading implementation of SV
OOP, Functional Coverage etc.
Broadest Assertion Library support
SV Assertions
Comprehensive debug toolchain
Assertion Pane
Waveform display of assertions
Assertion Thread Viewer