Copyright 2001, Agrawal & Bushnell Copyright 2001, Agrawal & Bushnell

VLSI Test i ng
DFT and Sc an
VLSI Test i ng
DFT and Sc an
Definitions
Ad-hoc methods
Full Scan design
Partial scan
Boundary scan
Summary
Copyright 2001, Agrawal & Bushnell DFT and Scan 2 Copyright 2001, Agrawal & Bushnell 2
Def i ni t i ons
Def i ni t i ons
Design for testability (DFT) refers to those design
techniques that make test generation and test
application cost-effective.
DFT methods for digital circuits:
Ad-hoc methods
Structured methods:
Scan
Partial Scan
Built-in self-test (BIST)
Boundary scan
DFT method for mixed-signal circuits:
Analog test bus
Copyright 2001, Agrawal & Bushnell DFT and Scan 3 Copyright 2001, Agrawal & Bushnell 3
Ad-Hoc DFT Met hods
Ad-Hoc DFT Met hods
Good design practices learnt through experience are used as
guidelines:
Avoid asynchronous (unclocked) feedback.
Make flip-flops initializable.
Avoid redundant gates. Avoid large fanin gates.
Provide test control for difficult-to-control signals.
Avoid gated clocks.
Consider ATE requirements (tristates, etc.)
Design reviews conducted by experts or design auditing tools.
Disadvantages of ad-hoc DFT methods:
Experts and tools not always available.
Test generation is often manual with no guarantee of high fault
coverage.
Design iterations may be necessary.
Copyright 2001, Agrawal & Bushnell DFT and Scan 4
Di f f i c ul t i es i n Seq. ATPG
Di f f i c ul t i es i n Seq. ATPG
Poor i ni t i al i zabi l i t y.
Poor c ont r ol l abi l i t y/obser vabi l i t y of st at e var i abl es.
Gat e c ount , number of f l i p-f l ops, and sequent i al dept h
do not ex pl ai n t he pr obl em.
Cyc l es ar e mai nl y r esponsi bl e f or c ompl ex i t y.
An ATPG ex per i ment :
Ci r c ui t Number of Number of Sequent i al ATPG Faul t
gat es f l i p-f l ops dept h CPU s c over age
TLC 355 21 14* 1,247 89.01%
Chi p A 1,112 39 14 269 98.80%
* Max i mum number of f l i p-f l ops on a PI t o PO pat h
Copyright 2001, Agrawal & Bushnell DFT and Scan 5 Copyright 2001, Agrawal & Bushnell 5
Sc an Desi gn
Sc an Desi gn
Circuit is designed using pre-specified design rules.
Test structure (hardware) is added to the verified
design:
Add a test control (TC) primary input.
Replace flip-flops by scan flip-flops (SFF) and connect to form
one or more shift registers in the test mode.
Make input/output of each scan shift register
controllable/observable from PI/PO.
Use combinational ATPG to obtain tests for all testable
faults in the combinational logic.
Add shift register tests and convert ATPG tests into
scan sequences for use in manufacturing test.
Copyright 2001, Agrawal & Bushnell DFT and Scan 6 Copyright 2001, Agrawal & Bushnell 6
Sc an Desi gn Rul es
Sc an Desi gn Rul es
Use only clocked D-type of flip-flops for all state
variables.
At least one PI pin must be available for test; more
pins, if available, can be used.
All clocks must be controlled from PIs.
Clocks must not feed data inputs of flip-flops.
Copyright 2001, Agrawal & Bushnell DFT and Scan 7 Copyright 2001, Agrawal & Bushnell 7
Cor r ec t i ng a Rul e Vi ol at i on
Cor r ec t i ng a Rul e Vi ol at i on
All clocks must be controlled from PIs.
Comb.
l ogi c
Comb.
l ogi c
D1
D2
CK
Q
FF
Comb.
l ogi c
D1
D2
CK
Q
FF
Comb.
l ogi c
Copyright 2001, Agrawal & Bushnell DFT and Scan 8 Copyright 2001, Agrawal & Bushnell 8
Sc an Fl i p-Fl op (SFF)
Sc an Fl i p-Fl op (SFF)
D
TC
SD
CK
Q
Q
MUX
D f l i p-f l op
Mast er l at c h Sl ave l at c h
CK
TC
Nor mal mode, D sel ec t ed Sc an mode, SD sel ec t ed
Mast er open
Sl ave open
t
t
Logi c
over head
Copyright 2001, Agrawal & Bushnell DFT and Scan 9 Copyright 2001, Agrawal & Bushnell 9
Level -Sensi t i ve Sc an-Desi gn
Fl i p-Fl op (LSSD-SFF)
Level -Sensi t i ve Sc an-Desi gn
Fl i p-Fl op (LSSD-SFF)
D
SD
MCK
Q
Q
D f l i p-f l op
Mast er l at c h Sl ave l at c h
t
SCK
TCK
SCK
MCK
TCK
N
o
r
m
a
l
m
o
d
e
MCK
TCK
S
c
a
n
m
o
d
e
Logi c
over head
Copyright 2001, Agrawal & Bushnell DFT and Scan 10 Copyright 2001, Agrawal & Bushnell 10
Addi ng Sc an St r uc t ur e
Addi ng Sc an St r uc t ur e
SFF
SFF
SFF
Combi nat i onal
l ogi c
PI PO
SCANOUT
SCANI N
TC or TCK
Not show n: CK or
MCK/SCK f eed al l
SFFs.
Copyright 2001, Agrawal & Bushnell DFT and Scan 11 Copyright 2001, Agrawal & Bushnell 11
Comb. Test Vec t or s
Comb. Test Vec t or s
I 2 I 1
O1 O2
S2
S1
N2 N1
Combi nat i onal
l ogi c
PI
Pr esent
st at e
PO
Nex t
st at e
SCANI N
TC
SCANOUT
Copyright 2001, Agrawal & Bushnell DFT and Scan 12 Copyright 2001, Agrawal & Bushnell 12
Comb. Test Vec t or s
Comb. Test Vec t or s
I 2 I 1
O1 O2
PI
PO
SCANI N
SCANOUT
S1 S2
N1 N2
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
TC
Dont c ar e
or r andom
bi t s
Sequenc e l engt h = (n
c omb
+ 1) n
sf f
+ n
c omb
c l oc k per i ods
n
c omb
= number of c ombi nat i onal vec t or s
n
sf f
= number of sc an f l i p-f l ops
Copyright 2001, Agrawal & Bushnell DFT and Scan 13 Copyright 2001, Agrawal & Bushnell 13
Test i ng Sc an Regi st er
Test i ng Sc an Regi st er
Scan register must be tested prior to application
of scan test sequences.
A shift sequence 00110011 . . . of length n
sff
+ 4 in
scan mode (TC = 0) produces 00, 01, 11 and 10
transitions in all flip-flops and observes the result
at SCANOUT output.
Total scan test length:
(n
comb
+ 2) n
sff
+ n
comb
+ 4 clock periods.
Example: 2,000 scan flip-flops, 500 comb. vectors,
total scan test length ~ 10
6
clocks.
Multiple scan registers reduce test length.
Copyright 2001, Agrawal & Bushnell DFT and Scan 14 Copyright 2001, Agrawal & Bushnell 14
Mul t i pl e Sc an Regi st er s
Mul t i pl e Sc an Regi st er s
Sc an f l i p-f l ops c an be di st r i but ed among
any number of shi f t r egi st er s, eac h havi ng
a separ at e sc ani n and sc anout pi n.
Test sequenc e l engt h i s det er mi ned by t he
l ongest sc an shi f t r egi st er .
J ust one t est c ont r ol (TC) pi n i s essent i al .
SFF
SFF
SFF
Combi nat i onal
l ogi c
PI /SCANI N
PO/
SCANOUT
M
U
X
CK
TC
Copyright 2001, Agrawal & Bushnell DFT and Scan 15 Copyright 2001, Agrawal & Bushnell 15
Sc an Over heads
Sc an Over heads
IO pins: One pin necessary.
Area overhead:
Gate overhead = [4 n
sff
/(n
g
+10n
ff
)] x 100%
where n
g
= comb. gates; n
ff
= flip-flops
Example n
g
= 100k gates, n
ff
= 2k flip-flops
overhead = 6.7%.
More accurate estimate must consider scan wiring
and layout area.
Performance overhead:
Multiplexer delay added in combinational path;
approx. two gate-delays.
Flip-flop output loading due to one additional
fanout; approx. 5 - 6%.
Copyright 2001, Agrawal & Bushnell DFT and Scan 16 Copyright 2001, Agrawal & Bushnell 16
Hi er ar c hi c al Sc an
Hi er ar c hi c al Sc an
Sc an f l i p-f l ops ar e c hai ned w i t hi n
subnet w or k s bef or e c hai ni ng subnet w or k s.
Advant ages:
Aut omat i c sc an i nser t i on i n net l i st
Ci r c ui t hi er ar c hy pr eser ved hel ps i n
debuggi ng and desi gn c hanges
Di sadvant age: Non-opt i mum c hi p l ayout .
SFF1
SFF2 SFF3
SFF4
SFF3 SFF1
SFF2 SFF4
Sc ani n Sc anout
Sc ani n
Sc anout
Hi er ar c hi c al net l i st
Fl at l ayout
Copyright 2001, Agrawal & Bushnell DFT and Scan 17 Copyright 2001, Agrawal & Bushnell 17
Opt i mum Sc an Layout
Opt i mum Sc an Layout
I O
pad
Fl i p-
f l op
c el l
I nt er c onnec t s
Rout i ng
c hannel s
SFF
c el l
TC
SCANI N
SCAN
OUT
Y
X
X
Y
Ac t i ve ar eas: XY and XY
Copyright 2001, Agrawal & Bushnell DFT and Scan 18 Copyright 2001, Agrawal & Bushnell 18
Sc an Ar ea Over head
Sc an Ar ea Over head
Li near di mensi ons of ac t i ve ar ea:
X = (C + S) / r
X = (C + S + S) / r
Y = Y + r y = Y + Y(1--) / T
Ar ea over head
XY--XY
= -------------- x 100%
XY
1--
= [ (1+s)(1+ -------) 1] x 100%
T
1--
= (s + ------- ) x 100%
T
y = t r ac k di mensi on, w i r e
w i dt h+separ at i on
C = t ot al c omb. c el l w i dt h
S = t ot al non-sc an FF c el l
w i dt h
s = f r ac t i onal FF c el l ar ea
= S/(C+S)
= SFF c el l w i dt h f r ac t i onal
i nc r ease
r = number of c el l r ow s
or r out i ng c hannel s
= r out i ng f r ac t i on i n ac t i ve
ar ea
T = c el l hei ght i n t r ac k
di mensi on y
Copyright 2001, Agrawal & Bushnell DFT and Scan 19 Copyright 2001, Agrawal & Bushnell 19
Ex ampl e: Sc an Layout
Ex ampl e: Sc an Layout
2,000-gat e CMOS c hi p
Fr ac t i onal ar ea under f l i p-f l op c el l s, s = 0.478
Sc an f l i p-f l op (SFF) c el l w i dt h i nc r ease, = 0.25
Rout i ng ar ea f r ac t i on, = 0.471
Cel l hei ght i n r out i ng t r ac k s, T = 10
Cal c ul at ed over head = 17.24%
Ac t ual measur ed dat a:
Sc an i mpl ement at i on Ar ea over head Nor mal i zed c l oc k r at e
______________________________________________________________________
None 0.0 1.00
Hi er ar c hi c al 16.93% 0.87
Opt i mum l ayout 11.90% 0.91
Copyright 2001, Agrawal & Bushnell DFT and Scan 20 Copyright 2001, Agrawal & Bushnell 20
ATPG Ex ampl e: S5378
ATPG Ex ampl e: S5378
Or i gi nal
2,781
179
0
0.0%
4,603
35/49
70.0%
70.9%
5,533 s
414
414
Ful l -sc an
2,781
0
179
15.66%
4,603
214/228
99.1%
100.0%
5 s
585
105,662
Number of c ombi nat i onal gat es
Number of non-sc an f l i p-f l ops (10 gat es eac h)
Number of sc an f l i p-f l ops (14 gat es eac h)
Gat e over head
Number of f aul t s
PI /PO f or ATPG
Faul t c over age
Faul t ef f i c i enc y
CPU t i me on SUN Ul t r a I I , 200MHz pr oc essor
Number of ATPG vec t or s
Sc an sequenc e l engt h
Copyright 2001, Agrawal & Bushnell DFT and Scan 21
Par t i al -Sc an Def i ni t i on
Par t i al -Sc an Def i ni t i on
A subset of f l i p-f l ops i s sc anned.
Obj ec t i ves:
Mi ni mi ze ar ea over head and sc an
sequenc e l engt h, yet ac hi eve r equi r ed
f aul t c over age
Ex c l ude sel ec t ed f l i p-f l ops f r om sc an:
I mpr ove per f or manc e
Al l ow l i mi t ed sc an desi gn r ul e vi ol at i ons
Al l ow aut omat i on:
I n sc an f l i p-f l op sel ec t i on
I n t est gener at i on
Shor t er sc an sequenc es
Copyright 2001, Agrawal & Bushnell DFT and Scan 22
Par t i al -Sc an Ar c hi t ec t ur e
Par t i al -Sc an Ar c hi t ec t ur e
FF
FF
SFF
SFF
Combi nat i onal
c i r c ui t
PI PO
CK1
CK2
SCANOUT
SCANI N
TC
Copyright 2001, Agrawal & Bushnell DFT and Scan 23
A Par t i al -Sc an Met hod
A Par t i al -Sc an Met hod
Sel ec t a mi ni mal set of f l i p-f l ops f or sc an
t o el i mi nat e al l c yc l es.
Al t er nat i vel y, t o k eep t he over head l ow
onl y l ong c yc l es may be el i mi nat ed.
I n some c i r c ui t s w i t h a l ar ge number of
sel f -l oops, al l c yc l es ot her t han sel f -l oops
may be el i mi nat ed.
Copyright 2001, Agrawal & Bushnell DFT and Scan 24
The MFVS Pr obl em
The MFVS Pr obl em
For a di r ec t ed gr aph f i nd a set of ver t i c es w i t h
smal l est c ar di nal i t y suc h t hat t he del et i on of t hi s
ver t ex -set mak es t he gr aph ac yc l i c .
The mi ni mum f eedbac k ver t ex set (MFVS) pr obl em
i s NP-c ompl et e; pr ac t i c al sol ut i ons use heur i st i c s.
A sec ondar y obj ec t i ve of mi ni mi zi ng t he dept h of
ac yc l i c gr aph i s usef ul .
1 2
3
4 5 6
L=3
1 2
3
4 5 6
L=2
L=1
s-gr aph
A 6-f l i p-f l op c i r c ui t
Copyright 2001, Agrawal & Bushnell DFT and Scan 25
Par t i al Sc an Ex ampl e
Par t i al Sc an Ex ampl e
Ci r c ui t : TLC
355 gat es
21 f l i p-f l ops
Sc an Max . c yc l e Dept h* ATPG Faul t si m. Faul t ATPG Test seq.
f l i p-f l ops l engt h CPU s CPU s c ov. vec t or s l engt h
0 4 14 1,247 61 89.01% 805 805
4 2 10 157 11 95.90% 247 1,249
9 1 5 32 4 99.20% 136 1,382
10 1 3 13 4 100.00% 112 1,256
21 0 0 2 2 100.00% 52 1,190
* Cyc l i c pat hs i gnor ed
Copyright 2001, Agrawal & Bushnell DFT and Scan 26
Test Lengt h St at i st i c s
Test Lengt h St at i st i c s
Ci r c ui t : TLC
200
100
0
0 50 100 150 200 250
N
u
m
b
e
r
o
f

f
a
u
l
t
s
200
100
0
0 5 10 15 20 25
N
u
m
b
e
r
o
f

f
a
u
l
t
s
200
100
0
0 5 10 15 20 25
N
u
m
b
e
r
o
f

f
a
u
l
t
s
Wi t hout sc an
9 sc an f l i p-f l ops
10 sc an f l i p-f l ops
Test
l engt h
Test
l engt h
Test
l engt h
Copyright 2001, Agrawal & Bushnell DFT and Scan 27
Par t i al vs. Ful l Sc an:
S5378
Par t i al vs. Ful l Sc an:
S5378
Or i gi nal
2,781
179
0
0.0%
4,603
35/49
70.0%
70.9%
5,533 s
414
414
Ful l -sc an
2,781
0
179
15.66%
4,603
214/228
99.1%
100.0%
5 s
585
105,662
Number of c ombi nat i onal gat es
Number of non-sc an f l i p-f l ops
(10 gat es eac h)
Number of sc an f l i p-f l ops
(14 gat es eac h)
Gat e over head
Number of f aul t s
PI /PO f or ATPG
Faul t c over age
Faul t ef f i c i enc y
CPU t i me on SUN Ul t r a I I
200MHz pr oc essor
Number of ATPG vec t or s
Sc an sequenc e l engt h
Par t i al -sc an
2,781
149
30
2.63%
4,603
65/79
93.7%
99.5%
727 s
1,117
34,691
Copyright 2001, Agrawal & Bushnell DFT and Scan 28
Random-Ac c ess Sc an (RAS)
Random-Ac c ess Sc an (RAS)
PO
PI
Combi nat i onal
l ogi c
RAM
n
f f
bi t s
SCANOUT
SCANI N
CK
TC
ADDRESS
ACK
Addr ess sc an
r egi st er
l og
2
n
f f
bi t s
Addr ess dec oder
SEL
Copyright 2001, Agrawal & Bushnell DFT and Scan 29
RAS Fl i p-Fl op (RAM Cel l )
RAS Fl i p-Fl op (RAM Cel l )
Sc an f l i p-f l op
(SFF)
Q
To c omb.
l ogi c
D
SD
Fr om c omb. l ogi c
SCANI N
TC
CK
SEL
SCANOUT
Copyright 2001, Agrawal & Bushnell DFT and Scan 30
RAS Appl i c at i ons
RAS Appl i c at i ons
Logi c t est :
Reduc ed t est l engt h
Reduc ed sc an pow er
Del ay t est : Easy t o gener at e si ngl e-i nput -c hange
(SI C) del ay t est s.
Advant age: RAS may be sui t abl e f or c er t ai n
ar c hi t ec t ur e, e.g., w her e memor y i s i mpl ement ed
as a RAM bl oc k .
Di sadvant ages:
Not sui t abl e f or r andom l ogi c ar c hi t ec t ur e
Hi gh over head gat es added t o SFF, addr ess
dec oder , addr ess r egi st er , ex t r a pi ns and r out i ng
Copyright 2001, Agrawal & Bushnell DFT and Scan 31 Copyright 2001, Agrawal & Bushnell 31
Boundar y Sc an (BS)
I EEE 1149.1 St andar d
Boundar y Sc an (BS)
I EEE 1149.1 St andar d
Developed for testing chips on a printed circuit
board (PCB).
A chip with BS can be accessed for test from the
edge connector of PCB.
BS hardware added to chip:
Test Access port (TAP) added
Four test pins
A test controller FSM
A scan flip-flop added to each I/O pin.
Standard is also known as JTAG (Joint Test
Action Group) standard.
Copyright 2001, Agrawal & Bushnell DFT and Scan 32 Copyright 2001, Agrawal & Bushnell 32
Boundar y Sc an Test Logi c
Boundar y Sc an Test Logi c
Copyright 2001, Agrawal & Bushnell DFT and Scan 33 Copyright 2001, Agrawal & Bushnell 33
Summar y
Summar y
Scan is the most popular DFT technique:
Rule-based design
Automated DFT hardware insertion
Combinational ATPG
Advantages:
Design automation
High fault coverage; helpful in diagnosis
Hierarchical scan-testable modules are easily combined
into large scan-testable systems
Moderate area (~10%) and speed (~5%) overheads
Disadvantages:
Large test data volume and long test time
Basically a slow speed (DC) test
Variations of scan:
Partial scan
Random access scan (RAS)
Boundary scan (BS)
Copyright 2001, Agrawal & Bushnell DFT and Scan 34 Copyright 2001, Agrawal & Bushnell 34
Pr obl ems t o Sol ve
Pr obl ems t o Sol ve
What is the main advantage of scan method?
Given that the critical path delay of a circuit is 800ps and
the scan multiplexer adds a delay of 200ps, determine the
performance penalty of scan as percentage reduction in the
clock frequency. Assume 20% margin for the clock period
and no delay due to the extra fanout of flip-flop outputs.
How will you reduce the test time of a scan circuit by a
factor of 10?
Copyright 2001, Agrawal & Bushnell DFT and Scan 35 Copyright 2001, Agrawal & Bushnell 35
Sol ut i ons
Sol ut i ons
What is the main advantage of scan method?
Only combinational ATPG (with lower complexity) is used.
Given that the critical path delay of a circuit is 800ps and the scan
multiplexer adds a delay of 200ps, determine the performance penalty
of scan as percentage reduction in the clock frequency. Assume 20%
margin for the clock period and no delay due to the extra fanout of flip-
flop outputs.
Clock period of pre-scan circuit = 800+160 = 960ps
Clock period for scan circuit = 800+200+200 = 1200ps
Clock frequency reduction = 100(1200-960)/1200 = 20%
How will you reduce the test time of a scan circuit by a factor of 10?
Form 10 scan registers, each having 1/10
th
the length of a single scan
register.