CPU/Sound Board Theory of Operation

C PU Section:
The C PU is a 68B 09E (U 209) w ith up to 8 M Bytes ofC PU C ode Space (U 210). The C PU code is bank selected
by the use ofU 211 and each bank consists of 16 KBytes. 8 KBytes ofR AM (U 212) is available to the C PU .The
R AM is battery backed and has a w rite protected area. Battery back up is accom plished by 3-AA C ells w hich
have a TEST PO IN T VB to check the battery voltage status. The w rite protected area consists of 512 Bytes used
for storing gam e settings. This section ofR A M can only be w ritten to w hen the coin door is open. The C oin D oor
sw itch com es into the C PU on C N 6-12 and is fed into the address decoding PA L U 213. W hen this m em ory
protect signalis low w rites to the protected R A M area are prohibited. Address decoding for the system is
accom plished by one PA L U 213 and one 1-of-8 decoder U 214.

A w atchdog is used to m onitor the C PU and the 5v supply. Ifthe 5v supply is below 4.75 the w atchdog w illhold
the C PU /Sound Board & I/O Board in reset. The w atchdog m ustbe fed ata rate of250m s orfaster. The signal
used to feed the w atchdog com es from the EPR O M Bank select signalused to load U 211. The C PU has a tim er
interrupt used as a heartbeat for the system this signalcom es from counter U 2.The clock forthis counteris the
C PU Q C LO C K . C learing the tim erinterruptis done by reading the D IP Sw itch. The tim erinterruptcan be
observed at TEST PO IN T FIR Q .In norm aloperation "FIR Q " should be toggling ata rate of976H z.
The I/O Interface C N 1 is buffered by tw o (2) H C 245 C hips. The C PU ’s resetline is buffered by Q 10 and fed over
to the I/O through C N 1. An I/O strobe signalis feed through C N 1-15 and is used to notify the I/O thata valid
address is being sent.

Sw itches:
The Sw itch M atrix consists of eight (8) 2N 3904 Transistors w hich pullone of8 strobes ‘low ’to activate a Single
C olum n of sw itches.The Sw itch R eturn Signals are fed into C N 7 [SW ITC H R O W S] and are highly filtered and
com pared to a 2.5v reference voltage. The Sw itch R eturn Voltage m ustbe below 2.5v to m ake a Valid Sw itch
C losure. Iffalse sw itches are appearing, check that none of the 2N 3904 Transistors are perm anently pulling the
strobe line low .O nly one strobe from C N 5 [SW ITC H C O LU M N S] should be low atany tim e. C N 6 [D ED IC ATED
SW ITC H IN ]is a D edicated Bank ofInputSw itches. Sw itches connected to C N 6 are connected to ground instead
ofa strobe and m ay be read atany tim e.
Plasm a Interface:
The data path for com m unication to and from the Plasm a C ontroller Board is 8 bits w ide.There are separate
Inputand O utputBusses. The InputBus from the Plasm a C ontroller to the C PU /Sound Board com es in on C N 8
[PLASM A C O N TR O L]-Pins 3-10 and is fed into U 200 for inputto the C PU ’s D ata Bus. D ata going outto the
controller com es from the C PU ’s D ata Bus through U 201 and onto C N 8-Pins 11-18. Status back from the Plasm a
C ontroller com es in on C N 8-Pins 22-26 and is fed into U 202 forinputto the C PU ’s D ata Bus. Tw o controlsignals
that go out to the Plasm a C ontroller are PR ES [PLASM A R ESET] and C N 8-Pin 19 [PSTB -Plasm a Strobe]. The
Plasm a R eset is softw are controllable through U 216/B and also has a testpoint"Plasm a R eset". The Plasm a
Strobe Signalto the controller is generated from U 216/A and is used to latch data into the Plasm a C ontroller.

Sound Section:
The audio section consists of a B SM T SO U N D C H IP U 9 Sound (Voice) EPR O M s (U 17 U 21 U 36 U 37)68B 09E
U 6 and Sound C ode EPR O M U 7. The B SM T latches sound EPR O M addresses in U 13 & U 12 for outputto the
Sound EPR O M s. Sound D ata from the EPR O M s is read through U 19 to the B SM T. The EPR O M s are bank
selected by U 22. W hen the B SM T has sound data to be played outto the speakers itloads 16 bits into a 16 bit
shiftregister m ade up ofU 24 & U 23. The data stream from the shiftregisteris serially shifted into a stereo 16 bit
D igitalto Analog C onverter(D A C ). W hen the system is operating properly the w s (w ord select)inputofthe D A C
w illbe toggling. The w s inputis used to latch the rightand leftchannelsound data into the D A C . Ifthe w s line is
not oscillating no analog signalw illcom e out of the D A C . The D A C outputs are a controlled current source.
These outputs are converted to a voltage by an operationalam plifier U 30 to form the analog signal. TEST
PO IN TS A O R and A O L are the outputs of the operationalam plifier. These outputs are then fed directly into three
pow er am plifiers (TD A 2030A ) or optionally into an analog volum e controlchip U 35 for a potentiom eter volum e
control. The analog section has its ow n +5v & -5v derived from VR 1 & VR 2. These separate supply voltages are
for the D A C U 26 O perationalAm plifier U 30 and analog volum e controlU 35. Section 5 | PCBs
Sound calls are m ade from the C PU ’s 68B 09E U 200 to the sound section by latching data into U 5. The
sound section’s C PU 68B O 9E (U 6) reads in this data and handles the interfacing to the B SM T.

O ther Test Points:

E & Q - The C PU signals for both 68B 09E processors.Should be at2M hz w ith Q leading E by 500 nsec.
24M hz - The oscillator used for the B SM T & derivation ofE & Q .
SN D -FIR Q - The sound sections C PU interupt.
6M hz - This clock is generated internally on the B SM T and is used for shifting the data sam ples into th D A C .

W 6 Jum per - This jum per m ustbe installed for gam es thatuse 8M B Sound EPR O M s (U 17 U 21 U 36 U 37). For
gam es w hich use 4M B Sound EPR O M s this jum per is not installed but w illoperate on boards w ith W 6 installed.

Section 5, Chapter 4: Printed Circuit Boards (PCBs)

 CPU/Sound Board Schematic (Sheet 1 of 3)
Section 5 | PCBs

Section 5, Chapter 4: Printed Circuit Boards (PCBs)

 CPU/Sound Board Schematic (Sheet 1 of 3)

Section 5 | PCBs

Section 5, Chapter 4: Printed Circuit Boards (PCBs)

 CPU/Sound Board Schematic (Sheet 2 of 3)
Section 5 | PCBs

Section 5, Chapter 4: Printed Circuit Boards (PCBs)

 CPU/Sound Board Schematic (Sheet 2 of 3)

Section 5 | PCBs

Section 5, Chapter 4: Printed Circuit Boards (PCBs)

 CPU/Sound Board Schematic (Sheet 3 of 3)
Section 5 | PCBs

Section 5, Chapter 4: Printed Circuit Boards (PCBs)

 CPU/Sound Board Schematic (Sheet 3 of 3)

Section 5 | PCBs

Section 5, Chapter 4: Printed Circuit Boards (PCBs)

 CPU/Sound Board Component Layout
TE S T
PO IN TS:
<< VBATT

<< PLA SM A
R ESET

<< FIR Q
<< SW 200
<< G RO UND 1
<< C PU R ESET

<< L201 LED +5v

<< L200 LED
<< +5v

<< 24 M hz

<< W 6 requires
a Jum perif
using 8M B
EPR O M s in
U 17,U 21,U 36
and/orU 37

<< 6 M hz

<< E

<< SO U N D FIR Q
<< Q
Section 5 | PCBs

<< SO UND
R ESET

<< A O R
<< A O L

Section 5, Chapter 4: Printed Circuit Boards (PCBs)

CPU/Sound Board Parts
ITEM Q TY PA R T N U M B ER R EF-D ESIG N A TO R D ESC R IPTIO N (N S = N otStuffed)
---- 1 520-5136-16 C PU /Sound B oard M ono (FC C FEB 98) C om plete PC B A ssem bly
1 1 124-5001-00 VR 2 LM 7805C T +5v R egulator
2 5 121-5051-00 R 12,R 13,R 19,R 21,R 22,R 24 100K Ω 1/4W R es.(R 19:N S)
3 2 121-5009-00 R 103,R 107,R 111 1K Ω 1/4W R es.(R 103:N S)
4 38 121-5011-00 R 1>R 4,R 113,R 200>R 207,R 224>R 228,R 244>R 251, 10K Ω 1/4W R es.
R 260>R 267,R 296>R 299,R 301>R 306,R 409,R 413 (R 200>R 207,R 409,R 413:N S)
5 5 121-5023-00 R 9,R 14,R 100,R 102,R 104,R 106,R 110 22K Ω 1/4W R es.(R 100,R 102:N S)
6 20 121-5009-00 R 15,R 8,R 234>R 241,R 278>R 286,R 412 1K Ω 1/4W R es.
7 4 121-5043-00 R 16,R 17,R 25,R 112 2.2K Ω 1/4W R es.
8 1 121-5018-00 R7 1.5K Ω 1/4W R es.
9 2 121-5046-00 R 101,R 105,R 109 470K Ω 1/4W R es.(R 101:N S)
10 9 121-5045-00 R 108,R 287>R 294 39K Ω R es.
11 1 121-5036-00 R 312 330 Ω 1/4W R es.
12 12 n/a R 300,R 308>R 311,R 313>R 316,W X,W Y 0Ω Jum perW ire (24ga.)
13 15 121-5033-00 R 208>R 215,R 229>R 233,R 414>R 422 220 Ω 1/4W R es.(R 208>R 215:N S)
14 11 121-5021-00 R 216>R 223,R 242,R 243,R 400 4.7K Ω 1/4W R es.
15 16 121-5047-00 R 401>R 408,R 423>R 430 560 Ω 1/4W R es.
16 2 121-5048-00 R 410,R 411 3.3K Ω 1/4W R es.
17 1 100-0049-00 U3 74LS163
18 1 (See Pg.DR. „ Table) U7 27512 EPR O M
19 1 045-5015-07 CN4 7PKK156 (PIN 5=KEY)
20 1 N otU sed R ESET D o N otStuff
21 5 (See Pg.DR. „ Table) U 17,U 21,U 36,U 37,U 210 27C 040 EPR O M
22 2 100-5008-00 U 23,U 24 74LS165
23 4 125-5017-00 C 76>C 79 10uF,25v,R adialLytic C ap.
24 4 125-5020-00 C 40,C 59,C 101,C 108,C 115 22uF,25v,R adialLytic C ap.(C 101:N S)
25 2 125-5017-00 C 100,C 10,7 C 114 10uF,35v,R adialLytic C ap.(C 100:N S)
26 2 125-5015-00 C 102,C 104,C 109,C 112 100uF,25v,R ad.Ltc.Cap.(C102,C104:NS)
27 1 125-5014-00 C 409 22uF,16v,R adialLytic C ap.
28 1 100-5016-00 U 35 TD A1899
29 1 125-5037-00 C 30 1000uF,16v,R adialLytic C ap.
30 1 100-0027-00 U 34 74LS04
31 1 100-0043-00 U 18 74ALS139
32 6 100-0064-00 U 5,U 12,U 13,U 15,U 16,U 211 74LS374
33 1 100-0249-00 U2 74H C 4020
34 1 100-0149-00 U 10 74LS240
35 6 n/a W 1>W 6 (Jum perrequired @ W 6 ifusing 8M B EPR O M s) 0Ω Jum perW ire (24ga.)
36 2 125-5019-00 C 31,C 81 470uF,25v,R adialLytic C ap.
37 2 125-5017-00 C 10,C 35 10uF,16v,R adialTant.C ap.
38 2 125-5012-00 C 116,C 119 220uF,25v,R adialLytic C ap.
39 1 045-5015-06 CN2 6PKK156 (PIN 5=KEY)
40 1 140-0011-00 X1 24M hz
41 1 105-0116-00 U9 BSM T2000
42a 1 965-0136-00 U 19 -YELLO W D O T PAL16L8 (Program m ed)-YELLO W D O T
42b 1 965-0137-00 U 20 -W H ITE D O T PAL16L8 (Program m ed)-W H ITE D O T
42c 1 965-6504-00 U 213-B LU E D O T PAL16L8 (Program m ed)-B LU E D O T
43 5 100-0037-00 U 1,U 8,U 25,U 27,U 215 74LS74
44 3 125-5043-00 C 29,C 37,C 51 0.001uF,(102),C ap.
45 79 125-5031-00 C 1>C 5,C 7>C 9,C 12>C 16,C 18>C 21,C 23>C 26,C 28, 0.1uF,(104),AxialC er.C ap.
C 32>C 34,C 36,C 38,C 39,C 41>C 47,C 49,C 52,C 102 (C 102,C 103,C 105,C 106:N S)
C 103,C 105,C 106,C 110,C 111,C 113,C 117,C 118,
C 120,C 122>C 125,C 255,C 272>C 292,C 400>C 407
46 1 125-5038-00 C 121 100pF,(101),C ap.
47 4 125-5039-00 C 48,C 50,C 75,C 80 0.0022uF,(222),C ap.
48 39 125-5028-00 C 200>C 220,C 229,C 230,C 247>C 254,C 256>C 271 470pF,(471),C er.C ap.(C 200>C 207:N S)
49 8 125-5029-00 C 221>C 228,C 408 0.01uF,(103),100v C ap.(C 408:N S)
50 1 045-5015-06 CN3 6PKK156
51 1 100-0375-00 U 30 LM 833
52 2 100-0022-00 U 22 U 11 74LS273
53 7 112-5003-00 D 1>D 3,D 100>D 105 1N 4004,D iode (D 100,D 101:N S)
54 2 112-5008-00 D 200,D 201 1N 5817,D iode
55 8 112-0054-00 D 202,D 400>D 407 1N 4148,D iode (D 202:N S)
56 1 124-5002-00 VR 1 LM 7905C T -5v R egulator
57 2 100-5016-20 U 100>U 102 TD A2030V (U 100:N S)
58 1 100-5018-00 U 26 TD A1543
59 1 n/a SW 200 B3F4000
60 1 165-5099-00 L200 LED T1-3/4 D IFFU SER LED
61 1 165-5099-00 L201 LED T1-3/4 D IFFU SER LED
62 2 100-5015-00 U 216,U 217 H C T74
63 1 100-0148-00 U 214 74LS138
64 1 105-0046-00 U 212 M S6264A
65 1 100-0189-01 U 6,U 209 68B09E
66 1 545-5685-00 BAT1 BATTER Y H O LD ER 3-AA C ELLS 4.5v
67 1 045-5015-01 CN1 20-Pin,0.1 H EAD ER
68 10 n/a 6M H Z AO R Q AO L 24M H Z TestPoints -N S
69 10 110-0069-00 Q 1>Q 10 2N 3904,Transistor
Section 5 | PCBs
70 1 045-5013-00 CN5 9PKK156 (PIN 2=KEY)
71 2 100-5012-00 U 201,U 203 74H C T273
72 6 100-0338-00 U 200,U 202,U 204>U 208 74H C 245 (U 200:N S)
73 1 100-5023-00 U 218 D S1232
74 1 045-5015-26 CN8 26-Pin,0.1 H EAD ER
75 1 045-5014-01 CN7 10PKK156 (PIN 4=KEY)
76 4 n/a VBATT +5v G N D 1,G N D 2 TestPointW ire (24ga.)Loops
77 1 045-5015-00 CN6 12PKK156 (PIN 5=KEY)
78 1 181-5002-00 SW 300 8-Pin,D ip Sw itch
79 2 100-0377-00 U 400,U 401 LM 339AN
80 1 105-0052-05 U4 6116 R AM
81 3 535-5000-10 U 100>U 102 AAVID 531102
82 3 077-5209-00 U 6,U 9,U 209 40-Pin,IC Socket
83 5 077-5217-00 U 17,U 21,U 36,U 37,U 210 32-Pin,IC Socket
84 3 077-5208-00 U 4,U 7,U 212 28-Pin,IC D ip Socket
85 1 n/a U 1 (@ Pins 5 & 6) 100pF,C ap.

Section 5, Chapter 4: Printed Circuit Boards (PCBs)