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Euler Path Diagram

Stick diagrams are constructed in two steps: 1) Create a logic graph identifying each transistor and connection 2) Find an Euler path that traverses each node once for the pull-up and pull-down networks 3) Layout the stick diagram by tracing horizontal lines for the NMOS and PMOS devices, vertical lines for inputs, surrounding the devices in boxes, tracing horizontal lines for VDD and VSS, and labeling connections based on the Euler path.

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362 views5 pages

Euler Path Diagram

Stick diagrams are constructed in two steps: 1) Create a logic graph identifying each transistor and connection 2) Find an Euler path that traverses each node once for the pull-up and pull-down networks 3) Layout the stick diagram by tracing horizontal lines for the NMOS and PMOS devices, vertical lines for inputs, surrounding the devices in boxes, tracing horizontal lines for VDD and VSS, and labeling connections based on the Euler path.

Uploaded by

Debalina Panda
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Stick diagrams are constructed in two steps.

1) The first step is to construct a logic graph of the schematic (Figure 1).
A) Identify each transistor by a unique name of its gate signal.
(A, B, C, D, E in the example of Figure 1).
B) Identify each connection to the transistor by a unique name (1,2,3,4 in the
example of Figure 1).


2) The second step is to construct one Euler path for both the Pull up and Pull
down network (Figure 2).
A) Euler paths are defined by a path the traverses each node in the path, such
that each edge is visited only once.
B) The path is defined by the order of each transistor name.
i) If the path traverses transistor A then B then C. Then the path name is {A, B,
C}
C) The Euler path of the Pull up network must be the same as the path of the
Pull down network.
D) Euler paths are not necessarily unique.
E) It may be necessary to redefine the function to find a Euler path.
i) F = E + (CD) + (AB) = (AB) +E + (CD)

Figure 2: Euler Path
3) Once the Euler path is found it is time to lay out the stick diagram (Figure
3).
A) Trace two green lines horizontally to represent the NMOS and PMOS
devices.
B) Trace the number of inputs (5 in this example) vertically across each green
strip. These represent the gate contacts to the devices that are made of Poly.
C) Surround the NMOS device in a yellow box to represent the surrounding
Pwell material.
D) Surround the PMOS device in a green box to represent the surrounding
Nwell material.
E) Trace a blue line horizontally, above and below the PMOS and NMOS lines
to represent the Metal 1 of VDD and VSS.
F) Label each Poly line with the Euler path label, in order from left to right.
G) Place the connection labels upon the NMOS and PMOS devices.
i) In the example of Figure 2 the connection labels are 1, 2, 3, 4. Connection 1 is
the node that lies between the PMOS transistors A, B and E. The Euler path
defines the transistor ordering of {A, B, E, D, C} therefore, transistor B is
physically located beside transistor E.
Place the connection label 1 between the transistors B and E. Later, we will
route a Metal 1 connection from the drain of transistor A to the connection label
of 1.
ii) Connection 2 is the node that connects the PMOS transistors of E, D, and C.
Since the Euler path places transistors E and D next to each other, place the
connection label between these two. Later, we will route a Metal 1 strip from
the source of C to connection label 2.
iii) Connection label 3 lies between the NMOS transistors of A and B.
iiii) Connection label 4 lies between the NMOS transistors of D and C.







Stick Diagram Examples

NO

NOR




4 NAND implementation 16 transistors
xor (a, b) = nor (a.b, c), where c = nor (a, b)

Using transmission gate

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