VCC

CANH
7
6
CANL
RXD
1
TXD
S
8
DOMINANT
TIME OUT
OVER
TEMPERATURE
LOGIC
OUTPUT
MODE SELECT
4
NC / VRXD / FAULT (See Note A) VCC
5 3
GND
2
UNDER
VOLTAGE
DOMINANT
TIME OUT
(See Note B)
VCC
VCC or VRXD (See Note B)
FAULT LOGIC
MUX (See Note A)
S N 6 5 H V D 2 5 5
S N 6 5 H V D 2 5 6 , S N 6 5 H V D 2 5 7
www.ti.com SLLSEA2C DECEMBER 2011 REVISED SEPTEMBER 2013
' T u r b o' C A N T r a n s ce iv e r s f or H ig h e r D a ta R a te s a n d L a r g e N e twor k s I n cl u d in g F e a tu r e s
f or F u n ction a l S a f e ty
C h e ck f or S a mpl e s : S N 6 5 H V D 2 5 5 , S N 6 5 H V D 2 5 6 , S N 6 5 H V D 2 5 7
1F EA T UR ES D ES C R I PT I ON
This CAN transceiver meets the ISO1189-2 High
Me e ts th e R e qu ir e me n ts of I S O11898-2
Speed CAN (Controller Area Network) Physical Layer
' T u r b o' C A N :
standard. It is designed for data rates in excess of 1
S h or t a n d S y mme tr ica l Pr opa g a tion D e l a y
Mbps for CAN in short networks, and enhanced
T ime s a n d F a s t L oop T ime s f or En h a n ce d timing margin and higher data rates in long and
highly-loaded networks. The device provides many T imin g Ma r g in
protection features to enhance device and CAN-
H ig h e r D a ta R a te s in C A N N e twor k s
network robustness. The SN65HVD257 adds
I /O V ol ta g e R a n g e S u ppor ts 3.3V a n d 5 V MC Us
additional features, allowing easy design of redundant
I d e a l Pa s s iv e Be h a v ior Wh e n Un powe r e d and multi-topology networks with fault indication for
higher levels of functional safety in the CAN system.
Bu s a n d L og ic Pin s a r e H ig h I mpe d a n ce
(n o l oa d )
Powe r Up/D own With Gl itch F r e e Ope r a tion
On Bu s
Pr ote ction F e a tu r e s
H BM ES D Pr ote ction Exce e d s 12 k V
Bu s F a u l t Pr ote ction 2 7 V to 40V
Un d e r v ol ta g e Pr ote ction on S u ppl y Pin s
D r iv e r D omin a n t T ime Ou t (T XD D T O)
S N 6 5 H V D 2 5 7 : R e ce iv e r D omin a n t T ime Ou t
(R XD D T O)
S N 6 5 H V D 2 5 7 : F A UL T Ou tpu t Pin
T h e r ma l S h u td own Pr ote ction
C h a r a cte r ize d f or 40C to 12 5 C Ope r a tion
A PPL I C A T I ON S
A. Pin 5 function is device dependent; NC on
1Mb ps Ope r a tion in H ig h l y L oa d e d C A N
SN65HVD255, V
RXD
for RXD output level-
N e twor k s D own to 10k b ps N e twor k s Us in g shifting device on SN65HVD256, and
FAULT Output on SN65HVD257
T XD D T O
B. RXD logic output is driven to 5V V
CC
on
I n d u s tr ia l A u toma tion , C on tr ol , S e n s or s a n d
5V-only supply devices (SN65HVD255,
D r iv e S y s te ms
SN65HVD257) and driven to V
RXD
on
Bu il d in g , S e cu r ity a n d C l ima te C on tr ol output level-shifting device (SN65HVD256).
A u toma tion
C. RXD (Receiver) Dominant State Time Out
is a device dependent option available only
T e l e com Ba s e S ta tion S ta tu s a n d C on tr ol
on SN65HVD257.
S N 6 5 H V D 2 5 7 : F u n ction a l S a f e ty With
F ig u r e 1. F u n ction a l Bl ock D ia g r a m
R e d u n d a n t a n d Mu l ti-topol og y C A N n e twor k s
C A N Bu s S ta n d a r d s S u ch a s C A N ope n ,
D e v ice N e t, N MEA 2 000, A R N I C 82 5 , I S O117 83,
C A N a e r os pa ce
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 20112013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
S
CANL
FAULT
SN65HVD257
5V Supply and Fault
Output
TXD
RXD
GND
VCC
CANH
1
2
3
4
8
7
6
5
SN65HVD256
S
CANH
CANL
5V Supply with RXD
Level-Shifting
TXD
RXD
GND
VCC
VRXD
1
2
3
4
8
7
6
5
SN65HVD255
5V Supply
TXD
RXD
GND
VCC
S
CANH
CANL
NC
1
2
3
4
8
7
6
5
S N 6 5 H V D 2 5 5
S N 6 5 H V D 2 5 6 , S N 6 5 H V D 2 5 7
SLLSEA2C DECEMBER 2011 REVISED SEPTEMBER 2013 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
F ig u r e 2 . D PA C KA GE (T OP V I EW)
D EV I C E OPT I ON S
I /O
T XD R XD F A UL T
S UPPL Y PA R T N UMBER C OMMEN T
D T O D T O Ou tpu t
f or R XD
'251 and '1050 functional upgrade with 'Turbo CAN' fast loop times and
SN65HVD255 No Yes No No
TXD DTO protection allowing data rates down to 10kbps
'251 and '1050 functional upgrade with 'Turbo CAN' fast loop times and
SN65HVD256 Yes Yes No No TXD DTO protection allowing data rates down to 10kbps. RXD output
level shifting via RXD supply input.
'251 and '1050 functional upgrade with 'Turbo CAN' fast loop times,
SN65HVD257 No Yes Yes Yes TXD &RXD DTO protection allowing data rates down to 10kbps and
fault output pin
PI N F UN C T I ON S
PI N
T YPE D ES C R I PT I ON
N A ME N O.
TXD 1 I CAN transmit data input (LOW for dominant and HIGH for recessive bus states)
GND 2 GND Ground connection
V
CC
3 Supply Transceiver 5V supply voltage
RXD 4 O CAN receive data output (LOW for dominant and HIGH for recessive bus states)
NC 5 NC SN65HVD255: No Connect
V
RXD
Supply SN65HVD256: RXD output supply voltage
FAULT O SN65HVD257: open drain FAULT output pin
CANL 6 I/O Lowlevel CAN bus line
CANH 7 I/O High level CAN bus line
S 8 I Mode select: S (silent mode) select pin (active high)
OR D ER I N G I N F OR MA T I ON
(1)
T
A
PA C KA GE
(2 )
OR D ER A BL E PA R T N UMBER T OP S I D E MA R KI N G
SN65HVD255D and SN65HVD255DR HVD255
40C to 125C SOIC D SN65HVD256D and SN65HVD256DR HVD256
SN65HVD257D and SN65HVD257DR HVD257
(1) For the most current package and ordering information, see the Package Option Addendumat the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
2 Submit Documentation Feedback Copyright 20112013, Texas Instruments Incorporated
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
RXD
CANH
CANL
V /2
CC
Recessive
Logic H
Dominant
Logic L
Recessive
Logic H
Time, t
T
y
p
i
c
a
l
B
u
s
V
o
l
t
a
g
e
(
V
)
Normal & Silent Mode
CANL
CANH
V
diff(D)
V
diff(R)
4
3
2
1
S N 6 5 H V D 2 5 5
S N 6 5 H V D 2 5 6 , S N 6 5 H V D 2 5 7
www.ti.com SLLSEA2C DECEMBER 2011 REVISED SEPTEMBER 2013
F UN C T I ON A L D ES C R I PT I ON
OPER A T I N G MOD ES
The device has two main operating modes: normal mode and silent mode. Operating mode selection is made via
the S input pin.
T a b l e 1. Ope r a tin g Mod e s
S Pin MOD E D R I V ER R EC EI V ER R XD Pin
LOW Normal Mode Enabled (ON) Enabled (ON) Mirrors Bus State
(1)
HIGH Silent Mode Disabled (OFF) Enabled (ON) Mirrors Bus State
(1) Mirrors bus state: lowif CAN bus is dominant, high if CAN bus is recessive.
C A N BUS S T A T ES
The CAN bus has two states during powered operation of the device; dominant and recessive. A dominant bus
state is when the bus is driven differentially, corresponding to a logic lowon the TXD and RXD pin. A recessive
bus state is when the bus is biased to V
CC
/ 2 via the high-resistance internal input resistors R
IN
of the receiver,
corresponding to a logic high on the TXD and RXD pins. See Figure 3 and Figure 4.
F ig u r e 3. Bu s S ta te s (Ph y s ica l Bit R e pr e s e n ta tion )
F ig u r e 4. S impl if ie d R e ce s s iv e C ommon Mod e Bia s a n d R e ce iv e r
N OR MA L MOD E
Select the normal mode of device operation by setting S low. The CAN driver and receiver are fully operational
and CAN communication is bi-directional. The driver is translating a digital input on TXD to a differential output
on CANH and CANL. The receiver is translating the differential signal fromCANH and CANL to a digital output
on RXD.
Copyright 20112013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
S N 6 5 H V D 2 5 5
S N 6 5 H V D 2 5 6 , S N 6 5 H V D 2 5 7
SLLSEA2C DECEMBER 2011 REVISED SEPTEMBER 2013 www.ti.com
S I L EN T MOD E
Activate silent mode (receive only) by setting S high. The CAN driver is turned off while the receiver remains
active and RXD outputs the received bus state.
A PPL I C A T I ON N OT E: Silent mode may be used to implement babbling idiot protection, to ensure that the
driver does not disrupt the network during a local fault. Silent mode may also be used in redundant systems
to select or de-select the redundant transceiver (driver) when needed.
D R I V ER A N D R EC EI V ER F UN C T I ON T A BL ES
T a b l e 2 . D r iv e r F u n ction T a b l e
I N PUT S OUT PUT S
D R I V EN BUS
D EV I C E
S T A T E
S
(1) (2 )
T XD
(1) (3)
C A N H
(1)
C A N L
(1)
L H L Dominant
L or Open
All Devices H or Open Z Z Recessive
H X Z Z Recessive
(1) H =high level, L =lowlevel, X=irrelevant, Z =common mode (recessive) bias to V
CC
/ 2. See
Figure 3 and Figure 4 for bus state and common mode bias information.
(2) Devices have an internal pull down to GND on S pin. If S pin is open the pin will be pulled lowand the
device will be in normal mode.
(3) Devices have an internal pull up to V
CC
on TXD pin. If the TXD pin is open the pin will be pulled high
and the transmitter will remain in recessive (non-driven) state.
T a b l e 3. R e ce iv e r F u n ction T a b l e
C A N D I F F ER EN T I A L I N PUT S
D EV I C E MOD E BUS S T A T E R XD PI N
(1)
V
I D
= V
C A N H
V
C A N L
V
ID
0.9 V Dominant L
(2)
0.5 V <V
ID
<0.9 V ? ?
Normal or Silent
V
ID
0.5 V Recessive H
Open (V
ID
0 V) Open H
(1) H =high level, L =lowlevel, ? =indeterminate.
(2) RXD output remains dominant (low) as long as the bus is dominant. On SN65HVD257 device with
RXD dominant timeout, once the bus has been dominant longer than the dominant timeout, t
RXD_DTO
,
the RXD pin will return recessive (high). See RXD Dominant Timeout (SN65HVD257) for a description
of behavior during receiving a bus stuck dominant condition.
D I GI T A L I N PUT S A N D OUT PUT S
5 V V
C C
On l y D e v ice s (S N 6 5 H V D 2 5 5 a n d S N 6 5 H V D 2 5 7 ):
The 5V V
CC
device is supplied by a single 5 V rail. The digital inputs are 5 V and 3.3 V compatible. This device
has a 5 V (V
CC
) level RXD output. TXD is internally pulled up to V
CC
and S is internally pulled down to GND.
A PPL I C A T I ON N OT E: TXD is internally pulled up to V
CC
and the S pin is internally pulled down to GND.
However, the internal bias may only put the device into a known state if the pins float. The internal bias may
be inadequate for system-level biasing. TXD pullup strength and CAN bit timing require special consideration
when the SN65HVD25x devices are used with an open-drain TXD output on the CAN controller. An
adequate external pullup resistor must be used to ensure that the CAN controller output of the P maintains
adequate bit timing input to the SN65HVD25x.
5 V V
C C
with V
R XD
R XD ou tpu t S u ppl y D e v ice s (S N 6 5 H V D 2 5 6 ):
This device is a 5V V
CC
CAN transceiver with a separate supply for the RXD output, V
RXD
. The digital inputs are
5 V and 3.3 V compatible. These devices have a V
RXD
-level RXD output. TXD remains weakly pulled up to V
CC
.
A PPL I C A T I ON N OT E: On device versions with a V
RXD
supply that shifts the RXD output level, the input pins
of the device remain the same. TXD remains weakly pulled up to V
CC
internally. Thus, a small I
IH
current
flows if the TXD input is used belowV
CC
levels.
4 Submit Documentation Feedback Copyright 20112013, Texas Instruments Incorporated
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
S N 6 5 H V D 2 5 5
S N 6 5 H V D 2 5 6 , S N 6 5 H V D 2 5 7
www.ti.com SLLSEA2C DECEMBER 2011 REVISED SEPTEMBER 2013
5 V V
C C
with F A UL T Ope n -D r a in Ou tpu t D e v ice (S N 6 5 H V D 2 5 7 ):
This device has a FAULT output pin (open-drain). FAULT must be pulled up to V
CC
or I/O supply level via an
external resistor.
A PPL I C A T I ON N OT E: Because the FAULT output pin is open-drain, it actively pulls down when there is no
fault, and becomes high-impedance when a fault condition is detected. An external pullup resistor to the V
CC
or I/O supply of the systemmust be used to pull the pin high to indicate a fault to the host microprocessor.
The open-drain architecture makes the fault pin compatible with 3.3 V and 5 V I/O-level systems. The pullup
current, selected by the pullup resistance value, should be as low as possible while achieving the desired
voltage level output in the systemwith margin against noise.
PR OT EC T I ON F EA T UR ES
T XD D omin a n t T ime ou t (D T O)
During normal mode (the only mode where the CAN driver is active), the TXD DTO circuit prevents the
transceiver from blocking network communication in the event of a hardware or software failure where TXD is
held dominant longer than the timeout period t
TXD_DTO
. The DTO circuit timer starts on a falling edge on TXD.
The DTO circuit disables the CAN bus driver if no rising edge is seen before the timeout period expires. This
frees the bus for communication between other nodes on the network. The CAN driver is re-activated when a
recessive signal is seen on TXD pin, thus clearing the TXD DTO condition. The receiver and RXD pin still reflect
the CAN bus, and the bus pins are biased to recessive level during a TXD dominant timeout.
A PPL I C A T I ON N OT E: The minimumdominant TXD time allowed by the TXD DTO circuit limits the minimum
possible transmitted data rate of the device. The CAN protocol allows a maximum of eleven successive
dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by
an error frame. This, along with the t
TXD_DTO
minimum, limits the minimumdata rate. Calculate the minimum
transmitted data rate by: MinimumData Rate =11 / t
TXD_DTO
.
R XD D omin a n t T ime ou t (S N 6 5 H V D 2 5 7 )
The SN65HVD257 device has a RXD dominant timeout (RXD DTO) circuit that prevents a bus stuck dominant
fault from permanently driving the RXD output dominant (low) when the bus is held dominant longer than the
timeout period t
RXD_DTO
. The RXD DTO timer starts on a falling edge on RXD (bus going dominant). If no rising
edge (bus returning recessive) is seen before the timeout constant of the circuit expires (t
RXD_DTO
), the RXD pin
returns high (recessive). The RXD output is re-activated to mirror the bus receiver output when a recessive signal
is seen on the bus, clearing the RXD dominant timeout. The CAN bus pins are biased to the recessive level
during a RXD DTO.
A PPL I C A T I ON N OT E: The minimum dominant RXD time allowed by the RXD DTO limits the minimum
possible received data rate of the device. The CAN protocol allows a maximum of eleven successive
dominant bits for the worst case transmission, where five successive dominant bits are followed immediately
by an error frame. This, along with the t
RXD_DTO
minimum, limits the minimum data rate. The minimum
received data rate may be calculated by: MinimumData Rate =11 / t
RXD_DTO
.
T h e r ma l S h u td own
If the junction temperature of the device exceeds the thermal shut down threshold the device turns off the CAN
driver circuits thus blocking the TXD to bus transmission path. The shutdown condition is cleared when the
junction temperature drops belowthe thermal shutdown temperature of the device.
A PPL I C A T I ON N OT E: During thermal shutdown the CAN bus drivers turn off; thus no transmission is
possible fromTXD to the bus. The CAN bus pins are biased to recessive level during a thermal shutdown,
and the receiver to RXD path remains operational.
Copyright 20112013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
TXD
DTO
RXD
DTO
Thermal
Shutdown
FAULT
GND
UV
Lockout
V
CC
or V
IO
P
FAULT
Input
S N 6 5 H V D 2 5 5
S N 6 5 H V D 2 5 6 , S N 6 5 H V D 2 5 7
SLLSEA2C DECEMBER 2011 REVISED SEPTEMBER 2013 www.ti.com
Un d e r v ol ta g e L ock ou t
The supply pins have undervoltage detection that places the device in protected mode. This protects the bus
during an undervoltage event on either the V
CC
or V
RXD
supply pins.
T a b l e 4. Un d e r v ol ta g e L ock ou t 5 V On l y D e v ice s (S N 6 5 H V D 2 5 5 a n d S N 6 5 H V D 2 5 7 )
V
C C
D EV I C E S T A T E BUS OUT PUT R XD
GOOD Normal Per Device State and TXD Mirrors Bus
BAD Protected High Impedance High Impedance (3-state)
T a b l e 5 . Un d e r v ol ta g e L ock ou t 5 V a n d V
R XD
D e v ice (S N 6 5 H V D 2 5 6 )
V
C C
V
R XD
D EV I C E S T A T E BUS OUT PUT R XD
GOOD GOOD Normal Per Device State and TXD Mirrors Bus
BAD GOOD Protected High Impedance High (Recessive)
GOOD BAD Protected Recessive High Impedance (3-state)
BAD BAD Protected High Impedance High Impedance (3-state)
A PPL I C A T I ON N OT E: After an undervoltage condition is cleared and the supplies have returned to valid
levels, the device typically resumes normal operation in 300 s.
F A UL T Pin (S N 6 5 H V D 2 5 7 )
If one or more of the faults (TXD-Dominant Timeout, RXD dominant Timeout, Thermal Shutdown or
Undervoltage Lockout) occurs, the FAULT pin (open-drain) turns off, resulting in a high level when externally
pulled up to V
CC
or IO supply.
F ig u r e 5 . F A UL T Pin F u n ction D ia g r a m a n d A ppl ica tion
6 Submit Documentation Feedback Copyright 20112013, Texas Instruments Incorporated
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
Normal CAN
communication
CAN
Bus
Signal
Bus Fault stuck dominant , example CANH
short to supply =5V and CAN L short to GND .
RXD output is returned recessive (high)
and FAULT is signaled to P and link
layer / protocol.
RXD
(reciever)
RXD
(receiver)
t
RXD_DTO
FAULT
C
A
N
P
H
Y
W
i
t
h
R
X
D
D
T
O
A
N
D
F
A
U
L
T
S
N
6
5
H
V
D
2
5
7
C
A
N
P
H
Y
S
N
6
5
H
V
D
2
5
5
S
N
6
5
H
V
D
2
5
6
Fault is repaired and normal
communication returns
FAULT cleared signal
is given
RXD mirrors
bus
RXD will also be stuck dominant blocking
alternative communication paths
C
A
N
B
U
S
Normal CAN
communication
CAN
Bus
Signal
TXD fault stuck dominant, example PCB
failure or bad software
Fault is repaired & transmission
capability restored
TXD
(driver)
Bus would be "stuck dominant blocking communication for the
whole network but TXD DTO prevents this and frees the bus for
communication after the time t
TXD_DTO
.
t
TXD_DTO
Communication from
local node
Communication from
repaired node
RXD
(receiver)
Communication from
other bus node(s)
Communication from
repaired local node
FAULT
(HVD257)
Fault indication is removed. FAULT is signaled to link layer / protocol.
Communication from
other bus node(s)
t
TXD_DTO
Driver disabled freeing bus for other nodes
S N 6 5 H V D 2 5 5
S N 6 5 H V D 2 5 6 , S N 6 5 H V D 2 5 7
www.ti.com SLLSEA2C DECEMBER 2011 REVISED SEPTEMBER 2013
F ig u r e 6 . Exa mpl e T imin g D ia g r a m f or T XD D T O a n d F A UL T Pin
F ig u r e 7 . Exa mpl e T imin g D ia g r a m f or D e v ice s With a n d With ou t R XD D T O a n d F A UL T Pin
Copyright 20112013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
S N 6 5 H V D 2 5 5
S N 6 5 H V D 2 5 6 , S N 6 5 H V D 2 5 7
SLLSEA2C DECEMBER 2011 REVISED SEPTEMBER 2013 www.ti.com
Un powe r e d D e v ice
The device is designed to be an 'ideal passive' or 'no load' to the CAN bus if it is unpowered. The bus pins
(CANH, CANL) have extremely low leakage currents when the device is unpowered so they will not load down
the bus. This is critical if some nodes of the network will be unpowered while the rest of the of network remains in
operation. The logic pins also have extremely low leakage currents when the device is unpowered to avoid
loading down other circuits that may remain powered.
F l oa tin g Pin s
The device has internal pull ups and pull downs on critical pins to place the device into known states if the pins
float. The TXD pin is pulled up to V
CC
to force a recessive input level if the pin floats. The S pin is pulled down to
GND to force the device into normal mode if the pin floats.
C A N Bu s S h or t C ir cu it C u r r e n t L imitin g
The device has several protection features that limit the short circuit current when a CAN bus line is shorted.
These include driver current limiting (dominant and recessive). The device has TXD dominant state time out to
prevent permanent higher short circuit current of the dominant state during a system fault. During CAN
communication the bus switches between dominant and recessive states with the data and control fields bits,
thus the short circuit current may be viewed either as the instantaneous current during each bus state, or as a
DC average current. For system current (power supply) and power considerations in the termination resistors
and common-mode choke ratings, use the average short circuit current. Determine the ratio of dominant and
recessive bits by the data in the CAN frame plus the following factors of the protocol and PHY that force either
recessive or dominant at certain times:
Control fields with set bits
Bit stuffing
Interframe space
TXD dominant time out (fault case limiting)
These ensure a minimumrecessive amount of time on the bus even if the data field contains a high percentage
of dominant bits.
A PPL I C A T I ON N OT E: The short circuit current of the bus depends on the ratio of recessive to dominant bits
and their respective short circuit currents. The average short circuit current may be calculated with the
following formula:
I
OS(AVG)
=%Transmit [(%REC_Bits I
OS(SS)_REC
) +(%DOM_Bits I
OS(SS)_DOM
)] +[%Receive I
OS(SS)_REC
]
Where
I
OS(AVG)
is the average short circuit current
%Transmit is the percentage the node is transmitting CAN messages
%Receive is the percentage the node is receiving CAN messages
%REC_Bits is the percentage of recessive bits in the transmitted CAN messages
%DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
I
OS(SS)_REC
is the recessive steady state short circuit current
I
OS(SS)_DOM
is the dominant steady state short circuit current
A PPL I C A T I ON N OT E: Consider the short circuit current and possible fault cases of the network when sizing
the power ratings of the termination resistance and other network components.
8 Submit Documentation Feedback Copyright 20112013, Texas Instruments Incorporated
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
S N 6 5 H V D 2 5 5
S N 6 5 H V D 2 5 6 , S N 6 5 H V D 2 5 7
www.ti.com SLLSEA2C DECEMBER 2011 REVISED SEPTEMBER 2013
A BS OL UT E MA XI MUM R A T I N GS
(1) (2 )
1.0 R A T I N G UN I T
1.1 V
CC
Supply voltage range 0.3 to 6 V
1.2 V
RXD
RXD Output supply voltage range SN65HVD256 0.3 to 6 and V
RXD
V
CC
+0.3 V
1.3 V
BUS
CAN Bus I/O voltage range (CANH, CANL) 27 to 40 V
1.4 V
Logic_Input
Logic input pin voltage range (TXD, S) 0.3 to 6 V
1.5 V
Logic_Output
Logic output pin voltage range (RXD) SN65HVD255, SN65HVD257 0.3 to 6 V
1.6 V
Logic_Output
Logic output pin voltage range (RXD) SN65HVD256 0.3 to 6 and V
I
V
RXD
+0.3 V
1.7 I
O(RXD)
RXD (Receiver) output current 12 mA
1.8 I
O(FAULT)
FAULT output current SN65HVD257 20 mA
Operating virtual junction temperature range (see THERMAL
1.9 T
J
40 to 150 C
CHARACTERISTICS)
1.10 T
A
Ambient temperature range (see THERMAL CHARACTERISTICS) 40 to 125 C
(1) Stresses beyond those listed under "absolute maximumratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to ground terminal.
T R A N S I EN T A N D EL EC T R OS T A T I C D I S C H A R GE PR OT EC T I ON
2 .0 T ES T C ON D I T I ON S R A T I N G UN I T
All pins
(1)
2.5
2.1 Human-Body Model kV
CAN bus pins (CANH, CANL)
(2)
12
2.2 Charged-Device Model All pins
(3)
750 V
2.3 Machine Model All pins
(4)
250 V
IEC 61400-4-2 according to GIFT-ICT CAN EMC test
2.4 CAN bus pins (CANH, CANL) to GND 8 kV
spec
(5)
2.5 Pulse 1 100 V
2.6 Pulse 2 +75 V
ISO7637 Transients according to GIFT - ICT CAN CAN bus pins
EMC test spec
(6)
(CANH, CANL)
2.7 Pulse 3a 150 V
2.8 Pulse 3b +100 V
(1) Tested in accordance to J EDEC Standard 22, Test Method A114.
(2) Test method based upon J EDEC Standard 22 Test Method A114, CAN bus pins stressed with respect to GND.
(3) Tested in accordance to J EDEC Standard 22, Test Method C101.
(4) Tested in accordance to J EDEC Standard 22, Test Method A115.
(5) IEC 61000-4-2 is a systemlevel ESD test. Results given here are specific to the GIFT-ICT CAN EMC Test specification conditions.
Different systemlevel configurations may lead to different results.
(6) ISO7637 is a systemlevel transient test. Results given here are specific to the GIFT-ICT CAN EMC Test specification conditions.
Different systemlevel configurations may lead to different results.
R EC OMMEN D ED OPER A T I N G C ON D I T I ON S
3.0 MI N MA X UN I T
3.1 V
CC
Supply voltage 4.5 5.5
3.2 V
RXD
RXD supply (SN65HVD256 only) 2.8 5.5
3.3 V
I
or V
IC
CAN bus terminal voltage (separately or common mode) 2 7
V
3.4 V
ID
CAN bus differential voltage -6 6
3.5 V
IH
Logic HIGH level input (TXD, S) 2 5.5
3.6 V
IL
Logic LOW level input (TXD, S) 0 0.8
3.7 I
OH(DRVR)
CAN BUS Driver High level output current 70
3.8 I
OL(DRVR)
CAN BUS Driver Lowlevel output current 70
3.9 I
OH(RXD)
RXD pin HIGH level output current 2 mA
3.10 I
OL(RXD)
RXD pin LOW level output current 2
3.11 I
O(FAULT)
FAULT pin LOW level output current SN65HVD257 2
3.12 T
A
Operational free-air temperature (see THERMAL CHARACTERISTICS) 40 125 C
Copyright 20112013, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
S N 6 5 H V D 2 5 5
S N 6 5 H V D 2 5 6 , S N 6 5 H V D 2 5 7
SLLSEA2C DECEMBER 2011 REVISED SEPTEMBER 2013 www.ti.com
EL EC T R I C A L C H A R A C T ER I S T I C S
Over recommended operating conditions, T
A
=40C to 125C (unless otherwise noted). SN65HVD256 device V
RXD
=V
CC
.
PA R A MET ER T ES T C ON D I T I ON S / C OMMEN T MI N T YP
(1)
MA X UN I T
4.0 S UPPL Y C H A R A C T ER I S T I C S
Normal Mode See Figure 10, TXD =0 V, R
L
=50
4.1 60 85
(Driving Dominant) , C
L
=open, R
CM
=open, S =0V
Normal Mode
See Figure 10, TXD =0 V, S =0V,
(Driving
4.2 CANH =-12V, R
L
=open, C
L
= 130 180
Dominant bus
open, R
CM
=open
fault)
See Figure 10, TXD =0 V, R
L
=
Normal Mode open (no load), C
L
=open, R
CM
=
4.3 I
CC
5-V Supply current 10 20 mA
(Driving Dominant) open,
S =0V
See Figure 10, TXD =V
CC
, R
L
=50
Normal Mode
4.4 , C
L
=open, R
CM
=open, 10 20
(Recessive)
S =0V
See Figure 10, TXD =V
CC
, R
L
=50
4.5 Silent Mode ,C
L
=open, R
CM
=open, 2.5 5
S =V
CC
RXD Supply
current
4.6 I
RXD
All modes RXD Floating, TXD =0V 500 A
(SN65HVD256
only)
Undervoltage detection on V
CC
for
4.7 UV
VCC
3.5 4.45 V
protected mode
4.8 V
HYS(UVVCC)
Hysteresis voltage on UV
VCC
200 mV
Undervoltage detection on V
RXD
for
4.9 UV
RXD
1.3 2.75 V
protected mode (SN65HVD256 only)
Hysteresis voltage on UV
RXD
4.10 V
HYS(UVRXD)
80 mV
(SN65HVD256 only)
5 .0 S PI N (MOD E S EL EC T I N PUT )
5.1 V
IH
HIGH-level input voltage 2 V
5.2 V
IL
LOW-level input voltage 0.8 V
5.3 I
IH
HIGH-level input leakage current S =V
CC
=5.5 V 7 100 A
5.4 I
IL
Low-level input leakage current S =0 V, V
CC
=5.5 V 1 0 1 A
5.5 I
LKG(OFF)
Unpowered leakage current S =5.5 V, V
CC
=0 V, V
RXD
=0 V 7 35 100 A
6 .0 T XD PI N (C A N T R A N S MI T D A T A I N PUT )
6.1 V
IH
HIGH level input voltage 2 V
6.2 V
IL
LOW level input voltage 0.8 V
6.3 I
IH
HIGH level input leakage current TXD =V
CC
=5.5 V 2.5 0 1 A
6.4 I
IL
Lowlevel input leakage current TXD =0 V, V
CC
=5.5 V 100 -25 7 A
6.5 I
LKG(OFF)
Unpowered leakage current TXD =5.5 V, V
CC
=0 V, V
RXD
=0 V 1 0 1 A
6.6 C
I
Input Capacitance 3.5 pF
7 .0 R XD Pin (C A N R EC EI V E D A T A OUT PUT )
See Figure 11, I
O
=2 mA. For
7.1 V
OH
HIGH level output voltage devices with V
RXD
supply V
OH
=0.8 0.8V
CC
V
V
RXD
7.2 V
OL
LOW level output voltage See Figure 11, I
O
=2 mA 0.4 V
7.3 I
LKG(OFF)
Unpowered leakage current RXD =5.5 V, V
CC
=0 V, V
RXD
=0 V 1 0 1 A
7.4 t
R
Output signal rise time See Receiver Rise Time
7.5 t
F
Output signal fall time See Receiver Fall Time
(1) All typical values are at 25C and supply voltages of V
CC
=5 V and V
RXD
=5 V, R
L
=60 .
10 Submit Documentation Feedback Copyright 20112013, Texas Instruments Incorporated
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
S N 6 5 H V D 2 5 5
S N 6 5 H V D 2 5 6 , S N 6 5 H V D 2 5 7
www.ti.com SLLSEA2C DECEMBER 2011 REVISED SEPTEMBER 2013
EL EC T R I C A L C H A R A C T ER I S T I C S (con tin u e d )
Over recommended operating conditions, T
A
=40C to 125C (unless otherwise noted). SN65HVD256 device V
RXD
=V
CC
.
PA R A MET ER T ES T C ON D I T I ON S / C OMMEN T MI N T YP
(1)
MA X UN I T
8.0 D EV I C E S WI T C H I N G C H A R A C T ER I S T I C S
Total loop delay, driver input (TXD) to
8.1 t
PROP(LOOP1)
receiver output (RXD), recessive to 150
dominant
See Figure 13, S =0 V, R
L
=60 ,
ns
C
L
=100 pF, C
L_RXD
=15 pF
Total loop delay, driver input (TXD) to
8.2 t
PROP(LOOP2)
receiver output (RXD), dominant to 150
recessive
Mode change time, fromNormal to Silent
8.3 I
MODE
See Figure 12 20 S
or fromSilent to Normal
9.0 D R I V ER EL EC T R I C A L C H A R A C T ER I S T I C S
9.1 CANH See Figure 3 and Figure 10, TXD = 2.75 4.5
Bus output voltage
V
O(D)
0 V, S =0 V, R
L
=60 , C
L
=open, V
(dominant
9.2 CANL 0.5 2.25
R
CM
=open
See Figure 3 and Figure 10, TXD =
9.3 V
O(R)
Bus output voltage (recessive) V
CC
, V
RXD
=V
CC
, S =V
CC
or 0 V
(2)
, 2 0.5V
CC
3 V
R
L
=open (no load), R
CM
=open
See Figure 3 and Figure 10, TXD =
0 V, S =0 V, 45 R
L
65 , C
L
9.4 1.5 3
=open, R
CM
=330 , 2 V V
CM

7 V, 4.75 V V
CC
5.25 V
V
OD(D)
Differential output voltage (dominant) V
See Figure 3 and Figure 10, TXD =
0 V, S =0 V, 45 R
L
65 , C
L
9.5 1.25 3.2
=open, R
CM
=330 , 2 V V
CM

7 V, 4.5V V
CC
5.5 V
See Figure 3 and Figure 10, TXD =
9.6 V
CC
, S =0 V, R
L
=60 , C
L
=open, 0.12 0.012
R
CM
=open
V
OD(R)
Differential output voltage (recessive) V
See Figure 3 and Figure 10, TXD =
V
CC
, S =0 V, R
L
=open (no load),
9.7 0.100 0.050
C
L
=open, R
CM
=open, 40C T
A
85C
Output symmetry (dominant or See Figure 3 and Figure 10, S at 0
recessive) 9.8 V
SYM
V, R
L
=60 , C
L
=open, R
CM
= 0.4 0.4 V
open (V
CC
V
O(CANH)
V
O(CANL)
)
See Figure 3 and Figure 15, V
CANH
9.9 160
=0 V, CANL =open, TXD =0 V
short circuit steady-state output current,
I
OS(SS)_DOM
mA
Dominant
See Figure 3 and Figure 15, V
CANL
=
9.10 160
32 V, CANH =open, TXD =0 V
See Figure 3 and Figure 15, 20 V
short circuit steady-state output current, V
BUS
32 V, Where V
BUS
=CANH =
9.11 I
OS(SS)_REC
8 8 mA
Recessive CANL, TXD =V
CC
, Normal and
Silent Modes
9.12 C
O
Output capacitance See receiver input capacitance
(2) For the bus output voltage (recessive) will be the same if the device is in normal mode with S pin LOW or if the device is in silent mode
with the S pin is HIGH.
Copyright 20112013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
S N 6 5 H V D 2 5 5
S N 6 5 H V D 2 5 6 , S N 6 5 H V D 2 5 7
SLLSEA2C DECEMBER 2011 REVISED SEPTEMBER 2013 www.ti.com
EL EC T R I C A L C H A R A C T ER I S T I C S (con tin u e d )
Over recommended operating conditions, T
A
=40C to 125C (unless otherwise noted). SN65HVD256 device V
RXD
=V
CC
.
PA R A MET ER T ES T C ON D I T I ON S / C OMMEN T MI N T YP
(1)
MA X UN I T
10.0 D R I V ER S WI T C H I N G C H A R A C T ER I S T I C S
Propagation delay time, HIGH TXD to
10.1 t
pHR
50 70
Driver Recessive
Propagation delay time, LOW TXD to
10.2 t
pLD
40 70
See Figure 10, S =0 V, R
L
=60 , Driver Dominant
ns
C
L
=100 pF, R
CM
=open
10.3 t
sk(p)
Pulse skew(|t
pHR
- t
pLD
|) 10
10.4 t
R
Differential output signal rise time 10 30
10.5 t
F
Differential output signal fall time 17 30
Differential output signal rise time,
10.6 t
R(10k)
35
R
L
=10 k
See Figure 10, S =0 V, R
L
=10 k,
ns
CL
=10 pF, R
CM
=open
Differential output signal fall time,
10.7 t
F(10k)
100
R
L
=10 k
See Figure 14, R
L
=60 , C
L
=
10.8 t
TXD_DTO
Dominant timeout
(3)
1175 3700 s
open
11.0 R EC EI V ER EL EC T R I C A L C H A R A C T ER I S T I C S
Positive-going input threshold voltage,
11.1 V
IT+
900 mV
normal mode
See Figure 11, Table 3 and Table 6
Negative-going input threshold voltage,
11.2 V
IT
500 mV
normal mode
11.3 V
HYS
Hysteresis voltage (V
IT+
- V
IT
) 125 mV
Power-off (unpowered) bus input C
ANH
=C
ANL
=5 V, V
CC
=0 V, V
RXD
11.4 I
IOFF(LKG)
5.5 A
leakage current =0 V
Input capacitance to ground (CANH or TXD =V
CC
, V
RXD
=V
CC
, V
I
=0.4 sin
11.5 C
I
25 pF
CANL) (4E6 t) +2.5 V
TXD =V
CC
, V
RXD
=V
CC
, V
I
=0.4 sin
11.6 C
ID
Differential input capacitance 10 pF
(4E6 t)
11.7 R
ID
Differential input resistance 30 80 k
TXD =V
CC
=V
RXD
=5 V, S =0 V
11.8 R
IN
Input resistance (CANH or CANL) 15 40 k
Input resistance matching: V
(CANH)
=V
(CANL)
, 40C T
A

11.9 R
IN(M)
3% 3%
85C [1 R
IN(CANH)
/ R
IN(CANL)
] 100%
12 .0 R EC EI V ER S WI T C H I N G C H A R A C T ER I S T I C S
Propagation delay time, recessive input
12.1 t
pRH
70 90 ns
to high output
Propagation delay time, dominant input
12.2 t
pDL
70 90 ns
See Figure 11, C
L_RXD
=15 pF
to lowoutput
12.3 t
R
Output signal rise time 4 20 ns
12.4 t
F
Output signal fall time 4 20 ns
Receiver dominant time out
12.5 t
RXD_DTO
(4)
(SN65HVD257 only) See Figure 8, 1380 4200 s
C
L_RXD
=15 pF
(3) The TXD dominant timeout (t
TXD_DTO
) disables the driver of the transceiver once the TXD has been dominant longer than t
TXD_DTO
,
which releases the bus lines to recessive, preventing a local failure fromlocking the bus dominant. The driver may only transmit
dominant again after TXD has been returned HIGH (recessive). While this protects the bus fromlocal faults, locking the bus dominant, it
limits the minimumdata rate possible. The CAN protocol allows a maximumof eleven successive dominant bits (on TXD) for the worst
case, where five successive dominant bits are followed immediately by an error frame. This, along with the t
TXD_DTO
minimum, limits the
minimumbit rate. The minimumbit rate may be calculated by: MinimumBit Rate =11 / t
TXD_DTO
=11 bits / 1175 s =9.4 kbps.
(4) The RXD timeout (t
RXD_DTO
) disables the driver of the transceiver once the RXD has been dominant longer than t
RXD_DTO
, which
releases the bus lines to recessive, preventing a local failure fromlocking the bus dominant. The driver may only transmit dominant
again after RXD has been returned HIGH (recessive). While this protects the bus fromlocal faults, locking the bus dominant, it limits the
minimumdata rate possible. The CAN protocol allows a maximumof eleven successive dominant bits (on RXD) for the worst case,
where five successive dominant bits are followed immediately by an error frame. This, along with the t
RXD_DTO
minimum, limits the
minimumbit rate. The minimumbit rate may be calculated by: MinimumBit Rate =11 / t
RXD_DTO
=11 bits / 1380 s =8 kbps.
12 Submit Documentation Feedback Copyright 20112013, Texas Instruments Incorporated
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
S N 6 5 H V D 2 5 5
S N 6 5 H V D 2 5 6 , S N 6 5 H V D 2 5 7
www.ti.com SLLSEA2C DECEMBER 2011 REVISED SEPTEMBER 2013
EL EC T R I C A L C H A R A C T ER I S T I C S (con tin u e d )
Over recommended operating conditions, T
A
=40C to 125C (unless otherwise noted). SN65HVD256 device V
RXD
=V
CC
.
PA R A MET ER T ES T C ON D I T I ON S / C OMMEN T MI N T YP
(1)
MA X UN I T
13.0 F A UL T Pin (F a u l t Ou tpu t), S N 6 5 H V D 2 5 7 on l y
13.1 I
CH
Output current high level FAULT =V
CC
, See Figure 9 10 10 A
13.2 I
CL
Output current lowlevel FAULT =0.4 V, See Figure 9 5 12 mA
T H ER MA L C H A R A C T ER I S T I C S
13.0 T H ER MA L MET R I C
(1)
T ES T C ON D I T I ON S T YP UN I T
13.1
J A
J unction-to-air thermal resistance High-K thermal resistance
(2)
107.5
13.2
J B
J unction-to-board thermal resistance
(3)
48.9
13.3
J C(TOP)
J unction-to-case (top) thermal resistance
(4)
56.7 C/W
13.4
J T
J unction-to-top characterization parameter
(5)
12.1
13.5
J B
J unction-to-board characterization parameter
(6)
48.2
V
CC
=5 V, V
RXD
=5 V, T
J
=27C, R
L
=60 , S at
0 V, Input to TXD at 250 kHz, 25%duty cycle
13.6 square wave, C
L_RXD
=15 pF. Typical CAN 115
operating conditions at 500kbps with 25%
transmission (dominant) rate.
P
D
Average power dissipation mW
V
CC
=5.5 V, V
RXD
=5.5 V, T
J
=150C, R
L
=50 ,
S at 0 V, Input to TXD at 500 kHz, 50%duty cycle
13.7 square wave, C
L_RXD
=15 pF. Typical high load 268
CAN operating conditions at 1mbps with 50%
transmission (dominant) rate and loaded network.
13.8 Thermal shutdown temperature 170 C
13.9 Thermal shutdown hysteresis 5 C
(1) For more information about traditional and newthermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a J EDEC-standard, High-K board, as
specified in J ESD51-7, in an environment described in J ESD51-2a.
(3) he junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in J ESD51-8.
(4) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific J EDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(5) The junction-to-top characterization parameter,
J T
, estimates the junction temperature of a device in a real systemand is extracted
fromthe simulation data for obtaining
J A
, using a procedure described in J ESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter,
J B
estimates the junction temperature of a device in a real systemand is extracted
fromthe simulation data for obtaining
J A
, using a procedure described in J ESD51-2a (sections 6 and 7).
Copyright 20112013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
V
OD
R
L
CANH
CANL
TXD
R
CM
R
CM
V
CM
C
L
TXD
0.9V
0.5 V
V
OD
t
pLD
t
pHR
50% 50%
V
O(CANH)
V
O(CANL)
t
R
t
F
0V
90%
10%
V
CC
TXD
DTO
RXD
DTO
Thermal
Shutdown
FAULT
GND
+
-
I
FAULT
UV
Lockout
V
O
CANH
RXD
CANL
V
ID
50%
0.9V
0.5V
V
ID
t
RXD_DTO
0V
V
ID(D)
RXD
0V
V
OH
C
L_RXD
S N 6 5 H V D 2 5 5
S N 6 5 H V D 2 5 6 , S N 6 5 H V D 2 5 7
SLLSEA2C DECEMBER 2011 REVISED SEPTEMBER 2013 www.ti.com
PA R A MET ER MEA S UR EMEN T I N F OR MA T I ON
F ig u r e 8. R XD D omin a n t T ime ou t T e s t C ir cu it a n d Me a s u r e me n t
F ig u r e 9. F A UL T T e s t a n d Me a s u r e me n t
F ig u r e 10. D r iv e r T e s t C ir cu it a n d Me a s u r e me n t
14 Submit Documentation Feedback Copyright 20112013, Texas Instruments Incorporated
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
CANH
CANL
TXD
C
L
V
O
C
L_RXD
RXD
S
V
I
0 V
t
MODE
S
RXD
V
OH
V
OL
V
CC
50%
50%
R
L
0 V
V
O
C
L_RXD
CANH
RXD
CANL
V
ID
V
ID
0 . 5 V
0 . 9 V
1 . 5 V
0 V
V
O(RXD)
50 %
V
OH
V
OL
t
pDL
t
pRH
90 %
10 %
t
R
t
F
I
O
S N 6 5 H V D 2 5 5
S N 6 5 H V D 2 5 6 , S N 6 5 H V D 2 5 7
www.ti.com SLLSEA2C DECEMBER 2011 REVISED SEPTEMBER 2013
PA R A MET ER MEA S UR EMEN T I N F OR MA T I ON (con tin u e d )
F ig u r e 11. R e ce iv e r T e s t C ir cu it a n d Me a s u r e me n t
F ig u r e 12 . t
MOD E
T e s t C ir cu it a n d Me a s u r e me n t
T a b l e 6 . R e ce iv e r D if f e r e n tia l I n pu t V ol ta g e T h r e s h ol d T e s t
I N PUT OUT PUT
V
CANH
V
CANL
|V
ID
| R
XD
-1.1V -2.0 V 900 mV L
V
OL
7.0 V 6.1 V 900 mV L
-1.5 V -2.0 V 500 mV H
7.0 V 6.5 V 500 mV H V
OH
Open Open X H
Copyright 20112013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
CANH
CANL
TXD
0V
V
BUS
I
OS
or
200 s m
I
OS
V
BUS
V
BUS
V
BUS
0V
V
BUS
V
OD
CANH
CANL
TXD
C
L
TXD
0.9V
0.5V
0V
V
IH
t
TXD_DTO
0 V
R
L
V
OD
V
OD(D)
CANH
CANL
TXD
C
L
C
L_RXD
RXD
S
V
I
0V
t
PROP(LOOP1)
TXD
RXD
V
OH
V
OL
V
CC
0 V
50%
50%
V
O
R
L
t
PROP(LOOP2)
S N 6 5 H V D 2 5 5
S N 6 5 H V D 2 5 6 , S N 6 5 H V D 2 5 7
SLLSEA2C DECEMBER 2011 REVISED SEPTEMBER 2013 www.ti.com
F ig u r e 13. T
PR OP(L OOP)
T e s t C ir cu it a n d Me a s u r e me n t
F ig u r e 14. T XD D omin a n t T ime ou t T e s t C ir cu it a n d Me a s u r e me n t
F ig u r e 15 . D r iv e r S h or t C ir cu it C u r r e n t T e s t a n d Me a s u r e me n t
16 Submit Documentation Feedback Copyright 20112013, Texas Instruments Incorporated
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
3-V MCU
SN65HVD256
CAN Transceiver
S
RXD
TXD
CANH
CANL
Port x
RXD
TXD
V
CC
8
1
4
2
3
7
5
6
5-V Voltage
Regulator
(e.g. TPSxxxx)
V
OUT
GND
V
RXD
V
IN
3-V Voltage
Regulator
V
IN
V
OUT
V
IN
(e.g. TPSxxxx)
V
CC
5-V MCU
SN65HVD255
CAN Transceiver
S
RXD
TXD
CANH
CANL
Port x
RXD
TXD
V
CC
8
1
4
2
3
7
5
6
5-V Voltage
Regulator
(e.g.TPSxxxx)
V
OUT
GND
NC
V
IN
V
IN
V
CC
S N 6 5 H V D 2 5 5
S N 6 5 H V D 2 5 6 , S N 6 5 H V D 2 5 7
www.ti.com SLLSEA2C DECEMBER 2011 REVISED SEPTEMBER 2013
A PPL I C A T I ON I N F OR MA T I ON
F ig u r e 16 . T y pica l 5 V A ppl ica tion
F ig u r e 17 . T y pica l 3.3V A ppl ica tion
Copyright 20112013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
S N 6 5 H V D 2 5 5
S N 6 5 H V D 2 5 6 , S N 6 5 H V D 2 5 7
SLLSEA2C DECEMBER 2011 REVISED SEPTEMBER 2013 www.ti.com
BUS L OA D I N G, L EN GT H A N D N UMBER OF N OD ES
The ISO11898 Standard specifies a maximum bus length of 40m and maximum stub length of 0.3m with a
maximum of 30 nodes. However, with careful design, users can have longer cables, longer stub lengths, and
many more nodes to a bus. A large number of nodes requires a transceiver with high input impedance such as
the SN65HVD25x family.
Many CAN organizations and standards have scaled the use of CAN for applications outside the original
ISO11898. They have made systemlevel trade offs for data rate, cable length, and parasitic loading of the bus.
Examples of some of these specifications are ARINC825, CANopen, DeviceNet and NMEA200.
A CAN network design is a series of tradeoffs, but these devices operate over wide common-mode range. In
ISO11898-2 the driver differential output is specified with a 60 load (the two 120 termination resistors in
parallel) and the differential output must be greater than 1.5V. The SN65HVD25x family is specified to meet the
1.5V requirement with a 45 load incorporating the worst case including parallel transceivers. The differential
input resistance of the SN65HVD25x is a minimum of 30K. If 167 SN65HVD25x family transceivers are in
parallel on a bus, this is equivalent to a 180 differential load worst case. That transceiver load of 180 in
parallel with the 60 gives a total 45. Therefore, the SN65HVD25x family theoretically supports over 167
transceivers on a single bus segment with margin to the 1.2V minimumdifferential input at each node. However
for CAN network design margin must be given for signal loss across the system & cabling, parasitic loadings,
network imbalances, ground offsets and signal integrity thus a practical maximumnumber of nodes is typically
much lower. Bus length may also be extended beyond the original ISO11898 standard of 40mby careful system
design and datarate tradeoffs. For example CANopen network design guidelines allow the network to be up to
1kmwith changes in the termination resistance, cabling, less than 64 nodes and significantly lowered data rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO11898 CAN standard. In using this flexibility comes the
responsibility of good network design and balancing these tradeoffs.
18 Submit Documentation Feedback Copyright 20112013, Texas Instruments Incorporated
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
CAN
Transceiver
CANL
CANH
C
SPLIT
CAN
Transceiver
R
TERM
Standard Termination Split Termination
CANL
CANH
R /2
TERM
R /2
TERM
MCU or DSP
CAN
Controller
CAN
Transceiver
Node 1
MCU or DSP
CAN
Controller
CAN
Transceiver
Node 2
MCU or DSP
CAN
Controller
CAN
Transceiver
Node 3
MCU or DSP
CAN
Controller
CAN
Transceiver
Node n
(with termination)
R
TERM
R
TERM
S N 6 5 H V D 2 5 5
S N 6 5 H V D 2 5 6 , S N 6 5 H V D 2 5 7
www.ti.com SLLSEA2C DECEMBER 2011 REVISED SEPTEMBER 2013
C A N T ER MI N A T I ON
The ISO11898 standard specifies the interconnect to be a twisted pair cable (shielded or unshielded) with 120
characteristic impedance (Z
O
). Resistors equal to the characteristic impedance of the line should be used to
terminate both ends of the cable to prevent signal reflections. Unterminated drop lines (stubs) connecting nodes
to the bus should be kept as short as possible to minimize signal reflections. The termination may be on the
cable or in a node, but if nodes may be removed fromthe bus the termination must be carefully placed so that it
is not removed fromthe bus.
F ig u r e 18. T y pica l C A N Bu s
Termination may be a single 120 resistor at the end of the bus, either on the cable or in a terminating node. If
filtering and stabilization of the common mode voltage of the bus is desired, then split termination may be used.
(See Figure 19). Split termination improves the electromagnetic emissions behavior of the network by eliminating
fluctuations in the bus common-mode voltages at the start and end of message transmissions.
F ig u r e 19. C A N Bu s T e r min a tion C on ce pts
Copyright 20112013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
~
~ ~
~
P
SN65HVD257
An
R
X
D
_
A
T
X
D
F
A
U
L
T
_
A
R
X
D
R
X
D
_
B
SN65HVD257
Bn
F
A
U
L
T
_
B
S
_
B
S
_
A
P
SN65HVD257
A3
R
X
D
_
A
T
X
D
F
A
U
L
T
_
A
R
X
D
R
X
D
_
B
SN65HVD257
B3
F
A
U
L
T
_
B
S
_
B
S
_
A
P
SN65HVD257
A2
R
X
D
_
A
T
X
D
F
A
U
L
T
_
A
R
X
D
R
X
D
_
B
SN65HVD257
B2
F
A
U
L
T
_
B
S
_
B
S
_
A
P
SN65HVD257
A1
R
X
D
_
A
T
X
D
F
A
U
L
T
_
A
R
X
D
R
X
D
_
B
SN65HVD257
B1
F
A
U
L
T
_
B
S
_
B
S
_
A
S N 6 5 H V D 2 5 5
S N 6 5 H V D 2 5 6 , S N 6 5 H V D 2 5 7
SLLSEA2C DECEMBER 2011 REVISED SEPTEMBER 2013 www.ti.com
Exa mpl e : F u n ction a l S a f e ty Us in g th e S N 6 5 H V D 2 5 7 in a R e d u n d a n t Ph y s ica l L a y e r C A N
N e twor k T opol og y
CAN is a standard linear bus topology using 120 twisted pair cabling. The SN65HVD257 CAN device includes
several features to use the CAN physical layer in nonstandard topologies with only one CAN link layer controller
(P) interface. This allows much greater flexibility in the physical topology of the bus while reducing the digital
controller and software costs. The combination of RXD DTO and the FAULT output allows great flexibility, control
and monitoring of these applications.
A simple example of this flexibility is to use two SN65HVD257 devices in parallel with an AND gate to achieve
redundancy (parallel) of the physical layer (cabling &PHYs) in a CAN network.
For the CAN bit-wise arbitration to work, the RXD outputs of the transceivers must connect via AND gate logic so
that a dominant bit (low) fromany of the branches is received by the link layer logic (P), and appears to the link
layer and above as a single physical network. The RXD DTO feature prevents a bus stuck dominant fault in a
single branch fromtaking down the entire network by forcing the RXD pin for the transceivers on the branch with
the fault back to the recessive after the t
RXD_DTO
time. The remaining branch of the network continues to function.
The FAULT pin of the transceivers on the branch with the fault indicates this via the FAULT output to their host
processors, which diagnose the failure condition. The S pin (silent mode pin) may be used to put a branch in
silent mode to check each branch for other faults. Thus it is possible to implement a robust and redundant CAN
network topology in a very simple and lowcost manner.
These concepts can be expanded into more complicated & flexible CAN network topologies to solve various
systemlevel challenges with a networked infrastructure.
A. CAN nodes with termination are PHY A, PHY B, PHY An and PHY Bn.
B. RXD DTO prevents a single branch-stuck-dominant condition fromblocking the redundant branch via the AND logic
on RXD. The transceivers signal a received bus stuck dominant fault via the FAULT pin. The systemdetects which
branch is stuck dominant, and issues a system warning. Other network faults on a single branch that appear as
recessive (not blocking the redundant network) may be detected through diagnostic routines, and using the Silent
Mode of the PHYs to use only one branch at a time for transmission during diagnostic mode. This combination allows
robust fault detection and recovery within single branches so that they may be repaired and again provide
redundancy of the physical layer.
F ig u r e 2 0. T y pica l R e d u n d a n t Ph y s ica l L a y e r T opol og y Us in g th e S N 6 5 H V D 2 5 7
20 Submit Documentation Feedback Copyright 20112013, Texas Instruments Incorporated
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
S N 6 5 H V D 2 5 5
S N 6 5 H V D 2 5 6 , S N 6 5 H V D 2 5 7
www.ti.com SLLSEA2C DECEMBER 2011 REVISED SEPTEMBER 2013
R EV I S I ON H I S T OR Y
C h a n g e s f r om Or ig in a l (D e ce mb e r 2 011) to R e v is ion A Pa g e
Updates the Features list ...................................................................................................................................................... 1
Updated the Applications list ................................................................................................................................................ 1
Added text to the Description "The SN65HVD257 adds additional.." ................................................................................... 1
Changed Figure 1 - Functional Block Diagramto include HVD257 and Note changes. ...................................................... 1
Added SN65HVD257 to the D PACKAGE OPTIONS images .............................................................................................. 2
Changed the DEVICE OPTIONS table ................................................................................................................................. 2
Added SN65HVD257 FAULT pin to the PIN FUNCTIONS table ......................................................................................... 2
Added SN65HVD257 to the Ordering Information table ....................................................................................................... 2
Added footnote for SN65HVD257 function to Table 3 .......................................................................................................... 4
Added 5 V V
CC
with FAULT Open-Drain Output Device (SN65HVD257) section ................................................................ 5
Added RXD Dominant Timeout (SN65HVD257) section ...................................................................................................... 5
Added FAULT pin information .............................................................................................................................................. 6
Added SN65HVD257 FAULT pin information to the Abs Max table ..................................................................................... 9
Added FAULT pin information to the ROC table .................................................................................................................. 9
changed R
ID
- Differential input resistance value from3 k to 30 k ................................................................................ 12
Added t
RXD_DTO
- SN65HVD257 information ....................................................................................................................... 12
Added Figure 8 "RXD Dominant Timeout Test Circuit and Measurement" ........................................................................ 14
Added Figure 9 "FAULT Test and Measurement" .............................................................................................................. 14
Added Example: Functional Safety Using the SN65HVD257 in a Redundant Physical Layer CAN Network Topology
section ................................................................................................................................................................................. 20
C h a n g e s f r om R e v is ion A (Ju n e 2 012 ) to R e v is ion B Pa g e
Added SN65HVD257 status to production in Ordering Information table ............................................................................ 2
C h a n g e s f r om R e v is ion B (Ju n e 2 012 ) to R e v is ion C Pa g e
Added Figure 6 - Example Timing Diagramfor TXD DTO and FAULT Pin ......................................................................... 7
Added Table 6 - Receiver Differential Input Voltage Threshold Test ................................................................................. 15
Added - Bus loading, length and number of nodes section to Application Information ...................................................... 18
Copyright 20112013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jul-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (C) Device Marking
(4/5)
Samples
SN65HVD255D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 HVD255
SN65HVD255DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 HVD255
SN65HVD256D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 HVD256
SN65HVD256DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 HVD256
SN65HVD257D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 HVD257
SN65HVD257DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 HVD257

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jul-2013
Addendum-Page 2

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
SN65HVD255DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD256DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD257DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Jul-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65HVD255DR SOIC D 8 2500 340.5 338.1 20.6
SN65HVD256DR SOIC D 8 2500 340.5 338.1 20.6
SN65HVD257DR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Jul-2013
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per J ESD46, latest issue, and to discontinue any product or service per J ESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as components) are sold subject to TIs terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TIs terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license froma third party under the patents or other intellectual property of the
third party, or a license fromTI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different fromor beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harmand take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TIs goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or enhanced plasticare designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLPProducts www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright 2014, Texas Instruments Incorporated