ELE 724 / EE 8502

CMOS Analog Integrated Circuits

Laboratory Manual
Dr. F. Yuan
1
Department of Electrical and Computer Engineering
Ryerson University
Toronto, Ontario, Canada
September 2, 2014
1
This laboratory manual is an essential component of ELE 724 / EE 8502 CMOS Analog
Integrated Circuits oered in the Department of Electrical and Computer Engineering at
Ryerson University. Permission to duplicate this document is granted for educational
purpose. Please report any error in this Laboratory Manual to Professor F. Yuan at
fyuan@ryerson.ca.
Contents
1 Preface 2
2 Marking Scheme and Requirements 4
2.1 Marking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Condentiality . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Laboratory One : Cadence Tutorial 6
3.1 Pre-Laboratory . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Laboratory Work . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.1 Cadence Environment . . . . . . . . . . . . . . . . . . 7
3.2.2 Cadence Facilities . . . . . . . . . . . . . . . . . . . . . 10
3.2.3 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2.4 Create Schematic . . . . . . . . . . . . . . . . . . . . . 13
3.2.5 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 Post-Laboratory Report . . . . . . . . . . . . . . . . . . . . . 28
4 Laboratory Two : Single-Stage Ampliers 29
4.1 Pre-Laboratory . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2 Laboratory Work . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.3 Post-Laboratory Report . . . . . . . . . . . . . . . . . . . . . 31
5 Laboratory Three : Three-Stage Cascode Voltage Amplier 33
5.1 Pre-Laboratory . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1
2
5.2 Laboratory Work . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.3 Post-Laboratory Report . . . . . . . . . . . . . . . . . . . . . 35
6 Laboratory Four : Voltage Comparator with Hysteresis 37
6.1 Pre-Laboratory . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1.2 Allstot Voltage Comparator . . . . . . . . . . . . . . . 38
6.1.3 Pre-Lab Requirements . . . . . . . . . . . . . . . . . . 40
6.2 Laboratory Work . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.3 Post-Laboratory Report . . . . . . . . . . . . . . . . . . . . . 41
7 Laboratory Five : Voltage References 44
7.1 Pre-Laboratory . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.2 Laboratory Work . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.3 Post-Laboratory Report . . . . . . . . . . . . . . . . . . . . . 45
Chapter 1
Preface
This laboratory manual is an essential component of ELE 704 / EE 8502
CMOS Analog Integrated Circuits oered in the Department of Electrical
and Computer Engineering at Ryerson University. This laboratory manual
consists of ve laboratories.
Chapter 3 provides a step-by-step walk-through of using Cadence CAD
tools to analyze and design integrated circuits and systems.
Chapter 4 is concerned with the design of single-stage voltage ampli-
ers. Three basic congurations of voltage-mode ampliers, namely,
common-source, common-gate, and common-drain ampliers and their
characteristics are investigated in detail in this laboratory :
Chapter 5 deals with the design of a three-stage cascode voltage am-
plier. The performance of the amplier including voltage gain, phase
margin, dynamic range, input and output impedances are studied.
Chapter 6 investigates the popular Allstot voltage comparator. The
hysteresis and other gure-of-merit quantifying the performance of the
comparator are investigated.
Chapter 7 deals with the design of a voltage reference with a focus on
supply voltage and temperature sensitivities.
3
CHAPTER 1. PREFACE 4
Each laboratory consists of three compulsory components, namely, pre-
laboratory report, laboratory work, and post-laboratory report.
Students must complete and hand in the pre-laboratory report of each lab-
oratory prior to undertaking the laboratory work. A post-laboratory report
that documents the ndings of the laboratory work must be handed in one
week after the scheduled laboratory work. Both pre-laboratory report and
post-laboratory report will be graded.
All laboratories in this Laboratory Manual are open-ended. Neither
schematics nor design specications are provided. Students are required to
prototype and analyze their design to ensure that the design is error-free and
meets the chosen design specications. Students are encouraged to apply the
knowledge and skills acquired from the lectures and prior studies to propose
new circuit topology and verify the performance of the proposed design using
CAD tools.
If two or more identical designs or simulation results are found, a
ZERO grade will be assigned to all reports containing the identical
designs or simulation results.
Chapter 2
Marking Scheme and
Requirements
2.1 Marking Scheme
Each laboratory consists of three compulsory components : a pre-laboratory
report that provides a theoretical investigation of the circuits to be investi-
gated in laboratory work, laboratory work where the performance of the pro-
posed circuits in the pre-laboratory report is investigated using CAD tools,
and a post-laboratory report that documents the ndings of the laboratory
work.
The marking scheme of the laboratory is given below :
Pre-laboratory report (40%).
Post-laboratory report (60%).
Pre-laboratory reports can be prepared in either Microsoft Word or La-
TeX. Hand-written pre-laboratory reports are also acceptable. Pre-laboratory
reports are due on Friday of the week before the scheduled laboratory work.
Post-laboratory reports must be prepared in either Microsoft Word or
LaTeX. Figures, tables, and expressions should be embedded in the main
5
CHAPTER 2. MARKING SCHEME AND REQUIREMENTS 6
body of the report. Hand-written post-laboratory reports will be
rejected. Post-laboratory reports are due on Friday of the week after the
scheduled laboratory work.
2.2 Requirements
In pre-laboratory reports, students are required to carry out both the
design and analysis of the circuits to be analyzed in laboratory work. A
detailed description of the requirement is given in the pre-laboratory of
each laboratory. The pre-Laboratory report must be completed prior
to the start of the laboratory work for grading. Pre-laboratory reports
will be returned to students at the start of laboratory work.
All laboratory work must be carried out individually. Attendance will
be checked during each laboratory session.
Post-laboratory reports must be professionally prepared and handed
in one week after the completion of the laboratory work. The detailed
requirement of the post-laboratory report is given in post-laboratory of
each laboratory. Hand-written post-laboratory reports will be
rejected and a zero grade will be assigned.
As per university academic policies, should two identical laboratory
reports, such as identical schematic, identical simulation results, etc,
be spotted, a zero grade will be assigned to both reports of the students.
2.3 Condentiality
Each student must sign a NDA (Non-disclosure-Agreement) before using IBM
130 nm CMOS technology for the laboratories.
Chapter 3
Laboratory One : Cadence
Tutorial
3.1 Pre-Laboratory
Pre-Laboratory must be completed and handed in prior to the
commence of the corresponding Laboratory Work
1. Derive the voltage transfer function H(s) of the circuit in Fig.3.1.
2. Obtain the zeros and poles of H(s).
3. Determine the transfer characteristics of the circuit (low-pass, high-
pass, or band-pass). Find the bandwidth of the passband.
4. Sketch the Bode plot of |H(j)| and its phase plot.
5. Obtain the resonant frequency
0
and the quality factor Qof the circuit.
7
CHAPTER 3. LABORATORY ONE : CADENCE TUTORIAL 8
C=47n
Vin
R1=22k
Vo
L=500m
R2=75
Figure 3.1: Schematic of RLC circuit
3.2 Laboratory Work
3.2.1 Cadence Environment
A. Start Up
Cadence is a set of computer-aided design tools for design, analysis, and
verication of integrated circuits. To run Cadence, you need
Unix commands
Cadence tools: Virtuoso Composer, Analog Design environment(ADE)
and Virtuoso XL
cmosp13 IBM CMRF8SF design kit in this lab
The rst step you need to do is to install Cadence in your home directory.
To do so, type pdkInstall. A window showing a variety libraries would be
pop-up Fig.3.2.
Choose cmosp13 option, which is IBM 0.13m standard CMOS technol-
ogy. Then you need to give a name for your own folder, where the lab will
be carried out and stored. Fig.3.3 shows the interface window that will be
CHAPTER 3. LABORATORY ONE : CADENCE TUTORIAL 9
Figure 3.2: pdkInstall window.
Figure 3.3: Create folder.
appeared. Before create the folder, make sure your have enough space to
nish all the labs, e.g. 100MB.
Once you successfully install the folder, a prompt box showing detail
information of how to start Cadence will occur in Fig.3.4.
Till this step, you are able to run Cadence design tools. Now the prompt
in the Linux terminal indicates you are in the folder, which is created in
the previous step. To rst run Cadence, type startCds -t cmosp13. This
command will start Cadence software and launches the Cadence Command
Interpreter Window (icfb), where you can check your current version of Ca-
CHAPTER 3. LABORATORY ONE : CADENCE TUTORIAL 10
Figure 3.4: Install completed.
dence tools and the version of the design kit being used.
B. Initialization Files
Cadence environment uses three major initialization les and one model le
of cmosp13.
cds.lib: sets the path to the libraries used in your design. This le is cre-
ated in your current folder when you start Cadence. When you start
Cadence for the rst time, cds.lib will be automatically copied to the
current directory.
.cdsinit: Customizes specic simulation environmen
.cdsenv: sets global Cadence environment.
C. Where to Find Help
In your current directory, a new folder named as, cadenceDocs, has been cre-
ated. Under this folder, the most useful documents associated with Cadence
tools and IBM pdk are linked to the original directory.
Up to this point, you have learned how to start Cadence software and
where to nd on-line help. Before jumping to Cadence tools to start your
circuit design project, it is benecial to have a look at Cadence facilities that
support the basic operation.
CHAPTER 3. LABORATORY ONE : CADENCE TUTORIAL 11
3.2.2 Cadence Facilities
A. The icfb Window
Figure 3.5: icfb window.
When Cadence starts, it brings up the icfb (Integrated Circuit front-to-
back) window, as shown in Fig.3.5. It is Cadences Command Interpreter
Window that can be thought of Cadence Shell. It is through icfb window
that you can do all of your Cadence tasks, including le management and
program execution.
B. Libraries, Cells and Views
Cadence uses the hierarchy of Library | Cell | View to manage design
data. Cadence stores design data into libraries that are not transparent to
external le systems. How each library corresponds to a physical path in
the le system is registered in the le named cds.lib, which is one of the
three major initialization les mentioned earlier. This le can be modied
using icfb |Tools| Library Path Editor. The rst thing you should do
in Cadence is to create your own library, we will come back to this point in
Cadence Walk Though shortly.
A cell contains Cadences design data, or more specically, the data of the
designed circuit. Each cell has at least one view that is the representation
of the cell. Fig.3.6 shows the Library Manager window. Each time when
a new library or a new cell is created, a new item will appear in the cor-
CHAPTER 3. LABORATORY ONE : CADENCE TUTORIAL 12
Figure 3.6: Library Manager window.
responding column of the library manager. Tow libraries that will be most
frequently used in the laboratories are
cmrf8sf - this library contains the cells of 0.13 devices, such as tran-
sistors, capacitors, inductors and resistors.
analogLib library contains basic components for analog circuits. It also
contains various types of independent and dependent sources.
3.2.3 Design Flow
In this section, we will go through the basic design steps of Cadence CAD
tools.
Step 1 - Create Schematic
Instance transistors and other elements from libraries
CHAPTER 3. LABORATORY ONE : CADENCE TUTORIAL 13
Create the schematic of the circuit by connecting elements to-
gether and modify their properties.
Create the Symbol view of the schematic view.
Step 2 - Simulation
Use simulation and waveform viewers to modify circuit parameters
until design specications are met.
Step 3 - Layout and DRC
Map the schematic onto silicon
Layout must follow the design rules of chosen technology and pass
design rule check (DRC).
Step 4 - Extraction and LVS
Create post-layout schematic from layout. Both the parasitic ca-
pacitances and resistances can be extracted from the layout in this
step.
Perform LVS (Layout versus schematic) to verify whether the
post-layout schematic matches the original schematic.
Step 5 - Post-Layout Simulation
Simulate extracted view (post-layout schematic) by taking into
account the eect of parasitic capacitances and resistances.
Using simulation results to modify the layout until design speci-
cations are met.
Up to this point, you have known the overall picture of the design ow.
In sections that follow, we will use a simple RLC circuit as an example to
walk you through these basic steps, except for step 3, 4 and 5.
CHAPTER 3. LABORATORY ONE : CADENCE TUTORIAL 14
3.2.4 Create Schematic
In this laboratory work, You are required to do the followings
Create the schematic of the RLC circuit.
Create the symbol view of the circuit.
Create a test xture circuit for testing the RLC circuit.
Perform transient analysis, AC analysis, and DC analysis on the circuit
using Cadences Spectre analog simulator.
Provide a detailed comparison between the analytical results from your
Pre-Laboratory Report and those obtained from the Laboratory Work.
A. Create New Libraries and Schematic Views
1. Create New Libraries
Figure 3.7: Create library window.
It is necessary to have a separate library to store your design cells and
their views. To do that
CHAPTER 3. LABORATORY ONE : CADENCE TUTORIAL 15
From the icfb menu, select File | New | Library
Navigate to the cadence13 directory (if not already there)
Type in mylibs as the name of your new library
Select to attach to an existing technology library, click OK,
then select the cmrf8sf library when prompted. By selecting the
IBM 0.13m library, you will be able to use the cells from cmrf8sf
library for your design.
2. Create new design cells
Figure 3.8: Create schematic view window.
From the icfb menu, select File | New | Cellview. You are
prompted for the library to place the new cell in and what type
of view you are creating.
Select mylibs that was created in the previous step and ensure
schematic is selected as the tool for your new cell. Note that
schematic is the default name of the view.
Enter rlc as the cellname and select OK to open the new cell in
composer.
CHAPTER 3. LABORATORY ONE : CADENCE TUTORIAL 16
The rest of this section describes the steps to create the rlc circuit
shown at Fig. 3.1 in schematic view.
B. Add Components and Wires
When creating a schematic, you place instances that were created previously,
edit their properties e.g. resistance, capacitance, width, etc, and wire them
together. In the case of the RLC circuit, you will place two resistors, one
capacitor, one inductor and ground. You wire the devices together using the
wire tool, and wire snapping, and then edit the property of the devices to
set R
1
=75k, R
2
= 75, C=47nF, and L=500mH.
1. Instantiate Components
Figure 3.9: Add instance window.
To place a resistor, follow these steps from the main composer window.
Click on the Instance Icon. The Add Instance window will
appear as shown in Fig. 3.9. Click on the Browse button.
CHAPTER 3. LABORATORY ONE : CADENCE TUTORIAL 17
Table 3.1: Component value of RLC circuit
Component Library Cell View Value
R1 analogLib res Spectre 75 k
R2 analogLib res Spectre 75
C analogLib Cap Spectre 47 nF
L analogLib Ind Spectre 500 mH
Ground analogLib gnd symbol N/A
In the browse library window, select analogLib library, resistor
cell, and symbol view.
Move the cursor to the Schematic Editor L Editing window,
the resistor symbol follows. Also, note that the Add Instance
window has expanded to display other parameters. Before you
click on the schematic window to place the resistor symbol, edit
the form, modifying the resistance value to 75k. IMPORTANT:
Do not get concerned with all of the seemingly irrelevant param-
eters. They are used for more detailed simulations and other ap-
plications.
Click in the schematic editor window to place the resistor.
Another resistor symbol follows the cursor. Place it in the window
then click on Cancel on the Add Instance window. The form
disappears.
In the same way in which you added the resistor, add the other
instances from the library, cell, and view as indicated below.
To rotate an instance in Schematic Editor window, click once
on it to select (left-click with the mouse), then middle-click to
open the auxiliary menu. Select Rotate. Or click the rotate icon
in the toolbar.
2. Add I/O pins
CHAPTER 3. LABORATORY ONE : CADENCE TUTORIAL 18
There are many types of pins in Cadence. But here we only use
two of them, namely, input pins and output pins.
To add the input and output pins, click on the Pin icon, which is
close to the create instance icon in the schematic editor window.
The Add Pin form appears as shown in Fig. 3.10.
Figure 3.10: Add pin window.
Under Pin Names, type Vin Vout. Note that direction in the
form reads input.
Click once on the schematic window. The rst pin is placed. Note
the other pins symbol follows the cursor as you move across the
window. The Add Pin form is still active, but with only Vout
displaying in the Pin Names eld;
In the Add Pin property form, change direction to read Output.
Place the Vout pin in the schematic window. Close the Add Pin
form when all pins are added.
3. Connect Wires
Move the components that you just added around so that they
are positioned properly. Use the ESC key to terminate the mode
that you can drag the components around on the screen.
To begin connecting the wires as per the schematic of Fig. 3.1,
click on the Wire (narrow) icon.
CHAPTER 3. LABORATORY ONE : CADENCE TUTORIAL 19
While the Add Wire window is still displaying (but not selected),
press the s key on your keyboard. This snaps the wires to connect
between the little diamond-shapes displaying by the nodes.
Press s Key once on the begin-node, then click on the end-node.
Complete the schematic of the circuit as shown in Fig.3.11
Figure 3.11: Schematic View of RLC.
C. Modify the Property of Components
To modify the property of the devices of the circuit,
click once to select the instance, on the left side of the window, a
subwindow named as property editor shows the value of your current
choosing instance.
CHAPTER 3. LABORATORY ONE : CADENCE TUTORIAL 20
Modify the value of the inductor to 500 mH, the capacitance to 47 nF
and the resistance of the second resistor to 75.
Note: When you enter the value of parameters, you must enter the unit.
You have to explicitly indicate the standard SI given below (case-sensitive):
G = Giga (10
9
)
M = Mega (10
6
)
k = kilo (10
3
)
m = milli (10
3
)
u = micro (10
6
)
n = nano (10
9
)
p = pico (10
12
)
f = femto (10
15
)
a = atto (10
18
)
For example, for 20 femptoFarads, you just enter 20f. No space between
the number and sux. Do not include the unit as they are predened in the
instance property le.
D. Check and Save
Click on Check and Save icon. Cadence will check your design for
any electrical connection rule violation. The design will be saved if no
error is found.
Read the messages displayed in the icfb window carefully. Make sure
that no warnings and errors. If there is a warning or an error, go
back to the schematic window and look for ashing boxes where the
warnings/errors were found.
By clicking on the ashing box, an explanation of the error will dis-
played in the CIW window. Fix the errors/warnings until your design
is both error-free and warning-free.
CHAPTER 3. LABORATORY ONE : CADENCE TUTORIAL 21
E. Add Borders
When your design is completed and is error/warning-free. You should add a
border around your design to document the design. A border is treated as a
cell in Cadence under library, US 10th.
Navigate border library US 10th, click on the Instance icon and
chose US 10ths | Asize and add an A-size border around the RLC
schematic.
To edit the border title, click on Edit | Sheet Title and ll the form
appropriately. Then type in both your name and your student ID.
Click Check and Save icon to save your work.
F. Create Symbol Cellviews
Now we will create a symbol view to represent the RLC circuit that has just
been created.
In Schematic Editor window, click Create | Cellview | from cel-
lview. This sequence creates a symbol using the primary input and
output pins automatically. The form appears as shown in Fig.3.12.
Make sure From View Name: schematic, To View Name : sym-
bol and Tool/Data Type: schematicSymbol, then click OK.
Click OK and a new form will appear, select the Load/Save button
to expand the form.
Change the cyclic eld next to load to Analog.
Click the Load button, this will load the Analog Symbol Genera-
tion window. Then click on OK button
It is important that you click NO if a message appears calling for
Overwrite Base Cell CDF. This ensures that the parameters of the
base cell are not changed.
CHAPTER 3. LABORATORY ONE : CADENCE TUTORIAL 22
Figure 3.12: Create symbol cellview window.
A Symbol Editing window will appear. The green box denes the
dimensions of the symbol. The red box denes the selection region of
the symbol. The cdsTerm(Vout) represents the pin-names. The
cdsParam(1,2,3) represents the parameters of each instance. The
cdsName( ) represents the cell-name.
You can re-shape your symbol.
Click on the Label icon and name the circuit properly.
Save and close the window.
G. Create TestFixtures
A testxture is a new schematic cell used for testing the designed circuits.
In this case, it contains rlc symbol as one of its instances. You will have
to go through the process of creating the schematic view again to create the
testxture.
Go to: icfb | File | New | Cellview.... Create a new cell called
test rlc, with a schematic cellview.
CHAPTER 3. LABORATORY ONE : CADENCE TUTORIAL 23
Click OK. In the new Schematic Editor window. Add instances, con-
nect your new circuit using components according to the following ta-
ble, and referring to the schematic in Fig. 3.13. Note: Press ESC if
you want quit current command.
Table 3.2: Components in testxture
Component Library Cell View Value
RLC Mylibs rlc Symbol N/A
C analogLib Capacitor Spectre 1 pF
Input analogLib vsin Symbol AC Magnitude = 1
Amplitude = 50 mV
Frequency = 1 M
Oset Voltage=0
gnd analogLib gnd symbol N/A
To add the wire names, click on Wire Name icon.
Under Names, type in Vin and Vout. Click OK. The name Vin
follows the mouse as you move over the schematic window. Click on
the input wire as shown in Fig. 3.13 to place it. The name Vout next
follows the mouse pointer. Repeat the process for Vout.
Click on Check and Save icon when done.
3.2.5 Simulation
A. Introduction
This section deals with the second step in the basic design ow. To invoke
Analog Circuit Design Environment:
CHAPTER 3. LABORATORY ONE : CADENCE TUTORIAL 24
Figure 3.13: Schematic of the TextFixture of RLC circuit.
Open test rlc schematic view. You may skip this step if test rlc is
already open.
In the test rlc schematic window, select Launch | ADE L.
Fig.3.14 shows what the window looks like when fully congured.
The icons on the right provide quick access to frequent commands/menus;
The Design Area on the top left lists the library, cell, and cellView
of the design being simulated.
The Analysis Area on the top right lists the types of analysis, any
arguments (i.e. time interval), and whether it is enabled to perform
the simulation in the current run.
The Design Variables Area on the bottom left lists component set-
up as variables. Select Variables | Copy from Cellview and the
variable will appear in this list.
CHAPTER 3. LABORATORY ONE : CADENCE TUTORIAL 25
Figure 3.14: Analog Design Environment.
The Outputs Area lists names of nets/signals/expressions/ports
to be plotted on the output waveform window;
B. Initialize Simulation Environment
In the window of Analog Design Environment, do the followings
Choosing a simulation engine. Select Setup | Simulator/Directory/Host.
Ensure that the Simulator is set to Spectre.
When you leave the simulation window, you will be prompted to save
the current state. Save it using the default name state1 or give a
name associated with your design, e.g. rlc test. This will save you
from repeating the initializing process for the next time you simulate
the circuit. You also can use the same state le for other circuits.
CHAPTER 3. LABORATORY ONE : CADENCE TUTORIAL 26
C. Choose Analysis
To begin an analysis, click on Choose Analysis icon at right area from the
Simulation Environment window. A new window will appear. Do not
close this window until all three-analysis modes are set.
1. Transient Analysis
Select tran in the new window.
Set the stop time to a number, e.g. 3 (Note that the start time
is set to 0 by default).
Turn on the Enabled Field and click Apply. Note that by
setting Enable Field, you enable the transient analysis. You can
disable the transient analysis by resetting this option.
2. AC Analysis
Select ac.
Set the Sweep Variable to Frequency.
Set the Sweep Range to Start: 0.01K and Stop: 10K.
Set the Sweep Type to log with 50 pts decade.
Turn on the Enabled Field and click Apply.
3. DC Analysis or DC Sweep
Select dc.
In the Sweep Variable Section, select Component Parameter.
By doing so, you will be able to choose a component by clicking
on it from the schematic view.
Select the component Vsin from the schematic window. A new
form will appear.
CHAPTER 3. LABORATORY ONE : CADENCE TUTORIAL 27
Select dc parameter and click OK.
You are back to the original window (DC Analysis). Ensure the
Sweep Range to Start: 0 and Stop: 100.
Turn on the Enabled Field and click Apply.
D. Save and Plot Simulation Data
All nodal voltages are congured to be saved by the simulation environment.
But save certain voltages and currents from the circuit will require a manual
selection of these voltage and currents from the schematic view.
From the simulation window, select Outputs | Save All. Assert Se-
lect signals to output | all, Select device currents | all and click
OK.
Select Outputs | To Be Plotted | Select on Schematic. Click nets
that you want to monitor. For the simulation you are about to run,
only the input and output voltages are of our interest in this laboratory.
The current of a branch is selected by clicking on the nodes to which
the branch is connected. You can also use the component iprobe from
the library AnalogLib to measure the current of any branch. The
voltage of a node is selected by clicking on the wires that are connected
to the node.
Select the voltage of the input and output nodes.
E. Run Simulation - The Waveform Window
In the schematic editing window, click on Check and Save button. If
you see any error messages, correct the design and try this again.
Click on the icon Netlist and Run. A Waveform window showing
the results of all three analyses will appear when simulation is com-
pleted.
CHAPTER 3. LABORATORY ONE : CADENCE TUTORIAL 28
The plots of the input and output voltages are overlapped. To view
them separately, click on the analysis area (i.e. AC, DC or Transient)
and select Axes | To Strip.
Repeat the above steps for the other two waveform windows.
To change the label of an axe, double-clicking on the axis and rename
the it appropriately.
For the transient response window, place Marker A at the negative
peak of the output waveform and Marker B at the positive peak.
In the AC Response section, delete the Vin vs. Vin plot by selecting
the graph and press the delete key on the keyboard. Use a Marker to
measure the resonant frequency of the RLC circuit.
In the DC Response section, delete the Vin vs. Vin plot.
F. Print Waveforms
To print from a schematic editor window, Select File | print | Plot
Options. Chose the appropriate printer and click on OK.
To print the waveforms, go to waveform window, select File | Save
Image. Choose Graph | Properties, change background color to
white.
G. Save and Exit Cadence
From the icfb window, save your defaults and session.
From the Analog Design Environment window, click Session |
Save State, give an appropriate state name and press OK.
From the Waveform window, select Window | Save... Click OK.
Close all windows by choosing Close Window.
CHAPTER 3. LABORATORY ONE : CADENCE TUTORIAL 29
Exit from Cadence Properly.
3.3 Post-Laboratory Report
Post-Laboratory Report must be completed and handed in after the sched-
uled Laboratory Work. The followings must be included in your Post-
Laboratory Report.
1. The schematic of the RLC circuit with an appropriate border. Your
name and student ID must be shown in the border title section.
2. The schematic of your RLC test xture circuit.
3. The waveform of the output voltage of the RLC circuit from tran, AC,
and DC analyses.
4. Measure the resonant frequency, overshoot and calculate the quality
factor.
5. Comment on the resonant frequency and the quality factor of the circuit
obtained from analytical analysis of your Pre-Laboratory Report and
those obtained from the Laboratory Work.
Chapter 4
Laboratory Two : Single-Stage
Ampliers
4.1 Pre-Laboratory
Common-source, common-gate, and common-drain ampliers are the basic
building blocks of complex analog systems. In this laboratory, you are re-
quired to design and analyze common-source, common-gate, and common-
drain ampliers with only one power supply. You are required to com-
plete a pre-laboratory report prior to undertaking any laboratory work. The
pre-laboratory report is due on Friday of the week before the start of the
laboratory. A 20% penalty will apply to a late pre-laboratory report.
Pre-laboratory reports can be prepared in either Microsoft Word, LaTeX, and
other text editors. Hand-written pre-laboratory reports are also acceptable.
Your pre-laboratory report must contain the followings :
1. A cover page containing the title of the report, the name and student
identication number.
2. The schematic of common-source, common-gate, and common-drain
ampliers with biasing included. The load of the ampliers is a current
30
CHAPTER 4. LABORATORY TWO : SINGLE-STAGE AMPLIFIERS 31
source implemented using transistors in the saturation. Drive the dc
biasing condition of the transistors of the ampliers (40%).
3. The small-signal equivalent circuit of the ampliers at low frequencies.
Derive the expression of the voltage gain A
v
, the input impedance R
in
,
and the output impedance R
out
of the ampliers at low frequencies
(30%).
4. The small-signal equivalent circuit of the ampliers at high frequencies.
Find the poles of the ampliers at the input and output of the amplier
with C
gs
and C
gd
considered (30%).
4.2 Laboratory Work
1. Choose the size of each transistors properly. To obtain appropriate
DC biasing conditions, the width of PMOS transistors should be made
approximately twice that of NMOS transistors. Do not use the mini-
mum width (default) as they will make the circuits more sensitive to
process variation (mismatch eects). Use large width, for example,
10 100m, will also give you a larger g
m
, subsequently a larger volt-
age gain. For channel length, typically keep it at the minimum channel
length to avoid bandwidth reduction. Note that the channel length of
the transistors used for biasing purpose only can be increased to mini-
mize the eect of channel length modulation so as to boost the output
resistance of the transistors.
2. Create the corresponding schematic view and symbol view of each am-
plier. The substrate of the NMOS transistors should be connected to
the ground while the n-well of the PMOS transistors should be con-
nected to V
DD
.
3. Create a testxture.(You may use one text xture cell for all three
congurations).
CHAPTER 4. LABORATORY TWO : SINGLE-STAGE AMPLIFIERS 32
4. Perform DC analysis to nd out the DC operating point of each tran-
sistor: record V
GS
, V
DS
, and I
D
of each transistors. Using pinch-o
condition to verify that all transistors are biased in the saturation.
5. Perform DC analysis by sweeping the amplitude of the input DC source
and record the output. Since V
DD
= 1.2 V, the maximum amplitude
of the input voltage should be 1.2 V. Plot the output voltage as a
function of the input DC voltage. Record the maximum input voltage
at which a clear distortion of the output voltage is observed. This
analysis allows you to determine the dynamic range of the ampliers,
i.e., the maximum input voltage range of the ampliers, approximately.
6. Perform AC analysis and determine R
in
and R
out
. To determine R
in
,
all DC biasing voltage sources should be retained. A small AC signal
source v
in
is applied to the input and the corresponding current at the
input node of the ampliers i
in
is recorded. R
in
= v
in
/i
in
. To determine
R
out
, all DC biasing voltage sources should be retained and the input
source should be removed. Apply a small output current source i
o
at
the output node of the amplier and record the corresponding voltage
of the output node v
o
, R
out
= v
o
/i
o
.
7. Perform AC analysis. Find the bandwidth and phase margin of the
ampliers. Plot the magnitude and phase responses of the ampliers.
8. Perform transient analysis to nd out the average slew rate of the
ampliers to a step voltage input whose amplitude should be smaller
than v
in,max
determined earlier (the amount of time for the output to
rise from 10% to 90%).
4.3 Post-Laboratory Report
The post-lab report must be prepared in either Microsoft Word, LaTeX, or
other text editors. Figures, tables, and expressions should be embedded in
CHAPTER 4. LABORATORY TWO : SINGLE-STAGE AMPLIFIERS 33
the main body of the report. Cadence print-outs attached to the end
of the report are not acceptable. Hand-written post-laboratory
reports will also be rejected. The post-laboratory report must contain
the followings :
1. Cover page containing the name and student identication number;
2. Table of content;
3. List of gures and list of tables;
4. An introduction of the laboratory and your design approach (10%);
5. The main body of the report that details the laboratory work and
observations:
The schematic of the ampliers (10%);
The schematic of the test xture for testing the ampliers (10%);
Tabulate the dimension of the transistors of the ampliers (10%);
Tabulate the DC biasing conditions (V
GS
, V
DS
, and I
DS
) of the
transistors of the ampliers. Use pinch-o condition to verify that
the transistors are in saturation (10%);
DC analysis : Show the maximum input voltage (10%).
Frequency response (both magnitude and phase) of the ampliers.
Find the bandwidth and phase margin of the ampliers (10%);
Tabulate the voltage gain A
v
, the input resistance R
in
, and output
resistance R
out
of the ampliers at low frequencies. Calculate the
theoretical value of A
v
, R
in
, and R
out
using the dc biasing condi-
tion obtained earlier and compare the results with those obtained
from simulation (20%);
Analyze slew rate (10%).
Chapter 5
Laboratory Three :
Three-Stage Cascode Voltage
Amplier
5.1 Pre-Laboratory
Voltage ampliers are essential components of electronic systems. They have
found applications in virtually every electronic systems, such as lters, regu-
lators, function generators, instrumentation ampliers, analog-to-digital data
converters, signal conditioners, to name a few. The basic conguration of
voltage ampliers consists of three stages, namely, a dierential input stage
that has a large dierential input impedance and the ability to suppress
common-mode noise including the noise coupled from the power and sub-
strate rails, an amplication stage that provides a large voltage gain, and an
output stage that provides a low output impedance. In addition, a common-
mode feedback is required to stabilize the dc operating points of the ampli-
ers. To avoid oscillation and improve the phase margin, feedback is also
needed.
In this laboratory, you are required to design and analyze a three-stage
cascode dierential-input single-ended output voltage amplier with a sin-
34
CHAPTER 5. LABORATORYTHREE : THREE-STAGE CASCODE VOLTAGE AMPLIFIER35
gle supply voltage. There are many topologies at your disposal such as
regular cascode and folded cascode, you are free to choose any of them.
You are required to complete a pre-laboratory report prior to undertaking
laboratory work. Your pre-laboratory report must include the followings :
1. The complete schematic including biasing and common-mode feedback
of the amplier (20%).
2. Derive the common-mode voltage gain A
c
and that of the dierential-
mode voltage gain A
d
of the dierential stage at low frequencies. Derive
the expression of the common-mode rejection ratio at low frequencies
(40%).
3. Determine the common-mode input voltage range of the amplier (20%).
4. Derive the dierential voltage gain of the amplier with C
gd
and C
gs
considered (20%).
5.2 Laboratory Work
You need to complete the followings:
1. Create the schematic view and symbol view of the amplier.
2. Create a test xture for testing the amplier.
3. Perform DC sweeping of the input voltage to nd out the dynamic
range of the voltage amplier. Plot the output voltage versus the input
voltage.
4. Perform DC analysis to nd out the DC operating point of the tran-
sistors and record them.
5. Perform AC analysis to nd out the frequency response, phase response,
the dierential-mode input impedance, and the output impedance of
CHAPTER 5. LABORATORYTHREE : THREE-STAGE CASCODE VOLTAGE AMPLIFIER36
the voltage amplier. Record the gain, bandwidth, and phase margin
of the amplier.
6. Perform transient analysis to nd out the average slew rate of the
amplier.
7. Sweep the common-mode input voltage and record the output voltage.
This analysis allows you to determine the common-mode input voltage
range.
5.3 Post-Laboratory Report
The report must be prepared in either Microsoft Word, LaTeX, or other
text editors. The cover page must contain the title of the lab report, the
name and identication number of the student. All required gures must be
embedded in the main body of the report. Cadence print-outs attached
to the end of the report are not acceptable. Hand-written post-
laboratory reports will also be rejected. The post-laboratory report
must contain the followings :
1. Cover page containing the name and identication number of the stu-
dent.
2. Table of content of your report.
3. List of gures and list of tables.
4. An introduction of the laboratory and your design approach
5. The main body of the report that details the laboratory work and
observations:
The complete schematic of the amplier (10%).
Tabulate the dimension of all transistors (10%).
CHAPTER 5. LABORATORYTHREE : THREE-STAGE CASCODE VOLTAGE AMPLIFIER37
Frequency response (magnitude and phase) of the output voltage
of the amplier. Find the gain, bandwidth, and phase margin of
the amplier (20%).
Tabulate the DC operating points (V
GS
, V
DS
, and I
DS
) of all tran-
sistors (20%).
DC sweeping analysis results. Clearly state the dynamic range of
the voltage amplier (10%).
Transient analysis results. Clearly state the average slew rate of
the amplier (10%).
Tabulate the output voltage of the amplier when sweeping common-
mode input voltage. Determine the common-mode input voltage
range of the amplier (10%).
Chapter 6
Laboratory Four : Voltage
Comparator with Hysteresis
6.1 Pre-Laboratory
6.1.1 Background
Voltage comparators are the essential components of electronic systems.
They have found broad applications in relaxation oscillators, analog-to-digital
converters, and clock and data recovery circuits, to name a few. Dierential
voltage comparators are essentially dierential ampliers with a fast state
transition. Positive feedback is typically employed to achieve a fast state
transition. Comparators with hysteresis are desirable in applications where
the inputs of the comparators contains high-frequency disturbances, as shown
in Fig.6.1. Comparators with hysteresis are often called Smith triggers, in
attribution to American scientist Otto Herbert Schmitt (1913-1998) [1]. The
original idea of Schmitt trigger was published a paper in Journal of Scientic
Instrument by Otto in 1938 when he was a only graduate student [2].
In this laboratory, you are required to design and analyze an Allstot
dierential-input single-ended output voltage comparator. Dr. Allstot is a
professor of University of Washington and a pioneer of many inventions in
38
CHAPTER 6. LABORATORYFOUR: VOLTAGE COMPARATOR WITH HYSTERESIS 39
v
i n
v
ref
v
in
(a) Without hysteresis
(b) With hysteresis
t
t t
t
v
o
v
o
Figure 6.1: Performance of comparators with and without hysteresis.
integrated circuits and systems.
6.1.2 Allstot Voltage Comparator
Perhaps the most widely used Schmitt trigger with hysteresis is the one
proposed by Allstot [3]. Fig.6.2 shows the simplied schematic of the com-
parator. All transistors are biased in the saturation.
Transistors M5 and M6 form a positive feedback to provide additional
paths to charge the output node. It can be shown that when the positive
feedback is absent, i.e. M5 and M6 are removed (in this case, the load of
M1 and M2 are diode-connected M3 and M4, which behave as resistors with
resistance 1/g
m3,4
), we have
v
+
in
= v

in
+

k
3,4
k
1,2
(v
+
o
v

o
), (6.1)
where k
1,2
=
1
2

n
C
ox

W
L

1,2
and k
3,4
=
1
2

p
C
ox

W
L

3,4
. Assume the state
CHAPTER 6. LABORATORYFOUR: VOLTAGE COMPARATOR WITH HYSTERESIS 40
M1 M2
M3 M4 M5
M7
M6
M8
M10 M9
v
o
vo- vo+
J
Figure 6.2: Comparator with hysteresis proposed by A. Allstot.
transition of the Schmitt trigger takes place when v
+
o
= v

o
. It is evident
from (6.1) that this will occur when v
+
in
= v

in
.
Now consider the case where the positive feedback is present. It can be
shown that
v
+
in
(V
ss
+ V
T
) +

k
3
k
1

V
DD
v

o
V
T

1 +
1
2
I
D6
I
D3

,
v

in
(V
ss
+ V
T
) +

k
4
k
2

V
DD
v

o
V
T

1 +
1
2
I
D5
I
D4

,
(6.2)
Note that we have assumed that
I
D6
I
D3
,
I
D5
I
D4
1 and utilized

1 + x1 +
1
2
x
in derivation of (6.2). It follows from (6.2) that
v
+
in
= v

in
+

k
3,4
k
1,2

v
+
o
v

+
I
D5,6
I
D3,4

k
3,4
k
1,2
(v
o
), (6.3)
where v
o
is the variation of the output voltage and is dened from v
+
o
=
v
o
+v
o
and v

o
= v
o
v
o
. A comparison of (6.1) and (6.3) reveals that the
switching point of the comparator has been shifted by the amount quantied
CHAPTER 6. LABORATORYFOUR: VOLTAGE COMPARATOR WITH HYSTERESIS 41
by the second term on the right hand side of (6.3). It also becomes apparent
that by varying the width of M5 and M6, which change I
D5
and I
D6
, the
switching voltages, i.e., the triggering voltage of the comparator, can be
adjusted.
6.1.3 Pre-Lab Requirements
In this laboratory, you are required to design and analyze an Allstot voltage
comparator with only one power supply. You are required to complete
a pre-laboratory report prior to undertaking any laboratory work. The pre-
laboratory report is due on Friday of the week before the start of the labo-
ratory. A 20% penalty will apply to a late pre-laboratory report.
Pre-laboratory reports can be prepared in either Microsoft Word, LaTeX, and
other text editors. Hand-written pre-laboratory reports are also acceptable.
Your pre-laboratory report must contain the followings :
1. A cover page containing the title of the report, the name and student
identication number.
2. The detailed derivation of the preceding expressions of the Allstot volt-
age comparator (100%).
6.2 Laboratory Work
You need to complete the followings:
1. Create the schematic view and symbol view of the comparator.
2. Create a test xture for testing the comparator.
3. Connect an ideal voltage source of 0.6 V to v
in
. Disable the positive
feedback by removing M5 and M6 (You do not need to remove the tran-
sistors. All you need to do is to cut wires connecting these transistors
CHAPTER 6. LABORATORYFOUR: VOLTAGE COMPARATOR WITH HYSTERESIS 42
to the output node. Warning messages will appear when recompiling.
Just ignore them as you know where they come from). Perform DC
sweeping of v
in
+ from 0 to 1.2V and from 1.2 to 0V to nd the trig-
gering voltages of the comparator. Plot the output voltage versus the
input voltage. Identify the triggering voltages in your plots.
4. Connect an ideal voltage source of 0.6 V to v
in
. Enable the positive
feedback by re-connecting M5 and M6 to the output nodes. Perform
DC sweeping of v
in
+ from 0 to 1.2 V and from 1.2 to 0V to nd the
triggering voltages of the comparator. Plot the output voltage versus
the input voltage. Identify the triggering voltages in your plots.
5. Repeat the last step by increasing and decreasing the width of M5 and
M6. This will change the strength of the positive feedback subsequently
the triggering voltages. Plot the output voltage versus the input voltage
for both cases.
6. Connect an ideal square-wave voltage source to v
in+
and keep the 0.6
V ideal voltage source connected to v
in
. The square-wave voltage
source should have voltage swing 0-1.2V and 50% duty cycle. You
can choose the oscillation period between kHz and MHz. Enable the
positive feedback by re-connecting M5 and M6 to the output nodes.
Perform transient analysis over several periods. Note that you should
choose more cycles and discard the initial few cycles, which correspond
to the initial conditions of your simulation. Plot the waveform of both
v
in+
and v
o
in the steady state. Identify the triggering voltages for
0-1.2V transitions and 1.2V-0 transitions.
6.3 Post-Laboratory Report
The report must be prepared in either Microsoft Word, LaTeX, or other text
editors. The cover page must contain the title of the lab report, the name and
identication number of the student. All required gures must be embedded
CHAPTER 6. LABORATORYFOUR: VOLTAGE COMPARATOR WITH HYSTERESIS 43
in the main body of the report. Hand-written post-laboratory reports
will be rejected. The post-laboratory report must contain the followings :
1. Cover page containing the name and identication number of the stu-
dent.
2. Table of content of your report.
3. List of gures and list of tables.
4. An introduction of the laboratory and your design approach
5. The main body of the report that details the laboratory work and
observation
The schematic of the voltage comparator (10%).
Tabulate the dimension of all transistors (10%).
Simulated voltage transfer characteristic with v
in
= 0.6 V when
the positive feedback is removed (20%).
Simulated voltage transfer characteristic with v
in
= 0.6 V when
the positive feedback is enabled (20%).
Simulated voltage transfer characteristic with v
in
= 0.6 V when
the positive feedback is enabled and the width of M5 and that of
M6 are increased and decreased (20%).
Simulated transient response of the output voltage with v
in
= 0.6
V when the positive feedback is enabled (20%).
Bibliography
[1] J. Harkness, An idea man, IEEE Engineering in Medicine and Biology
Maganize, pp.20-41, Nov./Dec. 2004.
[2] O. Schmitt, A thermionic trigger, J. Scientic Instruments, vol.15,
pp. 24-26, Jan. 1938.
[3] A. Allstot, A precision variable-supply CMOS comparator, IEEE J.
Solid-State Circuits, Vol. 17, No. 6, pp. 1080-1087, Dec. 1982.
44
Chapter 7
Laboratory Five : Voltage
References
7.1 Pre-Laboratory
Voltage or current references are a critical component of electronic systems.
The performance of voltage references is primarily measured by voltage coef-
cient (V
o
/V
DD
) dened as the ratio of the change of the output voltage
to that of the supply voltage and temperature coecient (V
o
/T) dened as
the ratio of the change of the output voltage to that of the supply voltage.
In this laboratory, you are required to design and analyze a voltage reference
with only one power supply.
You are required to complete a pre-laboratory report prior to undertak-
ing any laboratory work. The pre-laboratory report is due on Friday of the
week before the start of the laboratory. A 20% penalty will apply to a late
pre-laboratory report.
Pre-laboratory reports can be prepared in either Microsoft Word, LaTeX, and
other text editors. Hand-written pre-laboratory reports are also acceptable.
Your pre-laboratory report must contain the followings :
45
CHAPTER 7. LABORATORY FIVE : VOLTAGE REFERENCES 46
1. A cover page containing the title of the report, the name and student
identication number.
2. The schematic of the voltage reference (30%).
3. Derive the expression of the output voltage of the voltage reference.
Find the condition upon which the output voltage is independent of
temperature (70%).
7.2 Laboratory Work
1. Create the schematic view and symbol view of the voltage reference.
2. Create a test xture for testing the voltage reference.
3. Record V
GS
, V
DS
, and I
DS
of all transistors. Use pinch-o condition to
determine the mode of the operation of the transistors (Saturation or
triode).
4. Sweep the supply voltage from 80% to 120% of the nominal value with
10 steps. Record the output voltage of the voltage reference.
5. Sweep the temperature from -20C to 80C with 10 steps while keeping
V
DD
= 1.2 V. Record the output voltage of the voltage reference.
7.3 Post-Laboratory Report
The post-laboratory report must be prepared in either Microsoft Word, La-
TeX, or other text editors. Figures, tables, and expressions should be em-
bedded in the main body of the report. Hand-written post-laboratory
reports will be rejected. The post-laboratory report must contain the
followings :
1. Cover page containing the name and student identication number;
CHAPTER 7. LABORATORY FIVE : VOLTAGE REFERENCES 47
2. Table of content of the report;
3. List of gures and list of tables,
4. An introduction of the laboratory and your design approach (10%);
5. The main body of the report that details the laboratory work and
observation:
The schematic of the voltage reference (10%);
The schematic of the test xture for testing the voltage reference
(10%);
Tabulate the dimension of the transistors of the voltage reference
(10%);
Tabulate the DC biasing conditions (V
GS
, V
DS
, and I
DS
) of the
transistors of the voltage reference. Use pinch-o condition to nd
out the mode of operation of each transistor (saturation or triode)
(20%);
Tabulate the output voltage versus supply voltage. Find supply
voltage coecient (V
o
/V
DD
).
Tabulate the output voltage versus temperature. Find tempera-
ture coecient (V
o
/T).