Atari TT030 Computer Field Service Manual Part Number: ©302483-001 REVBSECTION ONE INTRODUCTION 1.1 OVERVIEW The Atari® TTO30™ is designed as an integrated unit wt processos, memory, and /O control in one package. ‘The 'T'T030 provides 2 Mbytes (2,097,142 bytes) of RAM memory and. is expandable to 26 Mbytes (27,262,846 bytes) by installing daughter boards, The T'T930 also rovides 512 Kbytes (524,288 bytes} of ROM space. A 720 Kbyte or Ltd Mbyte formatted) lappy. power supply, and lating point coprozesor are ls included inthe system. An optional hard disk drive can also be added. 1.2 MAIN COMPONENTS © Main Board + Separate Keyboard Assembly over Supply Floppy Disk Drive Plastic Case {upper and lowes) Mouse 1.3 CASE DESIGN ‘The front of the TTO30 contains the floppy disk deive with an eject burton and busy LED, An optional hard disk can also be installed and it also contains its own busy LED, Optional Hard Diske Power Floppy Floppy Eject Hard Disk TED Nameplate Acthity ston Actity LED LED Front ViewThee se of uae TO3O cate comuns the following ives fzom left to rg Reset button, LAN connector, MIDI QUT jack, MIDI IN jack, ROM cartridge port, and keyboaed jack, Reset LAN V4 \ MIDI IN ROM Cartridgr MIDI OUT Left Side View The rear of the TTO30 contains the following items. SCSI interface jack, External floppy jack, external ACSI interface connector, printer connector, monitor jack, VME slot, modem | connector, on/off switch, power plug, modem 2 connector, fan, audio R connector, and audio L connector, On/Off Switch VME AC Power In I a | PN Audio Audio SCSI Floppy ACST Printer Modem 2 Modem1 Right Left Monitor Rear View1.4 POWER SUPPLY 1.4.1 Power Supply Rating ‘The T7030 has an integral switching power supply providing 64 watts of power. The suppl can accept AC input of 10O-24GVAC at 2A, S0/60K 2, The power supply provides the following voltages and currents to the system: Voltage Current +5V 7A +12V 2A Sv OA “2V O38SECTION TWO THEORY OF OPERATION 2.1 OVERVIEW The, O30 isa new series of tar computers designed as an enhanced version of the Atari ST™ and Megar architecture. The TT030 uses the Motorolar 68030 microprocessor running, 4¢32 Mitr which provides enhanced graphics and sound capabilities. VME bus hasbeen included in the T'T030 for expansion, ‘The hardwaze is composed of a main system (central processing unit and support chips), audio/video subsystem, and several 1/O subsystems, Main System mcesox0 processor running at 32 MHz MC68882" coprocessor 512 Kbytes of ROM 2 Mbytes of RAM (expandable to 26 Mbytes) Intermupt mask, status, and control System tinaing and Bus control MA. support © Battery backed-up Real-time clock I/O Subsystems SCSI interface ST compatible ACSI interface Floppy disk interface Four serial ports LAN port Parallel printer interface Intelligent keyboard interface Mouse and Joystick interface Musical Instrument Digital Interface (MIDI) VME SlotAudio/Video Subsystem Bit Mapped video display using 32 Kbytes in ST mode and 153.6 Kbytes in TT mode of RAM. relocatable anywhere in-memory. * Six available display modes: ST Mode: 320 X 200 16 out of 4096 colors G40 X 200 4 out of 4096 colors G40 X 400 monochrome TT Mode: 320 X 200 16 out of 409% colors 640 X 200 4 out of 4096 colors 640 X 400 2 out of 4096 colors 640 X 480 16 out of 4096 colors 1280 X 960 monochrome 320 X 480 256 out of 4096 colors * Monitor interfaces include: RGB ECL Monochrome * Audio outputs internally mixed together: Programmable sound generator Stereo DMA sound. 2.2 MAIN SYSTEM ‘The hardware contained in the main system of the Atari TT030 are the processor, optional coprocessor, ROM, RAM, Laternupt control (SCU and MEP), Memory, Timing and Bus control (MCU), DMA support DMAC), and Reaktime clock (MC14G818). 2.2.1 Processor The processor used in the Atari TT030 system is a 32 MHz Motorolar MC68030r with a 32- bit internal architecture, 52-bit external data bus, and a 32-bit address bus, ‘This single chip contains a 68020 superset processor, a paged memory management unit, and independent data nd instruction caches, The processor s locked at 32 MILs2.2.2 Coprocessor The TT030 provides a Motorolar high performance MC68882 floating point coprocessor. The MC68882 coprocessor is clocked at 32 MHz. The processor recognizes the coprocessor as the standard floating point coprocessor ID of | in the 68030 CPU address space. 2.2.3 ROM ‘The system contains four 1 Mbit ROMs for a total of 512 Kbyte of access space. Since system ts acres is 32-bits wide, all four ROMs must be present for proper operation, Included in thet the ROM performs is system initialization and boot code. The ROM also contains the TOS operating system. 2.2.4 RAM ‘The T'/030 includes 2 Mbytes of RAM used for both system and video, The RAM is implemented with 16 256 Kbit X 4 100 ns DRAMs set up to yield a 64-bit wide internal bus for high performance video access. Memozy accesses to the RAM are intesleaved hetween the Memory Controller and the Video Controller in 250ns time slices. During display cycles the processor is prevented from accessing the RAM. However, the processor wl be allotted the next 250ns time slice. ‘The processor accesses the RAM through a 32-bit bus, even though the video system accesses the bus through a 6-bie wide architecture. The TT video chip (T'T'VIDEO) has on-chip buffering co provide very high bus bandwidths.Additional memory can be installed in the system via dual purpose ST RAM daughter boards, single purpose ‘TT RAM daughter boards, or YME memory cards, 4 or 16 Mbytes of additional 32-bit wide TT RAM can be installed, or 2.or 8 Mbytes of dual purpose 64-bit wide ST RAM can be installed. Additional memory can abo be installed in the system by plugging ia VME memozy cards. Either A24/D16 or A16/D16 cards can be used, however VME memory will typically run slower than on-board. system memory due to the fact that all accesses incur an additional wait state. Memory in the 1030s overlapped and xldressd in a unique fashion. When expansion RAM is ade tothe system the lower addrssep ae movadto an upper memory mapping scheme and the expansion RAM takes over the lower addzesses. Refer to the map on the following page for details.RAM memory map: Base System Address Function. cg008- 090800 System memory (privileged access) 000800-1FFFFF First 2 Mbytes 4 Megabyte system Address Function AFFFFF - 3FFFFF Expansion 2 Mbytes 800000 - 9FFEFF = Main Board 2 Mbytes 16 Megabyte system Address Function 000000 - 7EFFFF Expansion board 8 Megabytes 800000" SEEFEP Main board 2 megabytes * 2.2.5 System Control Unit (SCU) ‘The SCU provides several system support functions including interrupt masking and status reporting, interrupt generation, and bus time-out detection. 1 Interrupt Mask and Current Status ‘The SCU contains two registers used 10 mask interrupts to she processors, These register, in effect, screen the interrupts from both main system devices and VME bus devices and present them, when enabled (not masked), to the processor. Masked interrupts (not enabled) are not presented and therefore not seen by the processor. These registers are cleared at power up or reset, disabling all intecrupts. The SCU also contains a register which latches the curzent state of the seven intersupt request levels from each one of the sources. This register shows the state of the interrupt lines before they are ANDed with the mask registers.2.2.5.2 Interrupt Generation ‘The system can wate to an 1/0 ake to generate a level {autovectorad interape tothe processor, The SCU is hardwired to the following interrupt scheme: * Only intersupt levels 5 and 6 have external interrupt acknowledge (ACK) pins and are capable of genesating vectored interrupts to the system, © SCU generated interrupts IRQ1 and IRQ3 are hardwired to the corzesponding priorities and are always autovectored. * The VMEbus ACFAIL generates an IRQ7 interrupt to the processor. The only other source of IRQ7 interrupt is from a VMEbus eard. 2.2.5.3 Bus Timer ‘The SCU implements a bus timer so chat if a bus cycle is not terminated within I6us, the SCU vwill generate a bus e:ror signal. 2.2.6 68901 MFPs 2.2.6.1 MFP Interrupt Control ‘Tsvo 68901 MFPs are included in the TT030 system. Each 68901 MEP handles up to 16 interzupts. Currently all but one aze used. Exch interrupt can be masked off or disabled by: programming the MEP. The intercupts controlled by the MFP are: monochrome monitor detect (XMONO), RS-332 (Including CTS, DCD, and RD), floppy and hard disk (PDINT and SEIDINT sespectively) parallel port BUSY display enable (DE, which equals the sat ofthe splay line), 6850 IRC) for keyboard and MIDI data, and MEP timers. Interrupts received by the MFPs are then sent on to the SCU for further masking. Not all 1/0 operations are interrupts. The CPU can also poll the MFP while waiting for an operation to complete, The MEP also contains four timers. These are used by the Operating System for event timing, R252 port for transmit and receive clocks, an by application software.