Electronics

Journal

I C D A

E C H N O L O G Y

The War on Noise

New tools are needed to attack the noise problem in deep-submicron design
by
Robert
Patton

hough noise has posed a

problem for analog circuit designers ever since
the early days of crystal radios,
designers of digital integrated circuits have never had to worry
until now. One big advantage of
digital circuits, after all, is a high
degree of noise immunity. Not
only has that changed, but the
problem of noise has assumed
such importance that some industry experts believe that electrical
effects such as noise, not the limits
of optical lithography, will pose
the earliest threat to continued
growth in circuit density and
performance.
Ken Shepard, who has a foot
on each coast as both an assistant
professor in the EE department
of New Yorks Columbia University and the chief technology
officer of CadMOS Design Technology in San Jose, is working to
solve that problem. Digital circuits are very noisy, he says,
because, within the chip, certain
voltage values are going from high
to lowfrom Vdd to ground
then switching back up again,
from ground to Vdd.
Until recently the noise
immunity [of digital circuits] has
been more than enough to over-

come the noisiness and the only

designers who had a problem
[with digital noise] were those
who tried to mix digital and analog, who took the noisy digital
environment and inserted very
noise-sensitive analog circuits.
Now, with technology scaling,
with the jamming together of
interconnect wires, with the scaling of threshold voltages, with the
more aggressive use of circuits
that are more noise sensitive to
gain performance advantages,
the noise immunity of digital
circuits is no longer sufficient to
protect them against their [own]
inherent noisiness.

Noisy Neighbors
Noise has become a problem
because as design rules reach the
0.25-m level and below, interconnect is becoming an increasingly dominant factor in design.
Technology scaling has caused
coupling capacitance between
on-chip signals to become a larger
and larger fraction of total capacitance. At the same time, because
transistors are shrinking and the
number of long interconnects are
increasing, the amount of interconnect-related capacitance is
becoming much larger and more

In the latest submicron designs, both line width and line

spacing are less than line thickness, and are even less than the
separation between lines on different layers. As a result, lineto-line capacitance on the same layer has become dominant.

14 EJ

October 1998

significant than the amount of

capacitance in gates.
As circuit densities continue
to increase, interconnect capacitance will continue to be a growing fraction of the total capacitance of advanced devices. More
and more, the improbable and
unanticipated has become an
everyday and expected part of the
design job. Problems once associated only with interconnections
between devices on a board are
now invading chips themselves.
And the microscopic metallic
slivers that interconnect devices
on the chip are now, almost
unbelievably, behaving like
transmission lines.
John MacDonald, a staff engineer working on UltraSPARC
development at Sun Microsystems, Inc. of Palo Alto, CA, points
to the dramatic change that has
occurred in the way metal lines
behave. If you backed up a couple of generations, he explains,
and took a cross-section of the
metal layer, you would find that a
metal line was wider than it was
thick. And the typical separation
between different metal layers was
less than the width of a metal line.
So most of the capacitance was
between metal layers. Since then,
he continues, lateral dimensions
have scaled more rapidly than
vertical dimensions. So now if you
take a cross-section, the metal
lines look more like two-by-fours
standing on edge.
MacDonalds graphic metaphor emphasizes the dramatic
change in circuit aspect ratio
the shrinking width of interconnects with respect to height. In

Figure 1
Charge Sharing
Static Logic Gate
C1
B1

B2

A1

A2

A1
B1
C1

O1
A1

addition to this, lines are also

much closer together. In the latest
submicron designs, both line
width and line spacing are less
than line thickness, and are even
less than the separation between
lines on different layers. As a
result, line-to-line capacitance
on the same layer has become
dominant.
When layer-to-layer capacitance was the dominant factor,
signals would rarely interact in a
way that induced current into a
metal line. But now that line-toline capacitance is greater, it is
common to find problems created
by unwanted coupling between
individual signals where one line
acts as an aggressor, inducing
enough current into an adjacent
victim line to cause a functional
failure by destroying logical information and causing a latch to
store an incorrect machine state.
One way to decrease line-to-line
coupling is to increase spacing.
Another is to reduce the crosstalk
capacitance between wires by
altering the routing pattern. A
longer-term solution might use
lower-dielectric-constant materials between troublesome lines.
This kind of coupling-induced
noise problem is probably the
most significant noise issue in
deep-submicron design, but it is
not the only one. Noise can also
affect switching circuits by altering delay and causing timing
inaccuracy. If an aggressor line
induces current into a victim
while the victim line is changing
states, the extra current can help
or hinder the change, thus altering the timing. This introduces
an unexpected parameter.

Instead of the delay and timing

depending only on load, drive,
and the characteristics of the
interconnect, designers must
now concern themselves with
what is happening elsewhere in
the neighborhood.

B1

O2

C1
O1
O2

n1
A2

B2

Charge sharing between

nodes O1 and n1 in the
presence of other noise
sources can lead to
functional failures at a
downstream latch
CLK

CLK

Turning Down the Volume

Any solution to these problems
must deal with noise from a
number of sources. In addition
to noise coupled between metal
lines on the interconnect, noise
can move from a switching line
to a static one, or even originate
in the power supply. From a tool
perspective, says Shepard, the
problem is to verify functionality
in the presence of the noise. He
cites two basic approaches.
The first, he explains, is rulebased. You set up rules in your
design. Rules about data ratios,
circuit rules, rules about interconnects. You come up with a set
of rules which, if followed, will
hopefully avoid a problem.
But Shepard sees major drawbacks to rule-based approaches.
No rule set is likely to cover all
cases and catch everything. Even if
it could, the rule-based approach
is inherently conservative. Noise,
he argues, is always trading off
against performance, against area,
against power. Whenever you try
to get more noise immunity in
your design, it always costs something. If not performance, then
area, or power, or something. Its
never free. Building more noise
immunity into designs through
conservative rules, he concludes,
is inevitably going to hamstring
your ability to optimize other
metrics in the design.

S1

S2

S3

S4

D1

D2

D3

D4

L
CLK

CLK

Dynamic Logic Gate

CLK

Charge-sharing
noise at node D
causes node L
to change state

S1, S2, S3, S4

D
O
CLK
L

Capacitive coupling and charge sharing can move

a gate voltage beyond a threshold, causing that
gate to make and unwanted transition. (Source:
CadMOS)

The second approach, which

goes beyond rule checking, is to
do static noise analysis. Static
noise analysis is to noise what
static timing analysis is to timing.
Static noise analysis asks whether
a design will function in the
presence of noise. It actually calculates the noise appearing on
every net and, in the worst-case
scenario, how much noise can
appear on the net. At the same
time it evaluates the noise immunity of every net, flagging those
places where there are potential
failures. Static noise analysis
involves looking at the circuits,

October 1998

EJ 15

I C D A

E C H N O L O G Y

looking at the interconnects, and

analyzing the [entire] design
with much the same sort of rigor
applied to static timing analysis.
This technique underlies the
tools now under development at
CadMOS, which was co-founded
by Shepard. The fledgling company, which launched last summer and only formally announced
its formation in May of this year,
is now building both its initial
product line and marketing
strategy solely on its approach to
solving the growing problem of
combating noise effects in the
design of advanced circuits.
Although CadMOS has not yet
Figure 2
Changes in Supply and Ground
DC IR Drop (Voltage Drop)
Variations in the DC power supply levels on-chip due to
IR drops in the power/ground distribution
Delta-I Noise (Ground Bounce)
The simultaneous switching of off-chip drivers and internal
circuits causes periodic variations in the supply and ground
rails due to inductance on the chip and package supply and
ground wires
Package

On Chip
Vdd

Package
Decoupling
Capacitance

Switching
Circuits

Decoupling
Capacitance

Gnd

The static voltage drop across package and chip

resistance reduces the supply voltage available to
the circuitry. The change in ground reference due to
changes in ground current further reduces the voltage
available to the circuit. (Source: CadMOS)

16 EJ

October 1998

O N T I N U E D

released a commercial product, it

is now beta testing its first design
tool, PacifIC, a static noise analyzer for large digital ICs.

Noise at the Head Office

The noise problem is particularly
vexing to designers of advanced
microprocessors, because they are,
by necessity, the first to break new
ground and because the standard
tools developed by the EDA industry are, for economic reasons,
aimed at the largest marketsthe
designers of application-specific
devices. Meanwhile, at companies
like Sun, Compaq, Motorola, IBM,
and, of course, Intel, designing
in-house tools to meet the challenge of noise in next-generation
microprocessors is as important
as designing the chips themselves.
At Houston, TX-based Compaq Computer Corp.s recently
acquired Alpha Engineering
Group, Chris Houghton is a frontline soldier in the battle against
noise in deep-submicron designs.
A recent Alpha microprocessor
design, says Houghton, had over
15 million transistors with millions of signal nets to verify. Timing and coupling verification was
a monumental effort for this
device. This process directly
accounted only for parasitic resistance and capacitance, but not
high-frequency effects (HFEs).
The Alpha design team, while
recognizing that these effects
which include the inductance
and resistance in a signal/signalreturn loopcan be a problem,
did not make quantifying HFEs
a part of the verification process.

Indeed, the sheer size of these

problems hampers designers in
their efforts to obtain accurate
noise analyses. The Alpha group
uses a plethora of tools, some of
which do very large scale simulations that do not necessarily provide definitive answers, while
other, more accurate tools perform smaller-scale simulations.
Still other tools work for structures that are most easily represented in two dimensions, while
much slower and more cumbersome tools handle structures
that must be represented in three
dimensions.
At Sun, John MacDonald is
attacking the noise problem
largely with tools and methods
developed in-house. The objective, says MacDonald, is to
reduce the [degree of] coupling
between signals with respect to
the overall capacitanceincrease
the space between lines, put in
shielding, make sure a lines
neighbor is stable and isnt going
to switch and induce current
through the coupling capacitance.
One approach is minimizing the
range of rise and fall times that
occur in the design so that you
dont have some that switch fast
and some that switch slow. You
try to keep all the transition
timesthe rise and fall times
within certain bounds.
But applying such constraints
does not necessarily involve significant tradeoffs. In high-performance design, MacDonald
argues, if you design things
well, the rise and fall times tend
to be all about the same anyway.
Rather than paying a price, he
emphasizes, good designs will

Figure 3
Noise Reduction
Static Logic Gate
Disallows single
NFET or PFET pass
gates because of
Vt voltage drop

C1

minimize noise while improving

performance. Large variations in
rise and fall times that can cause
problems arise generally in lessthan-optimum designs. If youre
minimizing noise problems, he
says, youre generally also helping performance.
Another method is to put in
repeaters or insert a CMOS gate
with a single input and no logic
function as a buffer somewhere
along the line, to divide it up into
two nets. Here, MacDonald concedes, there is a price to pay in
terms of lost area, but, by using
these strategies judiciously on
lines that are particularly sensitive, designers can solve noise
problems at reasonable cost.
Sun Microsystems, he says,
primarily uses [CAD] tools that
have been developed in-house,
but not by preference. Internal
tool development is the price for
being on the cutting edge of technology. People designing highperformance microprocessors,
says MacDonald, tend to run into
problems before the EDA industry is ready to address them. We
tend to push the edge of what we
can do. We may be working one
technology ahead of what the
ASIC designer does.

Any Port in a Thunderstorm

The tools developed on an ad hoc
basis by microprocessor design
teams may do the job, but they
offer little to other deep-submicron designers as a general solution to the noise problem. Our
in-house solutions, says MacDonald, are very highly integrated into our [unique] design
methodologies, and that just

doesnt translate very well. Were

not in the tool business and we
dont do a great job of building
tools. Often, he quips, were
happy to put something together
with bailing wire and chewing
gum as long as it helps us get the
chip out.
MacDonald believes that the
industry has, so far, made more
progress identifying these problems than solving them. People
are just starting to put together
verification tools that can look
for potential noise problems in
each net in a designtools that
can verify every interconnect.
These tools, often cobbled
together by microprocessor design
teams, dont meet ASIC needs for
a number of reasons. For one
thing, the modeling primitive is
different. Where the microprocessor design and analysis paradigm
is transistor-based analysis, ASIC
design is gate-based. For ASIC
designers, the problem promises
to grow more acute. Where microprocessor designers have the relative luxury of working on next
years advanced devices, the ASIC
world needs to turn things around
in a matter of months or less.
The EDA industry is just
beginning to come to grips with
the noise problem. At least half a
dozen companies are working to
develop the new physical design
tools that will determine the performance of tomorrows chips.
The new breed of tools must
include powerful electrical analysis capabilitiesif not to overcome, then to at least postpone
the barrier presented by noise.
Its not yet clear how the EDA
industry and the designers of

Beta noise
can be tuned
to trade off
one noise
margin against
the other

B1

B2

A1

A2
O1

A1

B1

A2

B2

Weaken devices to
reduce charge sharing

Dynamic Logic Gate

Increase size of
feedback device
A2
A1

Tune up length to
reduce noise due
to leakage current

B1

O2

C1

C1

A2
B2
Add baby-sit device
to reduce charge sharing

The effects of charge sharing can be reduced by

changes in circuit topologies. (Source: CadMOS)

advanced devices will meet the

challenge of noise in the future.
Will large EDA firms eventually
develop highly automated tools
that reduce the problem to a more
manageable scale, or will smaller
start-ups break the new ground?
Will microprocessor designers
eventually possess fully-automated
noise analysis tools or will they
continue to outrun progress in
tool development? What is certain
is that noise will not go away, the
problem will expand as circuit
elements shrink in size, and the
need for better and better noise
analysis tools and methodologies
will remain.

Robert Patton is a freelance

technology writer in Newport,
VT.

October 1998

EJ 17