B.

TECH IT
SECOND SEMESTER
IT6211 DIGITAL LABORATORY
LAB MANUAL
REGULATION 2013

[Type the abstract of the document here. The abstract is typically a short summary of the contents of the
document. Type the abstract of the document here. The abstract is typically a short summary of the
contents of the document.]

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EXPT NO.
DATE:

: 1A

STUDY OF BASIC DIGITAL ICS

AIM:
To verify the truth table of basic digital ICs of AND, OR, NOT, NAND, NOR, EX-OR
gates.
APPARATUS REQUIRED:
Sl.No.

COMPONENT

SPECIFICATION

QTY.

AND GATE

IC 7408

OR GATE

IC 7432

NOT GATE

IC 7404

NAND GATE

IC 7400

NOR GATE

IC 7402

X-OR GATE

IC 7486

IC TRAINER KIT

PATCH CORDS & WIRES

As needed

THEORY:
Logic gates are the basic elements that make up a digital system.The electronic gate is a
circuit that is able to operate on a number of binary inputs in order to perform a particular logic
function.The type of gates available are the NOT,AND,OR,NAND,NOR,Exclusive-OR and the
Exclusive-NOR.
1.AND gate:
An AND gate is the physical realization of logical multiplication operation. It is an
electronic circuit which generates an output signal of 1 only if all the input signals are 1.
2.OR gate:
An OR gate is the physical realization of the logical addition operation. It is an electronic
circuit which generates an output signal of 1 if any of the input signal is 1.
3.NOT gate:
A NOT gate is the physical realization of the complementation operation. It is an electronic
circuit which generates an output signal which is the reverse of the input signal. A NOT gate is also
known as an inverter because it inverts the input.
4.NAND gate:
A NAND gate is a complemented AND gate. The output of the NAND gate will be 0 if all the
input signals are 1 and will be 1 if any one of the input signal is 0.
5.NOR gate:

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A NOR gate is a complemented OR gate. The output of the OR gate will be 1 if all the inputs are
0 and will be 0 if any one of the input signal is 1.
6.EX-OR gate:
An Ex-OR gate performs the following Boolean function,
A
B = ( A . B ) + ( A . B )
It is similar to OR gate but excludes the combination of both A and B being equal to one. The
exclusive OR is a function that give an output signal 0 when the two input signals are equal either
0 or 1

AND GATE
LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7408:

TRUTH TABLE
INPUT

S.No

A
0
0
1
1

1.
2.
3.
4.

OUTPUT
B
0
1
0
1

Y=A.B
0
0
0
1

OR GATE:
LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7432 :

TRUTH TABLE

S.No
1.
2.
3.
4.

INPUT
A
0
0
1
1

OUTPUT
B
0
1
0
1

Y=A+B
0
1
1
1

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NOT GATE
LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7404 :

TRUTH TABLE:

S.No
1.
2.

INPUT
A
0
1

OUTPUT
Y = A
1
0

NAND GATE
LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7400:

TRUTH TABLE
S.No
1.
2.
3.
4.

NOR GATE:
LOGIC DIAGRAM:

INPUT
A
0
0
1
1

B
0
1
0
1

OUTPUT
Y = (A . B)
1
1
1
0

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PIN DIAGRAM OF IC 7402

TRUTH TABLE
INPUT

S.No

A
0
0
1
1

1.
2.
3.
4.

B
0
1
0
1

OUTPUT
Y = (A + B)
1
0
0
0

EX-OR GATE:
LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7486 :

TRUTH TABLE
S.No
1.
2.
3.
4.

INPUT
A
0
0
1
1

B
0
1
0
1

PROCEDURE:
1. Connections are given as per the circuit diagram
2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.
3. Apply the inputs and verify the truth table for all gates.

RESULT:

OUTPUT
Y=A
B
0
1
1
0

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EXP. NO : 1 B
DATE

VERIFICATION OF BOOLEAN THEOREMS & LAWS

Aim:
To verify the truth tables of DeMorgan's theorem and Boolean algebraic laws by using logic
gates.
Apparatus Required:
S.NO
1

COMPONENTS
Digital IC trainer kit

IC

Patch Cords & Wires

SPECIFICATION
7400
7402
7404
7408
7432
7486
-

QUANTITY
1
1
1
1
1
1
1
As required

Theory:
DeMeorgans Theorems
First Theorem:
It states that the complement of a product is equal to the sum of the complements.
(AB) ' =A' + B'
Second Theorem:
It states that the complement of a sum is equal to the product of the complements.
(A+B)' =A' . B'
Boolean Laws:
Boolean algebra is a mathematical system consisting of a set of two or more distinct
elements, two binary operators denoted by the symbols (+) and (.) and one unary operator denoted
by the symbol either bar (-) or prime (). They satisfy the commutative, associative, distributive and
absorption properties of the Boolean algebra.
Commutative Property:
Boolean addition is commutative, given by
A+B=B+A
Boolean algebra is also commutative over multiplication, given by
A.B=B.A

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De-Morgans Theorem: 1

Truth Table

Input

Output

(A+B) '

A '. B '

De-Morgans Theorem: 2

Input

Output

(A.B) '

A'+B'

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Associative Property:
The associative property of addition is given by
A+ (B+C) = (A+B) +C
The associative law of multiplication is given by
A. (B.C) = (A.B).C
Distributive Property:
The Boolean addition is distributive over Boolean multiplication, given by
A+BC = (A+B) (A+C)
Boolean multiplication is also distributive over Boolean addition given by
A. (B+C) = A.B+A.C
Procedure:
1. Connections are made as per the circuit/logic diagram.
2. Make sure that the ICs are enabled by giving the suitable V cc and ground connections.
3. Apply the logic inputs to the appropriate terminals of the ICs.
4. Observe the logic output for the inputs applied.
5. Verify the observed logic output with the verification/truth table given.

Commutative Law:

Truth Table:
Input

Output

A+B

B+A

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Associative Law:

Truth Table:

Input

Output

A+B

(A+B)+C

B+C

A+(B+C)

Distributive Law:

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Truth Table:

Input

Output

B+C

A.(B+C)

A.B

A.C

A.B+A.C

Result :

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Ex.No:2 a.
Date:

IMPLEMENTATION OF BOOLEAN FUNCTION

Aim :
To realize the given Boolean functions using NAND and NOR gates
Apparatus required :
SI.No.

COMPONENT

SPECIFICATION

QTY.

AND GATE

IC 7408

NAND GATE

IC 7400

NOR GATE

IC 7402

3 input NAND GATE

IC 7410

IC TRAINER KIT

PATCH CORDS& Wires

As needed

Theory :
A Boolean function described by an algebraic expression consists of binary variables, the
constants 0 & 1, and the logic operation symbols. When a Boolean expression is implemented with
logic gates, each term requires a gate & each variable within the term designates an input to the
gate. The Boolean functions are expressed either in sum of product (SOP) form for NAND
implementation (or) product of sum (POS) form for NOR implementation. The given Boolean
function is minimized using K map.

Boolean function implementation :

a] Realize f (w, x, y, z) = (0, 1, 4, 5, 8, 9, 11) + d (2,10) using only NOR gate.
Truth table
Truth table
K map reduction
W
X Y Z

f= ( W+Y )( W+X )

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

F
0
0
d
1
0
0
1
1
0
0
d
0
1
1
1
1

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Minimized Truth table for the above function
WXY W+Y W+X ( W+Y )( W+X )
000

001

010

011

100

101

110

111

NOR gate implementation

f=
+
y
+
x
w
w

Logic diagram :

x
y
Fig.
2.1 12, 14, 15 ) using only NAND gates.
B] Realize f ( w, x, y, z ) = ( 3, 5, 6, 7, 8, 9, 10 ) +d(
4, 11,
TRUTH TABLE
W
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

Y
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

Z
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

F
0
0
0
1
d
1
1
1
1
1
1
d
d
0
d
d

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NAND gate implementation

3 input NAND IC 7410

f=
w
x
+
w
x
+
y
z
f=w
x
w
x
y
z

Procedure :
i. The connections are given as per fig 2.1, 2.2.
ii. For various combinations of inputs the outputs verified.

Viva question:
What is a combinational circuit
What is SOP & POS?

Result :
Thus the given functions are realized using NAND & NOR gates .

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Ex.No: 2 B.
DATE:

CODE CONVERTERS

AIM:
To design, construct and test the following code converters.
1. Binary Gray code converter (4 bit)
2. Gray - Binary code converter (4 bit)
3. Excess 3 to BCD code converter
APPARATUS REQUIRED:
Sl.No.

COMPONENT

SPECIFICATION

QTY.

AND GATE

IC 7408

OR GATE

IC 7432

NOT GATE

IC 7404

X-OR GATE

IC 7486

IC TRAINER KIT

PATCH CORDS & WIRES

As needed

THEORY:
Code converter is a circuit that makes two systems compatible even though each uses a
different code. In order that conversion from binary code to gray code & gray code to binary code, a
combinational circuit code converter can be implemented with gates.
Binary code has two elements 0 & 1 each bit of binary code has a weight of 2. Gray code
also has 0 & 1 as elements. But in this code there is no weight for bits.
Binary to Gray conversion:
The most significant bit w is obtained directly from binary code. The second bit x is
obtained by XORing a & b . Likewise all other bits are obtained in gray code by XORing the
corresponding & preceding bits of binary code.
Gray to binary conversion:
The MSB is obtained directly from the MSB and the other bits are obtained by XORing the
corresponding bit in gray code with preceding binary bit.
Example:

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Binary to Gray code converter:

A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Binary code
b
c
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1

d
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

W
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Gray Code
X
Y
0
0
0
0
0
1
0
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
0
1
0
1
0
0
0
0

Z
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0

Karnaugh map reduction:

The K-maps for W, X, Y, Z based on the truth table & the minimized expressions from them
are shown below.

W=a

X=a1b + a b1 = a b

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Y=bc1 + b1c = b c

Z=c1d + cd1 =c d

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CIRCUIT DIAGRAM:
Binary to gray code converters

Gray to Binary Code Converter:

Gray code
X
Y
0
0
0
0
0
1
0
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
0
1
0
1
0
0
0
0

W
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Z
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0

A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Binary Code
B
c
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1

D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

The K-maps for a, b, c & d based on the truth table & the minimized expressions from them are
shown below.

a=W

b=W1X +WX1 =W X

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c = W1XY1 +WX1Y1 +W1X1Y +WXY

= (W1X +WX1)Y1 + (W1X1 +WX)Y
=W X Y

d = W XYZ

CIRCUIT DIAGRAM
Gray to binary code converter

EXCESS-3 TO BCD CONVERTOR

TRUTH TABLE:
Excess 3 Input

BCD Output

X1

X2

X3

X4

0
0
0
0
0
1
1
1
1
1

0
1
1
1
1
0
0
0
0
1

1
0
0
1
1
0
0
1
1
0

1
0
1
0
1
0
1
0
1
0

0
0
0
0
0
0
0
0
1
1

0
0
0
0
1
1
1
1
0
0

0
0
1
1
0
0
1
1
0
0

0
1
0
1
0
1
0
1
0
1

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K-Map for A:

A = X1 X2 + X3 X4X1

K-Map for B:

K-Map for C:

K-Map for D:

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EXCESS-3 TO BCD CONVERTOR

PROCEDURE:
1. The connections were made as per the circuit diagram
2. The input with different combinations is given and its truth table is to be verified.

Viva Questions :
1. What is unit distance code
2. What are weighted & non weighted codes.
3. What is gray code.
4. What is BCD code
5. What is self complementing code

RESULT:

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EXPT NO.

: 3A

DATE

DESIGN OF ADDER AND SUBTRACTOR

AIM:
To design and construct half adder, full adder, half subtractor and full subtractor circuits
and verify the truth table using logic gates.

APPARATUS REQUIRED:
Sl.No.

COMPONENT

SPECIFICATION

QTY.

1.

AND GATE

IC 7408

2.

X-OR GATE

IC 7486

3.

NOT GATE

IC 7404

4.

OR GATE

IC 7432

5.

IC TRAINER KIT

6.

PATCH CORDS

As needed

THEORY:
HALF ADDER:
A half adder has two inputs for the two bits to be added and two outputs one from the
sum S and other from the carry c into the higher adder position. Above circuit is called as
a carry signal from the addition of the less significant bits sum from the X-OR Gate the carry
out from the AND gate.

FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it consists
of three inputs and two outputs. A full adder is useful to add three bits at a time but a half adder
cannot do so. In full adder sum output will be taken from X-OR Gate, carry output will be taken
from OR Gate.
HALF SUBTRACTOR:
The half subtractor is constructed using X-OR and AND Gate. The half subtractor has

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two input and two outputs. The outputs are difference and borrow. The difference can be applied
using X-OR Gate, borrow output can be implemented using an AND Gate and an inverter.

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FULL SUBTRACTOR:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor
the logic circuit should have three inputs and two outputs. The two half subtractor put together
gives a full subtractor .The first half subtractor will be C and A B. The output will be difference
output of full subtractor. The expression AB assembles the borrow output of the half subtractor
and the second term is the inverted difference output of first X-OR.
LOGIC DIAGRAM:
HALF ADDER

TRUTH TABLE:
A

CARRY

SUM

0
0
1
1

0
1
0
1

0
0
0
1

0
1
1
0

K-Map for SUM:

SUM = AB + AB

K-Map for CARRY:

CARRY = AB

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LOGIC DIAGRAM:
FULL ADDER
FULL ADDER USING TWO HALF ADDER

TRUTH TABLE:
A

CARRY

SUM

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
1
0
1
1
1

0
1
1
0
1
0
0
1

K-Map for SUM:

SUM = ABC + ABC + ABC + ABC

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K-Map for CARRY:

CARRY = AB + BC + AC

LOGIC DIAGRAM:
HALF SUBTRACTOR

TRUTH TABLE:
A

BORROW

DIFFERENCE

0
0
1
1

0
1
0
1

0
1
0
0

0
1
1
0

K-Map for DIFFERENCE:

DIFFERENCE = AB + AB

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K-Map for BORROW:

BORROW = AB
LOGIC DIAGRAM:
FULL SUBTRACTOR

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:

TRUTH TABLE:
A

BORROW

DIFFERENCE

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
1
1
0
0
0
1

0
1
1
0
1
0
0
1

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K-Map for Difference:

Difference = ABC + ABC + ABC + ABC

K-Map for Borrow:

Borrow = AB + BC + AC
PROCEEDURE:
(i)

Connections are given as per circuit diagram.

(ii)

Logical inputs are given as per circuit diagram.

(iii)

Observe the output and verify the truth table.

RESULT:

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EXPT NO.: 3 B
DATE :

DESIGN OF 4-BIT ADDER / SUBTRACTOR

AIM:
To design and implement 4-bit adder / subtractor using IC 7483.
APPARATUS REQUIRED:
Sl.No.

COMPONENT

SPECIFICATION

QTY.

1.

IC

IC 7483

2.

EX-OR GATE

IC 7486

3.

NOT GATE

IC 7404

4.

IC TRAINER KIT

5.

PATCH CORDS

As
needed

THEORY:
4 BIT BINARY ADDER:
A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adders connected in cascade, with the output carry from
each full adder connected to the input carry of next full adder in chain. The augends bits of A
and the addend bits of B are designated by subscript numbers from right to left, with subscript
0 denoting the least significant bits. The carries are connected in chain through the full adder.
The input carry to the adder is C0 and it ripples through the full adder to the output carry C4.

4 BIT BINARY SUBTRACTOR:

The circuit for subtracting A-B consists of an adder with inverters, placed between each
data input B and the corresponding input of full adder. The input carry C 0 must be equal to 1
when performing subtraction.

4 BIT BINARY ADDER/SUBTRACTOR:

The addition and subtraction operation can be combined into one circuit with one
common binary adder. The mode input M controls the operation. When M=0, the circuit is adder
circuit. When M=1, it becomes subtractor.

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PIN DIAGRAM FOR IC 7483:

LOGIC DIAGRAM:
4-BIT BINARY ADDER/SUBTRACTOR

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TRUTH TABLE:

Input Data A

Input Data B

Addition

A4 A3 A2 A1 B4 B3 B2 B1

Subtraction

S4 S3 S2 S1

D4 D3 D2

D1

Res
ult :

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Ex.No : 4
Date:

IMPLEMENTATION OF PARITY GENERATOR / CHECKER

AIM:
Design and implementation of Even and Odd Parity Generator/Checker using logic gates and MSI
device.
APPARATUS REQUIRED:
S.NO

COMPONENTS

Digital IC Trainer kit

IC

3
4

Connecting wires
Patch cords

CONFIGURATIO
N
7486
7404
74180
-

QUANTITY
1
1
1
1
As required
As required

Theory:
Parity generator:
A parity bit is a scheme of detecting error during transmitting of binary information. A parity
bit is an extra bit included with a binary message to make the number of 1s either odd or even.
Parity generators are used in digital transmission system for the errorless transmission of
digital data. A parity bit is added to the data before the transmission and it will be checked for the
correctness at the receiver end. There are two types of parity systems, even parity and odd parity. In
the even parity system if the number of 1s in the data word is odd, a 1 will be added as a parity bit
to the data to make total number of 1s even. If the number of 1s even, a 0 bit will be added. In the
odd parity system if the number of 1s in the data word is odd, a 0 will be added to make the
number of 1s odd. Otherwise, a 1 is added to make it odd. The circuit shown in the figure is used as
a parity generator as well as a checker. ABCD is the 4-bit data word. Pi and Po are the parity input
and parity output respectively.
The message, including the parity bit, is transmitted and then checked at the receiving end
for errors. An error detected if the checked parity does not correspond with the one transmitted. The
circuit that generates the parity bit in the transmitter is called a parity generator. The circuit that
checks the parity in the receiver is called parity checker. In even parity the added parity bit will
make the total number of 1s an even amount. In odd parity the added parity bit will make the total
number of 1s an odd amount.

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The working of the circuit can be concluded as follows,
Work as a Parity generator:
To generate an odd parity bit for ABCD, Pi must be made 0.
To generate an even parity bit for ABCD, Pi must be made1.
Work as a parity checker:
If the parity of ABCD Pi is odd, Po will be 0.
If the parity of ABCD Pi is even, Po will be 1.
Circuit Diagram:

EPB = D1D2D3D4

OPB = (D1D2D3D4)'

Truth Table (Even and odd parity generator):

D1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Data Inputs
D2
D3
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1

D4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Parity Bit
Even Odd
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1

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Circuit Diagram for Even Parity Checker:

PEC = ABCP
Truth Table for Even Parity Checker
4 BIT DATA RECEIVED
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

P
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

PARITY ERROR
CHECK
PEC
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0

Procedure:
Connections are made as per the circuit/logic diagram.
Make sure that the ICs are enabled by giving the suitable Vcc and ground
connections.
Apply the logic inputs to the appropriate terminals of the ICs.
Observe the logic output for the inputs applied.
Verify the observed logic output with the verification/truth table given.

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PIN DIAGRAM FOR IC 74180:

FUNCTION TABLE(Parity generator):

INPUTS
Number of High Data
PE
Inputs (I0 I7)
EVEN
1
ODD
1
EVEN
0
ODD
0

Result:

PO
0
0
1
1

OUTPUTS
O
E
0
1
0
1

1
0
1
0

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EX NO.: 5

DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR

DATE :
AIM:
To design and implement
(i)

2 bit magnitude comparator using basic gates.

(ii)

4 bit magnitude comparator using IC 7485.

APPARATUS REQUIRED:

Sl.No

COMPONENT

SPECIFICATION

QTY.

.
1.

AND GATE

IC 7408

2.

X-OR GATE

IC 7486

3.

OR GATE

IC 7432

4.

NOT GATE

IC 7404

5.

4-BIT MAGNITUDE

IC 7485

COMPARATOR
6.

IC TRAINER KIT

7.

PATCH CORDS & WIRES

As needed

THEORY:
The comparison of two numbers is an operator that determine one number is greater
than, less than (or) equal to the other number. A magnitude comparator is a combinational
circuit that compares two numbers A and B and determine their relative magnitude. The
outcome of the comparator is specified by three binary variables that indicate whether A>B, A=B
(or) A<B.
A = A3 A2 A1 A0
B = B3 B2 B1 B0
The equality of the two numbers and B is displayed in a combinational circuit designated
by the symbol (A=B).
This indicates A greater than B, then inspect the relative magnitude of pairs of significant
digits starting from most significant position. A is 0 and that of B is 0.
We have A<B, the sequential comparison can be expanded as

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(A>B) = A3B31 + X3A2B21 + X3X2A1B11 + X3X2X1A0B01
(A<B ) = A31B3 + X3A21B2 + X3X2A11B1 + X3X2X1A01B0
The same circuit can be used to compare the relative magnitude of two BCD digits.
Where, A = B is expanded as,
(A = B) = (A3 B3) ' (A2 B2) ' (A1 B1) ' (A0 B0) '

LOGIC DIAGRAM:
2 BIT MAGNITUDE COMPARATOR

K MAP

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TRUTH TABLE

Inputs

Outputs

A1

A0

B1

B0

A>B

A=B

A<B

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1

PIN DIAGRAM FOR IC 7485:

LOGIC DIAGRAM:
4 BIT MAGNITUDE COMPARATOR

TRUTH TABLE:
OUTPUT:

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A

A>B

A=B

A<B

0000

0000

0001

0000

0000

0001

1000

0001

0101

1000

0111

0101

PROCEDURE:
(i)

Connections are given as per circuit diagram.

(ii)

Logical inputs are given as per circuit diagram.

(iii)

Observe the output and verify the truth table.

RESULT:

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EXPT NO. : 6 DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXER
DATE :
AIM:
To design and implement multiplexer and demultiplexer using logic gates.
APPARATUS REQUIRED:
Sl.No.

COMPONENT

SPECIFICATION

QTY.

1.

3 Input AND GATE

IC 7411

2.

OR GATE

IC 7432

3.

NOT GATE

IC 7404

4.

IC TRAINER KIT

5.

PATCH CORDS

As required

THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a smaller number of
channels or lines. A digital multiplexer is a combinational circuit that selects binary information from one
of many input lines and directs it to a single output line. The selection of a particular input line is
controlled by a set of selection lines. Normally there are '2n input line and n' selection lines whose bit
combination determine which input is selected.
DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes information from one
line and distributes it to a given number of output lines. For this reason, the demultiplexer is also known
as a data distributor. Decoder can also be used as demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The data select
lines enable only one gate at a time and the data on the data input line will pass through the selected
gate to the associated data output line.

PIN DIAGRAM OF IC7411

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BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:
S1

S0

INPUTS Y

D0 D0 S1 S0

D1 D1 S1 S0

D2 D2 S1 S0

D3 D3 S1 S0

Y = D0 S1 S0 + D1 S1 S0 + D2 S1 S0 + D3 S1 S0

CIRCUIT DIAGRAM FOR MULTIPLEXER:

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TRUTH TABLE:

S1

S0

Y = OUTPUT

D0

D1

D2

D3

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

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FUNCTION TABLE:
S1

S0

INPUT

X D0 = X S1 S0

X D1 = X S1 S0

X D2 = X S1 S0

X D3 = X S1 S0

Y = X S1 S0 + X S1 S0 + X S1 S0 + X S1 S0

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LOGIC DIAGRAM FOR DEMULTIPLEXER:

TRUTH TABLE:
INPUT

OUTPUT

S1

S0

I/P

D0

D1

D2

D3

PROCEDURE:
iii. Connections are given as per circuit diagram.
iv. Logical inputs are given as per circuit diagram.

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v. Observe the output and verify the truth table.
RESULT:

EXPT NO.7 : CONSTRUCTION AND VERIFICATION OF 4 BIT RIPPLE COUNTER

DATE :
AIM:
To design and verify 4 bit ripple counter.
APPARATUS REQUIRED:
Sl.No.

COMPONENT

SPECIFICATION

QTY.

IC 7476

1.

JK FLIP FLOP

IC TRAINER KIT

PATCH CORDS

As required

THEORY:
A counter is a register capable of counting number of clock pulse arriving at its clock
input. Counter represents the number of clock pulses arrived. A specified sequence of states
appears as counter output. This is the main difference between a register and a counter. There
are two types of counter, synchronous and asynchronous. In synchronous common clock is given
to all flip flop and in asynchronous first flip flop is clocked by external pulse and then each
successive flip flop is clocked by Q or Q output of previous stage. The clock of second stage is
triggered by output of first stage. Because of inherent propagation delay time all flip flops are
not activated at same time which results in asynchronous operation.
PIN DIAGRAM FOR IC 7476:

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LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:

TRUTH TABLE:
CLK

QA

QB

QC

QD

10

11

12

13

14

15

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PROCEDURE:
(i)
(ii)
(iii)

RESULT:

Connections are given as per circuit diagram.

Logical inputs are given as per circuit diagram.
Observe the output and verify the truth table.

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EXPT NO. 8 :

DESIGN AND IMPLEMENTATION OF SHIFT REGISTER

DATE :
AIM:
To design and implement
vi. Serial in serial out
vii. Serial in parallel out
viii.

Parallel in serial out

ix. Parallel in parallel out

APPARATUS REQUIRED:

Sl.No.

COMPONENT

SPECIFICATION

QTY.

1.

D FLIP FLOP

IC 74174

2.

OR GATE

IC 7432

3.

IC TRAINER KIT

4.

PATCH CORDS

As required

THEORY:
A register is capable of shifting its binary information in one or both directions is known
as shift register. The logical configuration of shift register consist of a D-Flip flop cascaded with
output of one flip flop connected to input of next flip flop. All flip flops receive common clock
pulses which causes the shift in the output of the flip flop.

The

simplest

possible

shift

register is one that uses only flip flop. The output of a given flip flop is connected to the input of
next flip flop of the register. Each clock pulse shifts the content of register one bit position to
right.

PIN DIAGRAM: IC
74174

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LOGIC DIAGRAM:
SERIAL IN SERIAL OUT:

TRUTH TABLE:
Serial in

Serial out

CLK

LOGIC DIAGRAM:
SERIAL IN PARALLEL OUT:

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TRUTH TABLE:
OUTPUT
CLK

DATA

QA

QB

QC

QD

LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT:

TRUTH TABLE:
CLK

Q3

Q2

Q1

Q0

O/P

LOGIC DIAGRAM:
PARALLEL IN PARALLEL OUT:

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TRUTH TABLE:
DATA INPUT

OUTPUT

CLK

DA

DB

DC

DD

QA

QB

QC

QD

PROCEDURE:
Connections are given as per circuit diagram.
Logical inputs are given as per circuit diagram.
Observe the output and verify the truth table.
RESULT:

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VHDL - OVERVIEW
1. INTRODUCTION
As integrated circuit technology has improved to allow more and more components on a
chip, digital system have continued grow in complexity. As digital systems have become more
complex, detailed design of the systems at the gate and flip flop level has become very tedious
and time consuming. For this reason, use of hardware description languages in the digital design
process continues to grow in importance. A hardware description language allows a digital
system to be designed and debugged at a higher level before conversion to the gate and flip flop
level. Use of synthesis computer aided design tools to do this conversion is becoming more
widespread. This is analogous to writing software programs in a high level language such as C
and then using a compiler to convert the programs to machine language. The two most popular
hardware description languages are VHDL and Verilog.
VHDL is Hardware description language used to describe the behavior and structure of
digital systems. The acronym VHDL stands for VHSIC Hardware Description Language and
VHSIC stands for Very High Speed Integrated Circuit. VHDL is a general purpose hardware
description language that can be used to describe and simulate the operation of a wide variety of
digital systems, ranging in complexity from a few gates to an interconnection of many complex
integrated circuits. VHDL was originally developed for the military to allow a uniform method
for specifying digital systems. The VHDL language has since become an IEEE standard and it is
widely used in industry.
2. BASIC TERMINOLOGY:
ENTITY: A hardware abstraction of the digital system is called entity. An entity is modeled
using an entity declaration and at least one architecture body. The entity declaration describes
the external view of the entity. The architecture body contains the internal description of the
entity.
ARCHITECTURE BODY: The internal details of an entity are specified by an architecture body
using any of the following modeling styles:
(iii)
Structural style of Modeling (As a set of interconnected components).
(iv)
Dataflow style of Modeling ( As a set of concurrent assignment statement).
(v)
Behavioral
style of Modeling (As a set of sequential assignment
statement).
(vi)
Mixed style of Modeling (As any combination of the above three).
INTERFACE PORTS: Each interface port can have one of the following modes:
1. in : The value of the input port can only be read within the entity model.
2. out : The value of the output port can only be updated within the entity
model. It cannot be read
3. inout : The value of the bi-directional port can be read and updated within
the entity model.
4. buffer: The value of a buffer port can be read and updated within the entity
model. however it differs from the in-out mode in that it cannot have
more than one source.
5. linkage: The value of the linkage port can be read & updated. This can be done

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only by another port of mode linkage. The usage of linkage is not very
clear & is thus not recommended.
CONFIGURATION DECLARATION: A configuration declaration is used to create configuration
for an entity. It specifies the binding of one architecture body from the many architecture bodies
that may be associated with the entity. It may also specify the bindings of components used in
the selected architecture body to other entities.
PACKAGE DECLARATION: It encapsulates a set of related declarations, such as type
declarations, subtype declarations, &sub program declarations, which can be shared across two
or more design units. A package body contains the definitions of subprograms declared in a
package declaration.
3. BASIC LANGUAGE ELEMENTS
These include Data Objects that store values of a given type, Literals that represent
constant values, and Operators that operate on data values.
3.1 INDENTIFIERS:
There are 2 kinds of Identifiers, Basic & Extended Identifiers.
Basic Identifiers: Composed of sequence of one or more characters. The first character
must be a letter. The last character may not be an underscore.
Extended Identifiers: Sequence of characters written between 2 backslashes.
3.2 DATA OBJECTS:
Every data object belongs to one of the following classes.
1. Constant : It can hold a single value of given type. The value cannot be
changed during simulation.
2. Variable : It can hold a single value of given type. Different values can be
assigned to a single variable at different times.
3. Signal
: It holds a list of values, includes current and future values.
4. File
: It contains a sequence of values. Values can be read or written to
the file.
3.3 OBJECT DECLARATION:
Object declaration is used to declare an Object, its type and its class. A value can be
optionally assigned to a signal, variable, constant.
Example:
Constant rise_time: time := 10ns;
Variable sum : integer range 0 to 100 := 10;
Signal clk : bit;
File Declaration Syntax:
file file-name : file-type-name[[open mode] is string-expression];

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3.4 DATA TYPES:
A type is a name that has associated with it a set of values and a set of operations.
The major categories are as follows
1. Scalar types
: Values appear in sequential order.
2. Composite types: Composed of elements of single type(array type) or
elements of different types (record type).
3. Access types
: Provides access to objects of a given type (via pointers).
4. File types
: Provides access to objects that contain sequence of
values of a given type.
3.5 OPERATORS: The predefined operators are classified into the following six categories:
1.Logical Operators.

Eg : and, or, not, nand, nor,xor.

2.Relational Operators.
Eg: =, /=, <, <=, >, >=.
3.Shift Operators.
Eg: sll, sla, srl, rol,ror.
4.Adding Operators.
Eg: +, -, &.
5.Multiplying Operators.
Eg: *, /, mod.
6. Miscellaneous Operators. Eg: **, abs.
4. SEQUENTIAL STATEMENTS: These statements are executed serially. The following are the
some examples of Sequential statements.
(iv)

(v)

if statement: It selects a sequence of statements for execution based od the

value of condition. The general form is:
if Boolean-expression then
sequential statements
elsif Boolean-expression then
sequential statements
else
sequential statements
end if;
case statement: It selects one of the branches for execution based on the values
of the expression. The format of case statement is:
case expression is
when choices => sequential statements
when choices => sequential statements
when others => sequential statements
end case;
loop,null,exit,next assertion statement are some other examples of sequential
statements.

(vi)

Variable assignment statement: It can be declared and used inside the Process
statement. A variable is assigned a value using the Variable assignment statement.
The syntax is given by

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Variable-object := expression;
(vii)

Signal assignment statement: Signals are assigned values using a signal assignment
statement. The syntax is given by

Signal-object <= expression [after delay-value];

A signal assignment statement appears within a process or outside of a process. If it
occurs outside of the process, it is considered to be concurrent statement. It is considered to be
sequential signal assignment statement when appears within the process.

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5.CONCURRENT STATEMENTS:
These type of statements are executed in parallel manner. The following are the
examples of concurrent statements.
1.for-generation scheme : The format is given as follows
generate-label : for generate-identifier in discrete-range generate
block declarations
begin
concurrent-statements
end generate generate-label;
2. if-generation scheme : The general format is given as follows
generate-label : if expression generate
block declarations
begin
concurrent-statements
end generate generate-label;
This scheme allows for conditional selection of concurrent statements based
on the value of an expression.
(viii)

Component Instantiation :

A component instantiation statement defines a

subcomponent of the entity in which it appears. It associates the signals in the

entity with the ports of that subcomponent. A format is given as follows
Component-label : component name [port map (association -list)];
The Block and Process statements are also concurrent statements. The Process statement itself
is a concurrent statement. The statements within Process are sequential statements

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Ex.No:9

SIMULATION OF COMBINATIONAL CIRCUIT using VHDL

Date:
AIM:
To verify the Functionality of a full adder and a four bit binary adder using HDL.
THEORY:
A full adder is capable of adding 2, 1 bit numbers & an input carry. Four full adder circuits
are needed to sum, two 4 bit binary numbers, A&B in parallel. All the bits of A&B are applied
simultaneously. The output carry from one full adder is connected to their input carry of the full
adder to its left. As soon as the carries are generated, the correct sum bits emerge from the sum
outputs of all full adder.
TRUTH TABLE FOR SINGLE BIT FULL ADDER:
Input

Output

Ci

C0

Source Code:
1
0
1
SINGLE BIT FULL ADDER
1
0
library ieee; 1
1
1
1
use ieee.std_logic_1164.all;
entity faddr is
port (a,b,ci : in std_logic;
s,c0 : out std_logic);
end faddr;
architecture struct of faddr is

signal x,y,z : std_logic;

begin
x <= a xor b;
y <= a and b;
z <= x and ci;
s <= x xor ci;
c0 <= y or z;
end struct;

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Source Code
4 BIT BINARY ADDER
library ieee;
use ieee.std_logic_1164.all;
entity fouraddr is
port (a,b : in std_logic_vector(4 downto 1);
c1 :in std_logic;
s : out std_logic_vector(4 downto 1);
c5 : out std_logic);
end fouraddr;
architecture struct of fouraddr is
component faddr
port (a,b,ci : in std_logic;
s,c0 : out std_logic);
end component;
signal z : std_logic_vector(5 downto 1);
begin
z(1) <= c1;
g1 : for i in 1 to 4 generate
u1 : faddr port map (a(i), b(i),z(i),s(i),z(i+1));
c5 <= z(5);
end generate g1;
end struct;
SIMULATED OUTPUT:

Full Adder:

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4 Bit Binary Adder

RESULT:
Thus the functionality of the Four bit binary adder was verified using VHDL

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Ex.No:10

IMPLEMENTATION OF PRIORITY ENCODER

DATE:
AIM:
To verify the Functionality of 4 to 2 Priority Encoder using HDL
THEORY:
A priority encoder is an encoder circuit that includes the priority function. The operation of
the priority encoder is such that if 2 (or) more inputs are equal to 1 at the same time, the input
having the highest priority will take precedence. The truth table of a 4 input priority encoder is
shown in table. The Xs are dont care conditions that designate the binary value, it may be equal
either to 0 or 1. Input D3 has highest priority. D2 has next priority level. D0 has the lowest priority
level.
TRUTH TABLE:
Input
Output
W0 W1 W2 W3 Y0 Y1
0
0
0
0
x
x
1
0
0
0
0
0
x
1
0
0
1
0
x
1
0
1
0
x
x
x
x
1
1
1

Z
0
1
1
1
1

Source Code:
4 TO 2 PRIORITY ENCODER
library ieee;
use ieee.std_logic_1164.all;
entity priority4to2 is
port(w : in std_logic_vector (3 downto 0);
y : out std_logic_vector(1 downto 0);
z : out std_logic);
end priority4to2;
architecture behavior of priority4to2 is
begin
y <= "11" when w(3) = '1' else
"10" when w(2) = '1' else
"01" when w(1) = '1' else
"00" ;
z <= '0' when w = "0000" else '1';
end behavior;

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SIMULATED OUTPUT :

RESULT:
Thus the functionality of the 4 to 2 Priority Encoder was verified using VHDL

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Ex.No:11
Date:

IMPLEMENTATION OF BINARY UPCOUNTER

AIM:
To verify the Functionality of 4 Bit Up Counter using HDL
THEORY:
Four bit counter is capable of counting from 0 to 15. The clock inputs are connected in cascade.
The enable signal is directly connected to first flipflop. Flipflops are connected through the AND
gates. When enable =0 then the inputs of all the flipflpos are 0. When the enable input =1, it
operates. The count is incremented during the rising edge of the clock pulse.

TRUTH TABLE:
Clk
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Q3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Q2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

Source Code:
4 BIT BINARY UPCOUNTER
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity upcount is
port(clk,rst,en : in std_logic;
q : out std_logic_vector(3 downto 0)) ;
end upcount;

Q1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

Q0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

cseitquestions.blogspot.in | cseitquestions.blogspot.in | cseitquestions.blogspot.in

architecture struct of upcount is
signal cnt : std_logic_vector(3 downto 0);
begin
process(clk,rst)
begin
if rst = '0'then
cnt <= "0000";
elsif(clk'event and clk ='1')then
if en = '1'then
cnt <= cnt + '1';
else
cnt <= cnt;
end if;
end if;
end process;
q <= cnt;
end struct;
SIMULATED OUTPUT:

RESULT:
Thus the functionality of 4 bit binary Up Counter was verified using VHDL.