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Digital Combi Plus Seq CKT Design

The document discusses analyzing a combinational logic circuit. It shows how to: 1) Derive the logic expression from the circuit and create a truth table 2) Manipulate the logic expression using theorems into other forms like sum of products 3) Realize the logic expression using different gate types like AND-OR or NAND-NAND It also discusses techniques for minimizing logic expressions and circuits.

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0% found this document useful (0 votes)
306 views226 pages

Digital Combi Plus Seq CKT Design

The document discusses analyzing a combinational logic circuit. It shows how to: 1) Derive the logic expression from the circuit and create a truth table 2) Manipulate the logic expression using theorems into other forms like sum of products 3) Realize the logic expression using different gate types like AND-OR or NAND-NAND It also discusses techniques for minimizing logic expressions and circuits.

Uploaded by

Mahesh
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Combinational Circuit Analysis Example

Given this logic circuit we can : Truth Table


• Find corresponding logic expression from circuit Row X Y Z F
0 0 0 0 0
• Create truth table by applying all input combinations: 1 0 0 1 1
• From truth table find Canonical Sum/Product Representations 2 0 1 0 1
• Manipulate logic expression to other forms using theorems. 3 0 1 1 0
4 1 0 0 0
5 1 0 1 1
6 1 1 0 0
X+Y’ 7 1 1 1 1
X 00001111 00001111
11001111
From truth table:
00110011 11001100
Y Canonical Sum
Y’ (X+Y’) . Z F = Σ X,Y,Z (1, 2, 5,7)
01000101 Canonical Product
Z 01010101 F = Π X,Y,Z (0,3,4,6)
Z 01010101

01100101
X’ 11110000 F

Y 00110011
00100000
X’. Y. Z’
Z’ 10101010
corresponding logic expression: F = ((X + Y’) . Z) + (X’.Y. Z’)

EECC341 - Shaaban
1
#1 Lec # 6 Winter 2001 12-18-2001
Combinational Circuit Analysis Example
(continued)
• The previous circuit logic expression F can be transformed into sum
of products by multiplying out (Using T8’) and written as :

F = X . Z + Y’. Z + X’.Y. Z’
Realized using a 2-level AND-OR circuit:

X
X.Z

F = X . Z + Y’. Z + X’.Y. Z’
Y’
Y Y’ . Z

X’

X’ . Y . Z’
Z Z’

EECC341 - Shaaban
2
#2 Lec # 6 Winter 2001 12-18-2001
Combinational Circuit Analysis Example
(continued)

• The logic expression F for the previous circuit can


added out (using T8) and written as:

F = ((X+Y’).Z) + (X’.Y.Z’)
=
(X+Y’+X’).(X+Y’+Y).(X+Y’+Z’).(Z+X’).(Z+Y).(Z+Z’)
= 1.1.(X+Y’+Z’).(X’+Z).(Y+Z).1
F = (X+Y’+Z’).(X’+Z).(Y+Z)
Realized using 2-level OR-AND circuit.

EECC341 - Shaaban
3
#3 Lec # 6 Winter 2001 12-18-2001
Equivalent Symbols of NAND, NOR Gates
NAND Symbols
Normal Symbol Alternate NAND Symbol
X X
(X . Y)’ X’ + Y’
Y Y

According to DeMorgan’s theorem T13: (X . Y)’ = X’ + Y’

NOR Symbols
Normal NOR Symbol Alternate NOR Symbol

X X
(X + Y)’ X’ . Y’
Y
Y

According to DeMorgan’s theorem T13’: (X + Y)’ = X’ . Y’

EECC341 - Shaaban
4
#4 Lec # 6 Winter 2001 12-18-2001
NAND-NAND Logic Circuits for Sum of Products
• A sum of products logic expression can be realized by
NAND gates by replacing all AND gates and the OR GATE
in the usual realization with NAND gates as follows:
F = A + B + C + D ...

where A, B, C, …. are product terms of the


input variables e.g. A= x.y.z
F = (A’)’+(B’)’+(C’)’+(D’ )’ + …. from T4
= (A’.B’.C’.D’… )’ (from DeMorgan’s theorem T13)

This is a 2-level NAND representation.

EECC341 - Shaaban
5
#5 Lec # 6 Winter 2001 12-18-2001
Alternate Sum of Products Realizations
(Applying DeMorgan’s theorem T13 Graphically)

AND-OR

NAND-NAND

EECC341 - Shaaban
6
#6 Lec # 6 Winter 2001 12-18-2001
NAND-NAND Sum of Products Example
• The sum of products expression
F = X . Z + Y’. Z + X’.Y. Z’
F = ((X . Z)’)’ + ((Y’. Z)’)’ + ((X’.Y. Z’)’)’ double negate T4
F = [(X . Z)’ . (Y’. Z)’ . (X’.Y. Z’)’]’ DeMorgan’s theorem T13
Can be realized using the 2-level NAND-NAND circuit:

X
(X . Z)’

F = [(X . Z)’ + (Y’. Z)’ + (X’.Y. Z’)’]’


Y’
Y (Y’ . Z)’

X’

(X’ . Y . Z’)’
Z Z’

EECC341 - Shaaban
7
#7 Lec # 6 Winter 2001 12-18-2001
NOR-NOR Circuits for Product of Sums
• A product of sums expression can be realized by NOR
gates by replacing all the OR gates and the AND gate
with NOR gates as follows:
F = A.B.C.D. ….
Where A, B, C are sum terms of the input
variables (e.g. A = x+y+z)
F = (A’)’.(B’)’.(C’)’.(D’)’ …. using T4
= (A’ + B’ + C’ + D’ + …)’
(using Demorgan’s theorem T13’)

This is a 2-level NOR-NOR representation

EECC341 - Shaaban
8
#8 Lec # 6 Winter 2001 12-18-2001
Alternate Product of Sums Realizations
(Applying DeMorgan’s theorem T13’ Graphically)

OR-AND

NOR-NOR

EECC341 - Shaaban
9
#9 Lec # 6 Winter 2001 12-18-2001
Combinational Circuit Synthesis
• An example of a combinational circuit description:
Create a logic function in 4 input variables N=N 3N2N1N0
whose output is 1 only if the input is a prime number.
• This function is 1 when the input N =1,2,3,5,7,11 can be
written in the canonical sum of products representation
as:
F = Σ N3N2N1N0 (1,2,3,5,7,11,13)
= N3’N2’N1’N0+ N3’N2’N1N0’+ N3’N2’N1N0
+N3’N2N1’N +N3’N2N1N0+ N3N2’N1N0+ N3N2N1’N 0

EECC341 - Shaaban
10
#10 Lec # 6 Winter 2001 12-18-2001
A Verbal Synthesis Example:
An Alarm Circuit
• A verbal logic description:
– The ALARM output is 1 if the panic input is 1, or if the ENABLE
input is 1, the EXISTING input is 0, and the house is not secure.
– The house is secure if the WINDOW, DOOR, GARAGE inputs are all 1

• This can be put in logic expressions as follows:


ALARM = PANIC + ENABLE . EXISTING’ . SECURE’
SECURE = WINDOW. DOOR. GARAGE
ALARM = PANIC + ENABLE . EXISTING’. (WINDOW . DOOR . GARAGE)’

In sum of products form as (by using DeMorgan T13 and multiplying out) :
ALARM = PANIC + ENABLE. EXISTING’ . WINDOW’
+ ENABLE . EXISTING’. DOOR’+ ENABLE. EXISTING’. GARAGE’

EECC341 - Shaaban
11
#11 Lec # 6 Winter 2001 12-18-2001
Combinational Circuit Minimization
• Canonical sum and product logic expressions do not provide a
circuit realization with the minimum number of gates.

• Minimization methods reduce the cost of two level AND-OR,


NAND-NAND, OR-AND, NOR-NOR circuits in three ways:

1 By minimizing the number of first level gates


2 By minimizing the number of inputs of each first-level gate.
3 Minimizing the inputs of the second level gate

• Most minimization methods are based on the combining theorems


T10, T10’:

given product term.Y + given product term.Y’ = given product term


(given sum term+Y).(given sum term + Y’) = given sum term

EECC341 - Shaaban
#1 Lec # 7 Winter 2001 12-20-2001
Karnaugh Maps
• A Karnaugh Map or (K-map for short) is a graphical
representation of the truth table of a logic function.
• The K-map for an n-input logic function is an array with 2n cells or
squares, one for each input combination or minterm.
• The rows and columns are labeled so that the input combination for
any cell is determined from the row and column headings.
• The row and columns of the map are ordered in such a way that
each cell differs from an adjacent cell in only one input variable:
– Thus for an n-variable K-map, each cell has n adjacent cells.
• The K-map for a function is filled by putting:
– a ‘1’ in the square corresponding to a minterm
– a ‘0’ otherwise (maybe omitted)

EECC341 - Shaaban
#2 Lec # 7 Winter 2001 12-20-2001
2-Variable K-map
For a 2-variable logic function F(X,Y):
Truth Table: K-map
X
Row X Y F Minterm X
Y 0 1
0 0 0 F(0,0) X’.Y’
0 2
1 0 1 F(0,1) X’.Y 0
2 1 0 F(1,0) X.Y’ 1 3
3 1 1 F(1,1) X .Y 1 Y

Example: For the function F(X,Y) = Σ X,Y (1,2,3)


Truth Table: K-map
X
Row X Y F X
Y 0 1
0 0 0 0 0 2
1 0 1 1 0 1
2 1 0 1 1 3
3 1 1 1 1 1 1 Y

EECC341 - Shaaban
#3 Lec # 7 Winter 2001 12-20-2001
3-Variable K-map
For a 3-variable logic function F(X,Y,Z):
Truth Table:
Row X Y Z F Minterm
K-map
X
0 0 0 0 F(0,0,0) X’.Y’.Z’ XY
1 0 0 1 F(0,0,1) X’.Y’.Z Z 00 01 11 10
2 0 1 0 F(0,1,0) X’.Y.Z’
0 2 6 4
3 0 1 1 F(0,1,1) X’.Y.Z 0
4 1 0 0 F(1,0,0) X.Y’.Z’
5 1 0 1 F(1,0,1) X.Y’.Z 1 3 7 5
Z
6 1 1 0 F(1,1,0) X.Y.Z’ 1
7 1 1 1 F(1,1,1) X.Y.Z
Y
Example: For the function F(X,Y,Z) = Σ X,Y,Z (1,2,5,7)
Truth Table: X

Row X Y Z F
K-map XY

0 0 0 0 0
Z 00 01 11 10
1 0 0 1 1 0 2 6 4
2 0 1 0 1 0 1
3 0 1 1 0 1 3 7 5
4 1 0 0 0 1 1 1 1 Z
5 1 0 1 1
6 1 1 0 0
7 1 1 1 1 Y

EECC341 - Shaaban
#4 Lec # 7 Winter 2001 12-20-2001
3-Variable K-map (continued)
• There is a horizontal adjacency wrap-around in the 3-variable K-map:
For example:
– Cell 0 (minterm 0 = X’.Y’.Z’) is adjacent to:
• cell 4 (minterm 4, = X.Y’.Z’) by wrap-around.
• in addition to being adjacent to cells 1, 2 (minterm 1 = X’.Y’.Z
minterm 2, = X’.Y.Z’)

– Cell 1 (minterm 1, X’.Y’.Z) is adjacent to:


• cell 5 (minterm 5, X.Y’.Z) by wrap-around.
• in addition to being adjacent to cells 0 , 2 (minterm 0 = X’.Y’.Z’
minterm 3 = X’.Y.Z)
X
XY
Z 00 01 11 10
0 2 6 4
0
1 3 7 5
Z
1

EECC341 - Shaaban
#5 Lec # 7 Winter 2001 12-20-2001
4-Variable K-map
For a 4-variable logic function F(W,X,Y,Z):

Truth Table: K-map


Row W X Y Z F Minterm
0 0 0 0 0 F(0,0,0,0) W’.X’.Y’.Z’ W
1 0 0 0 1 F(0,0,0,1) W’. X’.Y’.Z WX
2 0 0 1 0 F(0,0,1,0) W’. X’.Y.Z’ YZ 00 01 11 10
3 0 0 1 1 F(0,0,1,1) W’. X’.Y.Z 0 4 12 8
4 0 1 0 0 F(0,1,0,0) W’. X.Y’.Z’ 00
5 0 1 0 1 F(0,1,0,1) W’.X.Y’.Z
1 5 13 9
6 0 1 1 0 F(0,1,1,0) W’.X.Y.Z’
7 0 1 1 1 F(0,1,1,1) W’.X.Y.Z 01
Z
8 1 0 0 0 F(1,0,0,0) W.X’.Y’.Z’ 3 7 15 11
9 1 0 0 1 F(1,0,0,1) W.X’.Y’.Z 11
Y
10 1 0 1 0 F(1,0,1,0) W.X’.Y.Z’ 2 6 14 10
11 1 0 1 1 F(1,0,1,1) W.X’.Y.Z
12 1 1 0 0 F(1,1,0,0) W.X.Y’.Z’
10
13 1 1 0 1 F(1,1,0,1) W.X.Y’.Z X
14 1 1 1 0 F(1,1,1,0) W.X.Y.Z’
15 1 1 1 1 F(1,1,1,1) W.X.Y.Z

EECC341 - Shaaban
#6 Lec # 7 Winter 2001 12-20-2001
4-Variable K-map (continued)
• There are 2 adjacency wrap-arounds in the 4-variable K-map :
a horizontal wrap-around and a vertical wrap-around.
• Every cell thus has 4 neighbours. For example, cell 0 corresponding
to minterm 0 is adjacent to: cells 1, 2, 4, 8

W
WX
YZ 00 01 11 10
0 4 12 8
00
1 5 13 9
01
Z
3 7 15 11
11
Y
2 6 14 10
10
X

EECC341 - Shaaban
#7 Lec # 7 Winter 2001 12-20-2001
4-Variable K-map Example
For the function F(W,X,Y,Z) = Σ W,X,Y,Z (5,7,12,13,14,15)

Truth Table: K-map


W
Row W X Y Z F
WX
0 0 0 0 0 0 YZ
1 0 0 0 1 0
00 01 11 10
0 4 12 8
2 0 0 1 0 0
00 1
3 0 0 1 1 0
4 0 1 0 0 0 1 5 13 9
5 0 1 0 1 1 01 1 1
Z
6 0 1 1 0 0 3 7 15 11
7 0 1 1 1 1 11 1 1
8 1 0 0 0 0 Y
2 6 14 10
9 1 0 0 1 0 1
10 1 0 1 0 0 10
11 1 0 1 1 0
12 1 1 0 0 1 X
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 1

EECC341 - Shaaban
#8 Lec # 7 Winter 2001 12-20-2001
Minimizing Sum of Products using K-maps
• Each input combination with “1” in a Karnaugh map or
truth table correspond to a minterm in the function’s
canonical sum representation.
• Pairs of adjacent “1” cells in the Karnaugh map indicate
minterms that differ in only one variable.
• Using the generalization of T10, such adjacent minterm
pairs can be combined into a single product term.
• In general, one can simplify a logic function by combining
pairs of adjacent 1-cell minterms and writing a sum of
products expression to cover all of the 1-cells.

EECC341 - Shaaban
#9 Lec # 7 Winter 2001 12-20-2001
K-Map Minimization Rules and Definitions
• A minimal sum of a logic function F(X 1, X2, ..Xn) is a sum-of-
products expression for F such that no other similar expression
for F has fewer product terms, and other expressions with the
same number of product terms have at least the same number
of literals.
• A set of 2 i 1-cells are combined into a single square or
rectangle if i variables take all 2 i possible combinations within
the set while the remaining variables have the same value.
• The corresponding product term for the combined cells has n-i
literals.
• Only the variables that have the same value appear in the
resulting product term:
– A variable in the resulting product term is complemented if
it appears as 0 in all the 1-cells, and uncomplemented if it
appears as 1.
EECC341 - Shaaban
#10 Lec # 7 Winter 2001 12-20-2001
Minimization Using K-maps
• Group or combine as many adjacent 1-cells as possible:
– The larger the group is, the fewer the number of literals in the
resulting product term.
– Each group of combined adjacent 1-cells must have a number of
cells equal to powers of two: 1, 2, 4, 8, …
– Grouping 2 adjacent 1-cells eliminates 1 variable, grouping 4 1-
cells eliminates 2 variables, grouping 8 1-cells eliminates 3
variables, and so on. In general, grouping 2n squares eliminates
n variables.

• Select as few groups as possible to cover all the 1-cells


(minterms) of the function:

– The fewer the groups, the fewer the number of product terms in
the minimized function.

EECC341 - Shaaban
#11 Lec # 7 Winter 2001 12-20-2001
3-Variable K-map Minimization Example
• Using K-map, find a minimal sum of products (SOP) expression
expression for the function:
F(X,Y,Z) = Σ X,Y,Z (1,2,5,7)
K-map X

XY

Z 00 01 11 10
0 2 6 4
0 1
1 3 7 5
1 1 1 1 Z

Truth Table
Y
Row X Y Z F
0 0 0 0 0
1 0 0 1 1
2 0 1 0 1
3 0 1 1 0
4 1 0 0 0
5 1 0 1 1
6 1 1 0 0
7 1 1 1 1
EECC341 - Shaaban
#12 Lec # 7 Winter 2001 12-20-2001
3-Variable K-map Minimization Example
• Using K-map, find a minimal sum of products (SOP) expression
expression for the function:
F(X,Y,Z) = Σ X,Y,Z (1,2,5,7)
K-map X’. Y . Z’ X

XY
X.Z
Z 00 01 11 10
0 2 6 4
0 1
1 3 7 5
1 1 1 1 Z

Truth Table
Y
Row X Y Z F
0 0 0 0 0
1 0 0 1 1
2 0 1 0 1
3 0 1 1 0 Y’ . Z
4 1 0 0 0
5 1 0 1 1 Minimum SOP for F = X’. Y . Z’ + X . Z + Y’ . Z
6 1 1 0 0
7 1 1 1 1
EECC341 - Shaaban
#13 Lec # 7 Winter 2001 12-20-2001
3-Variable K-map Minimization Example
• Using K-map, find a minimal sum of products (SOP) expression
expression for the function:
F(X,Y,Z) = Σ X,Y,Z (0,1,4,5, 6)
K-map X

XY
Z 00 01 11 10
0 2 6 4
0 1 1 1
1 3 7 5
1 1 1 Z

Truth Table
Row X Y Z F
Y
0 0 0 0 1
1 0 0 1 1
2 0 1 0 0
3 0 1 1 0
4 1 0 0 1
5 1 0 1 1
6 1 1 0 1
7 1 1 1 0
EECC341 - Shaaban
#14 Lec # 7 Winter 2001 12-20-2001
3-Variable K-map Minimization Example
• Using K-map, find a minimal sum of products (SOP) expression
expression for the function:
F(X,Y,Z) = Σ X,Y,Z (0,1,4,5, 6)
K-map
X . Z’ X

XY
Z 00 01 11 10
0 2 6 4
0 1 1 1
1 3 7 5
1 1 1 Z

Truth Table
Row X Y Z F
Y
0 0 0 0 1
1 0 0 1 1
2 0 1 0 0 Y’
3 0 1 1 0
4 1 0 0 1
5 1 0 1 1 Minimum SOP for F = Y’ + X . Z’
6 1 1 0 1
7 1 1 1 0
EECC341 - Shaaban
#15 Lec # 7 Winter 2001 12-20-2001
4-Variable K-map Minimization Example
• Using K-map, find a minimal sum of products (SOP) expression
expression for the function:
F(N3,N2,N1,N0) = Σ N3,N2,N1,N0 (1,2,3,5,7,11,13)

K-map N3
Truth Table:
N3 N2
Row W X Y Z F
N1 N0 00 01 11 10
0 0 0 0 0 0
0 4 12 8
1 0 0 0 1 1
2 0 0 1 0 1 00
3 0 0 1 1 1
4 0 1 0 0 0 1 5 13 9
5 0 1 0 1 1 01 1 1 1
6 0 1 1 0 0 N0
7 0 1 1 1 1 3 7 15 11
8 1 0 0 0 0
11 1 1 1
9 1 0 0 1 0 N1
2 6 14 10
10 1 0 1 0 0
11 1 0 1 1 1 10 1
12 1 1 0 0 0
13 1 1 0 1 1
14 1 1 1 0 0 N2
15 1 1 1 1 0

EECC341 - Shaaban
#16 Lec # 7 Winter 2001 12-20-2001
4-Variable K-map Minimization Example
• Using K-map, find a minimal sum of products (SOP) expression
expression for the function:
F(N3,N2,N1,N0) = Σ N3,N2,N1,N0 (1,2,3,5,7,11,13)

Truth Table: K-map N3


Row W X Y Z F N3 N2
0 0 0 0 0 0 00 01 11 10
N1 N0
1 0 0 0 1 1
0 4 12 8
2 0 0 1 0 1 N2 . N1’. N0
3 0 0 1 1 1 N3’. N0 00
4 0 1 0 0 0
5 0 1 0 1 1 1 5 13 9
6 0 1 1 0 0 01 1 1 1
7 0 1 1 1 1 N0
8 1 0 0 0 0 3 7 15 11
9 1 0 0 1 0 11 1 1 1
10 1 0 1 0 0 N1
2 6 14 10
11 1 0 1 1 1
12 1 1 0 0 0 10 1
13 1 1 0 1 1
14 1 1 1 0 0 N3’.N2’.N1 N2’ . N1 . N0
15 1 1 1 1 0 N2

Minimum SOP for F = N3’. N0 + N3’. N2’ . N1 + N2’. N1 . N0 + N2 . N1’.N0

EECC341 - Shaaban
#17 Lec # 7 Winter 2001 12-20-2001
K-Map Minimization Rules and Definitions
• A logic function P(X1, X2, ..Xn) implies a logic function F(X1, …, Xn)
if for every input combination such that P=1, then F=1 (F includes
P , or F covers P).
• A prime implicant of a logic function F(X1, ..Xn) is a normal product
term P(X1, ..Xn) that implies F, such that if any variable is removed
from P, the the resulting product term does not imply F.
• A minimal sum is a sum of prime implicants (not necessarily all of
them).
• A distinguished 1-cell of a logic function is an input combination that
is covered by only one prime implicant.
• An essential prime implicant of a logic function is a prime implicant
that covers one or more distinguished 1-cells and must be included
every minimal sum expression for the function.

EECC341 - Shaaban
#18 Lec # 7 Winter 2001 12-20-2001
4-Variable K-map Minimization Example
• Using K-map, find a minimal sum of products (SOP) expression
expression for the function:
F(W,X,Y,Z) = Σ W,X,Y,Z (2,3,4,5,6,7,11,13,15)
• Also identify all prime implicants, distinguished 1-cells and the
corresponding essential prime implicants that cover them.
W

K-map WX

YZ 00 01 11 10
0 4 12 8
00 1
1 5 13 9
01 1 1
Z
3 7 15 11
11 1 1 1 1
Y
2 6 14 10
10 1 1

EECC341 - Shaaban
#19 Lec # 7 Winter 2001 12-20-2001
4-Variable K-map Minimization Example
• Using K-map, find a minimal sum of products (SOP) expression expression for the
function: F(W,X,Y,Z) = Σ W,X,Y,Z (2,3,4,5,6,7,11,13,15)
• Also identify all prime implicants, distinguished 1-cells and the corresponding
essential prime implicants that cover them.
W
K-map W’.X
WX
From K-map:
YZ 00 01 11 10
Prime Implicants: 0 4 12 8
00 1 X.Z
W’. Y W’ . X Y.Z X.Z
1 5 13 9
Distinguished 1-cells: 01 1 1
Z
Cell 2 covered by W’ . Y 7 15 11
3
Cell 4 covered by W’ . X 11 1 1 1 1
Cell 11 covered by Y . Z Y
2 6 14 10
Cell 13 covered by X . Z
10 1 1
Here all prime implicants are Y.Z
essential prime implicants and
all of them must be included in X
minimum SOP expression:
F = W’ . Y + W’. X + Y . Z + X . Z W’ . Y

EECC341 - Shaaban
#20 Lec # 7 Winter 2001 12-20-2001
Minimization with Don’t care Input Combinations

• In some cases, the output of a combinational circuit


doesn’t matter for certain input combinations.

• Such combinations are called don’t cares and the output


is represented in the truth table and K-maps as “d”.

• When using K-maps to minimize such functions:


– Allow d’s to be included when circling sets of 1’s to
make the sets as large as possible.
– Do not circle any set that only contains d’s.

EECC341 - Shaaban
#21 Lec # 7 Winter 2001 12-20-2001
4-Variable K-map Minimization Example With Don’t cares
• Using K-map, find a minimal sum of products (SOP) expression for prime BCD-
digit detector which gives 1 when the input BCD digit is prime,
• Since the values 10-15 do not occur in a BCD digit minterms 10-15 are treated as
don’t cares giving the expression:
F(N3,N2,N1,N0) = Σ N3,N2,N1,N0 (1,2,3,5,7) + d(10,11,12,13,14,15)

From K-map: N3
N3’. N0
N3 N2
Prime Implicants: 00 01 11 10 N2 . N0
N1 N0
N3’. N0 N2’. N1 N2 . N0 0 4 12 8
00 d
Distinguished 1-cells:
1 5 13 9
Cell 1 covered by N3’. N0 1 d
01 1
Cell 2 covered by N2’. N1 N0
3 7 15 11
Here not all prime implicants are 11 1 1 d d
essential prime implicants that N1
2 6 14 10
must be included minimum 10 1 d d
SOP expression:
F = N3’ . N0 + N2’ . N1
N2 N2’. N1

EECC341 - Shaaban
#22 Lec # 7 Winter 2001 12-20-2001
K-map Minimization of Product of Sums
• Similar to K-map minimization of sum of products by
using duality and looking at 0-cells instead of 1-cells.
• A set of 2i 0-cells may be combined if i variables take all 2i
possible combinations within the set while the remaining
variables have the same value.
• In the resulting n-i literals sum term, a variable is
complemented if it appears as 1 in all the 0-cells, and
uncomplemented if it appears as 0.
• A prime implicate of a logic function F(X1, ..Xn), is a normal
sum term S(X1, ..Xn) implied by F, such as if any variable is
removed from S, then the resulting sum term is not
implied by F.
• A minimal product is a product of prime implicates.
EECC341 - Shaaban
#23 Lec # 7 Winter 2001 12-20-2001
K-map Product of Sums Minimization Example 1
• Using K-map, find a minimal product of sums (POS) expression
expression for the function:
F(X,Y,Z) = Π X,Y,Z (0,3,4,7)
K-map X

XY
Z 00 01 11 10
0 2 6 4
0 0 0
1 3 7 5
1 0 0 Z

Truth Table
Row X Y Z F
Y
0 0 0 0 0
1 0 0 1 1
2 0 1 0 1
3 0 1 1 0
4 1 0 0 0
5 1 0 1 1
6 1 1 0 1
7 1 1 1 0
EECC341 - Shaaban
#24 Lec # 7 Winter 2001 12-20-2001
K-map Product of Sums Minimization Example 1
• Using K-map, find a minimal product of sums (POS) expression
expression for the function:
F(X,Y,Z) = Π X,Y,Z (0,3,4,7)
K-map X (Y + Z)
XY
Z 00 01 11 10
0 2 6 4
0 0 0
1 3 7 5
1 0 0 Z

Truth Table
Row X Y Z F
Y
0 0 0 0 0
1 0 0 1 1
2 0 1 0 1 (Y’ + Z’)
3 0 1 1 0
4 1 0 0 0
5 1 0 1 1 Minimum POS for F = (Y + Z) . (Y’ + Z’)
6 1 1 0 1
7 1 1 1 0
EECC341 - Shaaban
#25 Lec # 7 Winter 2001 12-20-2001
K-map Product of Sums Minimization Example 2
• Using K-map, find a minimal product of sums (POS) expression
expression for the function:
F(W,X,Y,Z) = Π W,X,Y,Z (1,3,8,10,12,13,14,15)

K-map WX

YZ 00 01 11 10
0 4 12 8
00 0 0
1 5 13 9
01 0 0
Z
3 7 15 11
11 0 0
Y
2 6 14 10
10 0 0

EECC341 - Shaaban
#26 Lec # 7 Winter 2001 12-20-2001
K-map Product of Sums Minimization Example 2
• Using K-map, find a minimal product of sums (POS) expression
expression for the function:
F(W,X,Y,Z) = Π W,X,Y,Z (1,3,8,10,12,13,14,15)
W

WX
K-map
00 01 11 10
YZ
0 4 12 8 (W’ + Z)
00 0 0
1 5 13 9
(W + X + Z’) 01 0 0
Z
3 7 15 11
11 0 0
Y
2 6 14 10
10 0 0

(W’ + X’)
X

Minimum POS for F = (W + X + Z’) . (W’ + Z) . (W’ + X’)

EECC341 - Shaaban
#27 Lec # 7 Winter 2001 12-20-2001
5-variable K-maps
• The K-map for a 5-variable logic function F(V,W,X,Y,Z) is
organized as two 4-variable K-maps:
W W
WX WX
YZ 00 01 11 10 YZ 00 01 11 10
0 4 12 8 16 20 28 24
00 00
1 5 13 9 17 21 29 25
01 01
Z Z
3 7 15 11 19 23 31 27
11 11
Y Y
2 6 14 10 18 22 30 26
10 10
X X

V=0 V=1

Corresponding squares of each map are adjacent.


Can be visualised as being one 4-variable map on
top of another 4-variable map.

EECC341 - Shaaban
#28 Lec # 7 Winter 2001 12-20-2001
5-Variable K-map SOP Minimization Example
• Using K-map, find a minimal sum of products (SOP) expression
expression for the function:
F(V,W,X,Y,Z) = Σ V,W,X,Y,Z (4,5,6,7,9,11,13,15,25,27,29,31)
K-map
W W
WX WX
YZ 00 01 11 10 YZ 00 01 11 10
0 4 12 8 16 20 28 24
00 1 00
1 5 13 9 17 21 29 25
01 1 1 1 01 1 1
Z Z
3 7 15 11 19 23 31 27
11 1 1 1 11 1 1
Y Y
2 6 14 10 18 22 30 26
10 1 10
X X

V=0 V=1

EECC341 - Shaaban
#29 Lec # 7 Winter 2001 12-20-2001
5-Variable K-map SOP Minimization Example
• Using K-map, find a minimal sum of products (SOP) expression
expression for the function:
F(V,W,X,Y,Z) = Σ V,W,X,Y,Z (4,5,6,7,9,11,13,15,25,27,29,31)
K-map
W W
WX WX
YZ 00 01 11 10 YZ 00 01 11 10
0 4 12 8 16 20 28 24
00 1 00
1 5 13 9 17 21 29 25
01 1 1 1 01 1 1
Z Z
3 7 15 11 19 23 31 27
11 1 1 1 11 1 1
Y Y
2 6 14 10 18 22 30 26
10 1 10
X X

V’ . W’. X V=0 W.Z V=1

Minimum SOP for F = V’ . W’. X + W.Z

EECC341 - Shaaban
#30 Lec # 7 Winter 2001 12-20-2001
K-map for a 6-variable logic function F(U,V,W,X,Y,Z)
6-variable K-maps
is organized as two 5-variable K-maps:
W W
WX WX
YZ 00 01 11 10 YZ 00 01 11 10
0 4 12 8 16 20 28 24
00 00
1 5 13 9 17 21 29 25
01 01
Z Z
3 7 15 11 19 23 31 27
11 11
Y Y
2 6 14 10 18 22 30 26
10 10

X U,V = 0,1 X
U,V = 0,0
W W
WX WX
YZ 00 01 11 10 YZ 00 01 11 10
32 36 44 40 48 52 60 56
00 00
33 37 45 41 49 53 61 57
01 01
Z Z
35 39 47 43 51 55 63 59
11 11
Y Y
34 38 46 42 50 54 62 58
10 10

X U,V = 1,1 X
U,V = 1,0
EECC341 - Shaaban
#31 Lec # 7 Winter 2001 12-20-2001
Combinational Logic Circuit Transient Vs. Steady-state Output
• Gate propagation delay: The time between an input change and the
corresponding change of the output.
• Circuit steady-state output: The output is evaluated when the inputs have
been stable for a long time relative to the gate delays.
• Circuit transient output behavior: The circuit output when one or more
inputs change values.
• Example: For an inverter with propagation delay, ∆ when input changes
from 1 to 0:
Timing Diagram

1
X
X 0
X’
1 → 0 Transient Steady-state output
1 output
X’
0

Time
(propagation delay)

• The circuit analysis done so far ignores propagation delays and considers only
steady-state output when all propagation delays have completed though all the
circuit gates.
EECC341 - Shaaban
#1 Lec # 8 Winter 2001 1-9-2002
Combinational Logic Hazards
• Output glitch: A momentary unexpected transient output change (short
pulse) when an input changes and usually caused by gate propagation
delays.
• Hazards: A hazard exists in a combinational circuit when it produces an
output glitch when one or more inputs change.
• Types of combinational logic hazards:
• Static Hazards:
– Static-1 Hazard: The output should be 1 but goes momentary to 0 as a result of
an input change. (possible in AND-OR circuits)
– Static-0 Hazard: The output should be 0 but goes momentary to 1 as a result of
1 1 1
an input change. (possible in OR-AND circuits)
0 0 0

Static-0 Hazard Static-1 Hazard


• Dynamic Hazards: The output changes more than once as a result of a
single input change (impossible in 2-level circuits). 1 1

0 0

Dynamic Hazard Example


• Static hazards can be detected and eliminated for 2-level logic circuits
using K-maps.
EECC341 - Shaaban
#2 Lec # 8 Winter 2001 1-9-2002
Example: Circuit with Static-1 Hazard
• A static-1 hazard exists in the following AND-OR circuit when X = 1, Y = 1
and Z changes from 1 to 0 (assume all gates have propagation delay ∆ ):
Circuit
Timing Diagram
1
X X . Z’
Z Z’ 1
0 → 1
1 → 0→ 1
Z
1 → 0 0
F ∆
1
1 → 0
Z’
0
1 1
Y Y.Z Y. Z
0
1 ∆
K-map Y. Z’
X 0
XY Steady-state
Z 00 01 11 10 output

0 2 6 4 X . Z’ 1 ∆
0 1 1 F
0
Time
1 3 7 5
1 1 1 Z

Y Y.Z
EECC341 - Shaaban
#3 Lec # 8 Winter 2001 1-9-2002
Eliminating Static-1 Hazards Using K-maps
• A static-1 hazard occurs in AND-OR circuits when an input variable
and its complement are connected to two different AND gates.
• Static-1 hazards are found using k-maps by finding adjacent 1 cells that
are covered by different product terms.
• To eliminate static-1 hazards, additional product terms (prime
implicants) are needed to cover such cells thus covering the transition of
the variable causing the hazard.
• For in the previous example the static-1 hazard is eliminated by
including the additional product term X . Y

X Circuit with static-1 hazard eliminated


XY
Z 00 01 11 10 X X . Z’
0 2 6 4 X . Z’ Z’
0 1 1 Z
1 3 7 5 X.Y F
1 1 1 Z

Y.Z Y X. Y
Y Y.Z

New F = X . Z’ + Y . Z + X. Y
EECC341 - Shaaban
#4 Lec # 8 Winter 2001 1-9-2002
Eliminating Static-0 Hazards Using K-maps
• A static-0 hazard occurs in OR-AND circuits when an input variable
and its complement are connected to two different OR gates.
• The procedure to find and eliminate static-0 hazards using K-maps is
done in a dual way to finding static-1 hazards.
• Static-0 hazards are found using k-maps by finding adjacent 0 cells that
are covered by different sum terms.
• To eliminate static-0 hazards, additional sum terms (prime implicates)
are needed to cover such cells thus covering the transition of the
variable causing the hazard.

EECC341 - Shaaban
#5 Lec # 8 Winter 2001 1-9-2002
Combinational Logic Building Blocks
• Decoders:
– Binary n-to-2n decoders.
– Implementing functions using
decoders.
• Encoders:
– 2n -to-n binary decoders.
• Three-State Buffers.
• Multiplexers.
• Demultiplexers
EECC341 - Shaaban
#1 Lec # 9 Winter 2001 1-10-2002
Decoders
• A decoder is a multiple-input, multiple-output logic
circuit that converts coded inputs into coded outputs,
where the input and output codes are different.
e.g. n-to-2n, BCD decoders.
• Enable inputs must be on for the decoder to function,
otherwise its outputs assume a single “disabled” output
code word.

Decoder
Input
Code word
Output
Map code word
Enable
inputs

EECC341 - Shaaban
#2 Lec # 9 Winter 2001 1-10-2002
Decoder Example: Seven-Segment Decoders
/Bl DC B A a b c d e f g
• A seven segment decoder 0 x x x x 0 0 0 0 0 0 0
1 0 0 0 0 1 1 1 1 1 1 0
has 4-bit BCD input and 1 0 0 0 1 0 1 1 0 0 0 0
the seven segment display 1 0 0 1 0 1 1 0 1 1 0 1
1 0 0 1 1 1 1 1 1 0 0 1
code as its output: 1 0 1 0 0 0 1 1 0 0 1 1
1 0 1 0 1 1 0 1 1 0 1 1
• In minimizing the circuits 1 0 1 1 0 0 0 1 1 1 1 1
1 0 1 1 1 1 1 1 0 0 0 0
for the segment outputs all 1 1 0 0 0 1 1 1 1 1 1 1
1 1 0 0 1 1 1 1 0 0 1 1
non-decimal input combinations

-- don’t care inputs --


1 1 0 1 0 0 0 0 1 1 0 1
(1010, 1011, 1100,1101, 1110, 1 1 0 1 1 0 0 1 1 0 0 1
1 1 1 0 0 0 1 0 0 0 1 1
1111) are taken as don’t-cares 1 1 1 0 1 1 0 0 1 0 1 1
1 1 1 1 0 0 0 0 1 1 1 1
1 1 1 1 1 0 0 0 0 0 0 0

EECC341 - Shaaban
#3 Lec # 9 Winter 2001 1-10-2002
Binary n-to-2n Decoders
• A binary decoder has n inputs and 2n outputs.
• Only the output corresponding to the input value is equal
to 1.

n n to 2n 2n
inputs : decoder outputs
:

EECC341 - Shaaban
#4 Lec # 9 Winter 2001 1-10-2002
2-to-4 Binary Decoder
Truth Table:
X Y F0 F1 F2 F3
0 0 1 0 0 0
0 1 0 1 0 0 F0 = X'Y'
1 0 0 0 1 0
1 1 0 0 0 1
F1 = X'Y
• From truth table, circuit for
2x4 decoder is: F2 = XY'
• Note: Each output is a 2-
variable minterm (X'Y', X'Y, F3 = XY
XY' or XY)

F0
X Y
X 2-to-4 F1
Y Decoder F2
F3

EECC341 - Shaaban
#5 Lec # 9 Winter 2001 1-10-2002
3-to-8 Binary Decoder
Truth Table:
F0 = x'y'z'
x y z F0 F1 F2 F3 F4 F 5 F6 F7 F1 = x'y'z
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0 F2 = x'yz'
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0 F3 = x'yz
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0 F4 = xy'z'
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1 F5 = xy'z

F6 = xyz'
F0
F1 F7 = xyz
X
F2
Y
3-to-8 F3
Z
Decoder F4
F5
F6
x y z
F7

EECC341 - Shaaban
#6 Lec # 9 Winter 2001 1-10-2002
Implementing Functions Using Decoders
• Any n-variable logic function, in canonical sum-of-minterms
form can be implemented using a single n-to-2n decoder to
generate the minterms, and an OR gate to form the sum.
– The output lines of the decoder corresponding to the minterms
of the function are used as inputs to the or gate.
• Any combinational circuit with n inputs and m outputs can be
implemented with an n-to-2n decoder with m OR gates.
• Suitable when a circuit has many outputs, and each output
function is expressed with few minterms.

EECC341 - Shaaban
#7 Lec # 9 Winter 2001 1-10-2002
Implementing Functions Using Decoders
x y z C S
• Example: Full adder 0 0 0 0 0
S(x, y, z) = Σ (1,2,4,7) 0
0
0
1
1
0
0
0
1
1
C(x, y, z) = Σ (3,5,6,7) 0
1
1
0
1
0
1
0
0
1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

3-to-8 0
Decoder 1 S
2
x S2 3
y S1 4
5 C
z S0 6
7

EECC341 - Shaaban
#8 Lec # 9 Winter 2001 1-10-2002
Standard MSI Binary Decoders Example
74138 (3-to-8 decoder)

(a) Logic circuit.


(b) Package pin configuration.
(c) Function table.
EECC341 - Shaaban
#9 Lec # 9 Winter 2001 1-10-2002
Encoders
• If the a decoder's output code has fewer bits than the
input code, the device is usually called an encoder.
e.g. 2n-to-n, priority encoders.
• The simplest encoder is a 2n-to-n binary encoder, where it
has only one of 2n inputs = 1 and the output is the n-bit
binary number corresponding to the active input.
• For an 8-to-3 binay encoder with inputs I0-I7 the logic
expressions of the outputs Y0-Y2 are:
Y0 = I1 + I3 + I5 + I7 Binary
2n encoder n
. .
Y1= I2 + I3 + I6 + I7
inputs . . outputs
. .
Y2 = I4 + I5 + I6 +I7

EECC341 - Shaaban
#10 Lec # 9 Winter 2001 1-10-2002
8-to-3 Binary Encoder
At any one time, only Inputs Outputs
one input line has a value of 1.
I0 I1 I2 I3 I4 I5 I6 I7 y2 y1 y2
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
I0
I1 Y2 = I4 + I5 + I6 + I7
I2
I3 y1 = I2 + I 3 + I6 + I 7
I4
I5
I6
I7 Y0 = I1 + I3 + I5 + I7

EECC341 - Shaaban
#11 Lec # 9 Winter 2001 1-10-2002
Three State (Tri-State) Buffers
• Three state buffers are CMOS and TTL devices whose
outputs may be in one of three states: 0, 1 or Hi-Z (high
impedance, or floating state.
• Have an extra input called “output enable” or “output
disable”.
• When enables the device transmits the input value or its
complement to the output.
Enable
Output
Input

EECC341 - Shaaban
#12 Lec # 9 Winter 2001 1-10-2002
Multiplexers
• A multiplexer (MUX) is a digital switches which
connects data from one of n sources to the output.
• A number of select inputs determine which data source is
connected to the output.
D0 1Y
Multiplexer
Enable EN
s bits
2Y
Select SEL
D1
Data
b bits output
. .
D0
b bits Y . .
D1 . .
bY
n Data . Dn-1
Sources .
b bits
Dn-1
SEL EN

EECC341 - Shaaban
#13 Lec # 9 Winter 2001 1-10-2002
4-to-1 MUX
Truth table for a 4-to-1 multiplexer:

I0 I1 I2 I3 S1 S0 Y S1 S0 Y
d0 d1 d2 d3 0 0 d0 0 0 I0
d0 d1 d2 d3 0 1 d1 0 1 I1
d0 d1 d2 d3 1 0 d2 1 0 I2
d0 d1 d2 d3 1 1 d3 1 1 I3

Inputs Inputs
I0 0 I0
I1 4:1
1 MUX I1
I2 2 Y Output I2 mux Y
I3 3 I3
S1 S 0
S1 S 0
select select

EECC341 - Shaaban
#14 Lec # 9 Winter 2001 1-10-2002
4-to-1 MUX Circuit

I0 I0

I1 I1
Y Y
I2 I2

I3 I3

0 1 2 3
2-to-4
Decoder

S1 S0 S1 S0

EECC341 - Shaaban
#15 Lec # 9 Winter 2001 1-10-2002
Larger Multiplexers
• Larger multiplexers can be constructed from smaller ones.
• An 8-to-1 multiplexer can be constructed from smaller
multiplexers as shown:

I0
S2 S1 S0 Y
I1 4:1
I2 MUX 0 0 0 I0
I3 0 0 1 I1
2:1 0 1 0 I2
S1 S 0 MUX Y 0 1 1 I3
I4 1 0 0 I4
I5 4:1 1 0 1 I5
I6 MUX 1 1 0 I6
S2
I7 1 1 1 I7

S1 S 0

EECC341 - Shaaban
#16 Lec # 9 Winter 2001 1-10-2002
Larger Multiplexers

• A 16-to-1 multiplexer can be


constructed from five 4-to-1
multiplexers:

EECC341 - Shaaban
#17 Lec # 9 Winter 2001 1-10-2002
Standard MSI Multiplexer Example
74151A 8-to-1 multiplexer.

EECC341 - Shaaban
#18 Lec # 9 Winter 2001 1-10-2002
Demultiplexers
• Digital switches to connect data from one input source to one
of n outputs.
• Usually implemented by using n-to-2 n binary decoders where
the decoder’s enable line is used for data input of the
demultiplexer.
2X4
Select Decoder
s bits Demux b bits lines One of
Select four 1-bit
One of n outputs outputs
One of n b bits
Data
Data
Sources
Input
selected
. Input Enable
. data (1bit)
b bits
1-bit 4-output demultiplexer using
a 2x4 binary decoder.

EECC341 - Shaaban
#19 Lec # 9 Winter 2001 1-10-2002
1-to-4 Demultiplexer
Outputs

Y0 = D.S1 '.S0' S1 So Y0 Y1 Y2 Y3
0 0 D 0 0 0
Y1 = D.S1 '.S0
Data D demux
0 1 0 D 0 0
Y2 = D.S1 .S0' 1 0 0 0 D 0
1 1 0 0 0 D
Y3 = D.S1 .S0

S1 S 0
select

Y0 = D.S1 '.S0'
2x4
S1 Decoder Y1 = D.S1 '.S0
S0 Y2 = D.S1 .S0'
E Y3 = D.S1 .S0

D
EECC341 - Shaaban
#20 Lec # 9 Winter 2001 1-10-2002
Mux-Demux Application Example

This enables sharing a single communication line


among a number of devices.
At any time, only one source and one destination can
use the communication line.

EECC341 - Shaaban
#21 Lec # 9 Winter 2001 1-10-2002
Implementing n-variable Functions Using
2n-to-1 Multiplexers
• Any n-variable logic function, in canonical sum-of-
minterms form can be implemented using a single 2n-to-1
multiplexer:
– The n input variables are connected to the mux
select lines.
– For each mux data input line Ii ( 0 ≤ i ≤ 2n - 1):
• Connect 1 to mux input line I i if i is a minterm of the
function.
• Otherwise, connect 0 to mux input line Ii (because i is
not a minterm of the function thus the selected input
should be 0).

EECC341 - Shaaban
#1 Lec # 10 Winter 2001 1-15-2002
Example: 3-variable Function Using 8-to-1 mux
• Implement the function F(X,Y,Z) = Σ(1,3,5,6) using
an 8-to-1 mux.
– Connect the input variables X, Y, Z to mux select lines.
– Mux data input lines 1, 3, 5, 6 that correspond to function
minterms are connected to 1.
– The remaining mux data input lines 0, 2, 4, 7 are connected to 0.

Mux Data 0
Input Lines 0
1 1
0 2
1 3 mux F
0 4
1 5
1 6
0 7
Mux Select
X Y Z Lines

EECC341 - Shaaban
#2 Lec # 10 Winter 2001 1-15-2002
Implementing n-variable Functions Using 2 n-1-to-1
Multiplexers
• Any n-variable logic function can be implemented using a smaller 2 n-1-to-1
multiplexer and a single inverter (e.g 4-to-1 mux to implement 3 variable
functions) as follows:
– Express function in canonical sum-of-minterms form.
– Choose n-1 variables as inputs to mux select lines.
– Construct the truth table for the function, but grouping inputs by
selection line values (i.e select lines as most significant inputs).
– Determine multiplexer input line i values by comparing the remaining
input variable and the function F for the corresponding selection lines
value i:
• Four possible mux input line i values:
– Connect to 0 if the function is 0 for both values of remaining variable.
– Connect to 1 if the function is 1 for both values of remaining variable.
– Connect to remaining variable if function is equal to the remaining
variable.
– Connect to the inverted remaining variable if the function is equal to
the remaining variable inverted.

EECC341 - Shaaban
#3 Lec # 10 Winter 2001 1-15-2002
Example: 3-variable Function Using 4-to-1 mux
• Implement the function F(X,Y,Z) = Σ(0,1,3,6) using a single 4-to-1
mux and an inverter.
– We choose the two most significant inputs X, Y as mux select lines.
– Construct truth table:
Select Lines
Mux Data
Select Lines Mux
Value i X Y Z F Input i Input Lines

0 0 0 1
0 1 1 0
0 0 1 1
Z 1 F
0 1 0 0 mux
1 Z 0 2
0 1 1 1
1 0 0 0 3
2 0
1 0 1 0
1 1 0 1 X Y Mux Select
3 Z’ Lines
1 1 1 0
• We Determine multiplexer input line i values by comparing the remaining input
variable Z and the function F for the corresponding selection lines value i:
– when XY=00 the function F=1 (for both Z=0, Z=1) thus mux input0 = 1
– when XY=01 the function F=Z thus mux input1 = Z
– when XY=10 the function F=0 (for both Z=0, Z=1) thus mux input2 = 0
– when XY=11 the function F=Z’ thus mux input3 = Z’
EECC341 - Shaaban
#4 Lec # 10 Winter 2001 1-15-2002
Example: 4-variable Function Using 8-to-1 mux
• Implement the function F(x1,x2,x3,x4) = ∑(0,1,2,3,4,9,13,14,15) using
a single 74151A 8-to-1 mux and an inverter.
– We choose the three most significant inputs x1,x2,x3 as mux select lines.
– Construct truth table.
– Determine multiplexer Data input line Di values.

EECC341 - Shaaban
#5 Lec # 10 Winter 2001 1-15-2002
Combinational Arithmetic Circuits
• Addition:
– Half Adder (HA).
– Full Adder (FA).
– Carry Ripple Adders.
– Carry Look-Ahead Adders.
• Subtraction:
– Half Subtractor.
– Full Subtractor.
– Borrow Ripple Subtractors.
– Subtraction using adders.
• Multiplication:
– Combinational Array Multipliers.

EECC341 - Shaaban
#1 Lec # 11 Winter 2001 1-16-2002
Half Adder
• Adding two single-bit binary values, X, Y produces a sum S bit and a carry
out C-out bit.
• This operation is called half addition and the circuit to realize it is called a
half adder.

Half Adder Truth Table S(X,Y) = Σ (1,2)


Inputs Outputs S = X’Y + XY’
S = X⊕Y
X Y S C-out
0 0 0 0 C-out(x, y, C-in) = Σ (3)
0 1 1 0 C-out = XY
1 0 1 0
1 1 0 1 X
Sum S
Y
X Half S
Y Adder C-OUT C-out

EECC341 - Shaaban
#2 Lec # 11 Winter 2001 1-16-2002
Full Adder
• Adding two single-bit binary values, X, Sum S X
Y with a carry input bit C-in produces XY
a sum bit S and a carry out C-out bit. C-in 00 01 11 10
0 2 6 4
0 1 1
Full Adder Truth Table
1 3 7 5
Inputs Outputs 1 1 1 C-in

X Y C-in S C-out Y
0 0 0 0 0 S = X’Y’(C-in) + XY’(C-in)’ + XY’(C-in)’ + XY(C-in)
S = X ⊕ Y ⊕ (C-in)
0 0 1 1 0
0 1 0 1 0 Carry C-out X
0 1 1 0 1 XY
1 0 0 1 0 C-in 00 01 11 10
0 2 6 4
1 0 1 0 1 0 1
1 1 0 0 1 1 3 7 5
1 1 1 1 C-in
1 1 1 1 1

S(X,Y, C-in) = Σ (1,2,4,7)


Y

C-out = XY + X(C-in) + Y(C-in)


C-out(x, y, C-in) = Σ (3,5,6,7)
EECC341 - Shaaban
#3 Lec # 11 Winter 2001 1-16-2002
Full Adder Circuit Using AND-OR
X’ X’Y’C-in
X Y’
X X’ C-in

X’
X’YC-in’ Sum S
Y
Y C-in’
Y Y’ X
Y
C-in’ XY’C-in’
C-in
C-in C-in’ X
Y
C-in’ XYC-in

X Y X XY
Y
Full
C-out C-in X
XC-in
Adder C-out
C-in
Y

S
C-in YC-in

EECC341 - Shaaban
#4 Lec # 11 Winter 2001 1-16-2002
Full Adder Circuit Using XOR

Y Sum S
X Y C-in

Full X XY
C-out C-in
Adder Y

X
XC-in C-out
S C-in
Y

C-in YC-in

EECC341 - Shaaban
#5 Lec # 11 Winter 2001 1-16-2002
n-bit Carry Ripple Adders
• An n-bit adder used to add two n-bit binary numbers can built by
connecting in series n full adders.
– Each full adder represents a bit position j (from 0 to n-1).
– Each carry out C-out from a full adder at position j is connected to the
carry in C-in of the full adder at the higher position j+1.
• The output of a full adder at position j is given by:
Sj = Xj ⊕ Yj ⊕ Cj
Cj+1 = X j . Yj + Xj . C j + Y . C j
• In the expression of the sum Cj must be generated by the full adder at the
lower position j-1.
• The propagation delay in each full adder to produce the carry is equal to
two gate delays = 2 ∆
• Since the generation of the sum requires the propagation of the carry from
the lowest position to the highest position , the total propagation delay of
the adder is approximately:
Total Propagation delay ∆
= 2 n∆
EECC341 - Shaaban
#6 Lec # 11 Winter 2001 1-16-2002
4-bit Carry Ripple Adder
Inputs to be added
Adds two 4-bit numbers: X3X2X1X0 Y3Y2Y1Y0
X = X3 X2 X1 X0
Y = Y3 Y2 Y1 Y0
producing the sum S = S3 S2 S1 S0 ,
C-out = C4 from the most significant 4-bit
C4 C-out C-in C0 =0
position j=3 Adder

Total Propagation delay ∆ = 8∆


= 2 n∆ ∆ S3 S2 S1 S0
or 8 gate delays Sum Output

Data inputs to be added

X3 Y3 X2 Y2 X1 Y1 X0 Y0

C4
Full C3 Full C2 Full C1 Full
C-out C-in C-out C-in C-out C-in C-out C-in C0 =0
Adder Adder Adder Adder

S3 S2 S1 S0
Sum output

EECC341 - Shaaban
#7 Lec # 11 Winter 2001 1-16-2002
Larger Adders
• Example: 16-bit adder using 4, 4-bit adders
• Adds two 16-bit inputs X (bits X0 to X15), Y (bits Y0 to Y15)
producing a 16-bit Sum S (bits S0 to S15) and a carry out C16
from most significant position.
Data inputs to be added X (X0 to X15) , Y (Y0-Y15)
X3X2X1X0 Y3Y2Y1Y 0 X3X2X1X0 Y3Y2Y1Y 0 X3X2X1X0 Y3Y2Y1Y 0 X3X2X1X0 Y3Y2Y1Y 0

4-bit C12 4-bit C8 4-bit C4 4-bit


C16 C-out C-in C-out C-in C-out C-in C-out C-in C0 =0
Adder Adder Adder Adder

S3 S2 S1 S0 S3 S2 S1 S0 S3 S2 S1 S0 S3 S2 S1 S0

Sum output S (S0 to S15)

Propagation delay for 16-bit adder = 4 x propagation delay of 4-bit adder


∆ = 4 x 8∆
= 4 x 2 n∆ ∆ = 32 ∆
or 32 gate delays

EECC341 - Shaaban
#8 Lec # 11 Winter 2001 1-16-2002
Carry Look-Ahead Adders
• The disadvantage of the ripple carry adder is that the propagation delay of adder (2 n∆ ∆)
increases as the size of the adder, n is increased due to the carry ripple through all the
full adders.
• Carry look-ahead adders use a different method to create the needed carry bits for each
full adder with a lower constant delay equal to three gate delays.
• The carry out C-out from the full adder at position i or C j+1 is given by:
C-out = C i+1 = Xi . Y i + (Xi + Yi) . Ci
• By defining:
– G i = Xi . Y i as the carry generate function for position i (one gate delay)
(If G i =1 C i+1 will be generated regardless of the value C i)
– Pi = Xi + Yi as the carry propagate function for position i (one gate delay)
(If Pi = 1 C i will be propagated to C i+1)
• By using the carry generate function G i and carry propagate function Pi , then C i+1 can
be written as:
C-out = C i+1 = G i + Pi . C i

• To eliminate carry ripple the term Ci is recursively expanded and by


multiplying out, we obtain a 2-level AND-OR expression for each C i+1

EECC341 - Shaaban
#9 Lec # 11 Winter 2001 1-16-2002
Carry Look-Ahead Adders
• For a 4-bit carry look-ahead adder the expanded expressions
for all carry bits are given by:
C1 = G0 + P0.C0

C2 = G1 + P1.C1 = G1 + P1.G0 + P 1.P0.C0

C3 = G2 + P2.G1 + P 2.P1.G0 + P 2.P1.P0.C0

C4 = G3 + P3.G2 + P 3.P2.G1 + P 3 . P2.P1.G0 + P 3.P2.P1.P0.C 0

where G i = Xi . Yi P i = Xi + Yi

• The additional circuits needed to realize the expressions are


usually referred to as the carry look-ahead logic.
• Using carry-ahead logic all carry bits are available after three
gate delays regardless of the size of the adder.

EECC341 - Shaaban
#10 Lec # 11 Winter 2001 1-16-2002
Carry Look-Ahead Circuit

Ci = Gi-1 + Pi-1. Gi-2 + …. + Pi-1.P i-2. …P1 . G0 + P i-1.P i-2. …P0 . C0

EECC341 - Shaaban
#11 Lec # 11 Winter 2001 1-16-2002
Binary Arithmetic Operations
Subtraction
• Two binary numbers are subtracted by subtracting each
pair of bits together with borrowing, where needed.
• Subtraction Example:

0 0 1 1 1 1 1 0 0 Borrow
X 229 1 1 1 0 0 1 0 1
Y - 46 - 0 0 1 0 1 1 1 0
183 1 0 1 1 0 1 1 1

EECC341 - Shaaban
#12 Lec # 11 Winter 2001 1-16-2002
Half Subtractor
• Subtracting a single-bit binary value Y from anther X (I.e. X -Y ) produces
a difference bit D and a borrow out bit B-out.
• This operation is called half subtraction and the circuit to realize it is called
a half subtractor.

Half Subtractor Truth Table D(X,Y) = Σ (1,2)


Inputs Outputs D = X’Y + XY’
D = X⊕Y
X Y D B-out
0 0 0 0 B-out(x, y, C-in) = Σ (1)
0 1 1 1 B-out = X’Y
1 0 1 0
1 1 0 0 X Difference
D
Y
X Half D
Y Subtractor B-OUT B-out

EECC341 - Shaaban
#13 Lec # 11 Winter 2001 1-16-2002
Full Subtractor
• Subtracting two single-bit binary values, Y, Difference D X
B-in from a single-bit value X produces a XY
difference bit D and a borrow out B-out bit. B-in 00 01 11 10
This is called full subtraction. 0 2 6 4
0 1 1
Full Subtractor Truth Table 1 3 7 5
Inputs Outputs 1 1 1 B-in

X Y B-in D B-out Y
0 0 0 0 0 S = X’Y’(B-in) + XY’(B-in)’ + XY’(B-in)’ + XY(B-in)
S = X ⊕ Y ⊕ (C-in)
0 0 1 1 1
0 1 0 1 1 Borrow B-out X
0 1 1 0 1 XY
1 0 0 1 0 B-in 00 01 11 10
0 2 6 4
1 0 1 0 0 0 1
1 1 0 0 0 1 3 7 5
1 1 1 1 B-in
1 1 1 1 1

S(X,Y, C-in) = Σ (1,2,4,7)


Y

B-out = X’Y + X’(B-in) + Y(B-in)


C-out(x, y, C-in) = Σ (1,2,3,7)
EECC341 - Shaaban
#14 Lec # 11 Winter 2001 1-16-2002
Full Subtractor Circuit Using AND-OR
X’ X’Y’B-in
X Y’
X X’ B-in

X’
X’YB-in’ Difference D
Y
Y B-in’
Y Y’ X
Y
B-in’ XY’B-in’
B-in
B-in B-in’ X
Y
B-in’ XYB-in

X Y X’ X’Y
Y
Full
B-out B-in X’
X’B-in
Subtractor B-out
B-in
Y

D
B-in YB-in

EECC341 - Shaaban
#15 Lec # 11 Winter 2001 1-16-2002
Full Subtractor Circuit Using XOR

Y Difference D
X Y B-in

Full X’ X’Y
B-out B-in
Subtractor Y

X’
X’B-in
B-out
D B-in
Y

B-in YB-in

EECC341 - Shaaban
#16 Lec # 11 Winter 2001 1-16-2002
n-bit Subtractors
An n-bit subtracor used to subtract an n-bit number Y from another
n-bit number X (i.e X-Y) can be built in one of two ways:

• By using n full subtractors and connecting them in series,


creating a borrow ripple subtractor:
– Each borrow out B-out from a full subtractor at position j is connected to
the borrow in B-in of the full subtracor at the higher position j+1.

• By using an n-bit adder and n inverters:


– Find two’s complement of Y by:
• Inverting all the bits of Y using the n inverters.
• Adding 1 by setting the carry in of the least significant
position to 1
– The original subtraction (X - Y) now becomes an addition of
X to two’s complement of Y using the n-bit adder.

EECC341 - Shaaban
#17 Lec # 11 Winter 2001 1-16-2002
4-bit Borrow Ripple Subtractor
Inputs
X3X2X1X0 Y3Y2Y1Y0

Subtracts two 4-bit numbers:


Y = Y3 Y2 Y1 Y0 from 4-bit
X = X3 X2 X1 X0 B4 B-out B-in B0 =0
Subtractor
Y = Y3 Y2 Y1 Y0
producing the difference D = D3 D2 D1 D0 ,
B-out = B4 from the most significant
D3 D2 D1 D0
position j=3
Difference Output D

Data inputs to be subtracted

X3 Y3 X2 Y2 X1 Y1 X0 Y0

B3 B2 B1
B4 B-out Full B-in B-out Full B-in B-out Full B-in B-out Full B-in B0 =0
Subtractor Subtractor Subtractor Subtractor

D3 D2 D1 D0
Difference output D

EECC341 - Shaaban
#18 Lec # 11 Winter 2001 1-16-2002
4-bit Subtractor Using 4-bit Adder
Inputs to be subtracted
Y3 Y2 Y1 Y0

X3 X2 X1 X0

C4
4-bit
C-out C-in C0 = 1
Adder
S3 S2 S1 S0

D3 D2 D1 D0

Difference Output

EECC341 - Shaaban
#19 Lec # 11 Winter 2001 1-16-2002
Binary Multiplication
• Multiplication is achieved by adding a list of shifted multiplicands according to the
digits of the multiplier.
• Ex. (unsigned)
11 1011 multiplicand (4 bits) X3 X2 X1 X0
X 13 X 1101 multiplier (4 bits) x Y3 Y2 Y1 Y0
__________________________
-------- -------------------
X3.Y0 X2.Y0 X1.Y0 X0.Y0
33 101 1 X3.Y1 X2.Y1 X1.Y1 X0.Y1
11 0000 X3.Y2 X2.Y2 X1.Y2 X0.Y2
______ 1011 X3.Y3 X2.Y3 X1.Y3 X0.Y3
_______________________________________________________________________________________________________________________________________________

143 1011 P7 P6 P5 P4 P3 P2 P1 P0
---------------------
10001111 Product (8 bits)

• An n-bit X n-bit multiplier can be realized in combinational


circuitry by using an array of n-1 n-bit adders where is adder is
shifted by one position.
• For each adder one input is the multiplied by 0 or 1 (using AND
gates) depending on the multiplier bit, the other input is n partial
product bits.
EECC341 - Shaaban
#20 Lec # 11 Winter 2001 1-16-2002
4x4 Array Multiplier

EECC341 - Shaaban
#21 Lec # 11 Winter 2001 1-16-2002
Combinational Comparators
• Comparing two binary inputs A, B each n bits for equality (i.e A = B)
is a common operation in computers.
• A single output combinational circuit to accomplish this can be
constructed using n 2-input XNOR gates for bit-wise comparison plus
one n-input AND gate. The output = 1 if A = B
• This can also be done by subtraction (A - B) and checking for a zero
result using a single n-input NOR gate.
• Example: 1-bit comparator: A, B 1-bit each.
– The 1-bit comparison requires a single XNOR gate
Truth table: Output

A B (A ⊕ B)’ A
(A ⊕ B)’
0 0 1 B
Output
0 1 0
1 0 0 1-bit comparator
1 1 1
EECC341 - Shaaban
#1 Lec # 12 Winter 2001 1-23-2002
Example: 4-bit Comparator
Compares A = A3 A2 A1 A0 with B = B3 B2 B1 B0
Output = 1 if A = B

A3
B3

A2
B2
Comparator
Output
A1
B1

A0
B0

EECC341 - Shaaban
#2 Lec # 12 Winter 2001 1-23-2002
Combinational Shift Circuits
• An n-bit shift circuit (shifter) has a single n-bit data input A, and a
single n-bit output R and a number of control inputs to determine
the shift amount (0 to n-1).
• Possible shift operations include:
– Shift left or right:
• Arithmetic right shift (the sign bit is shifted in),
• logic shift (0 is shifted in)
• Rotate left or right.
• Example: Original data input A = 11011
• Shift left by one : 10110
• Logic shift right by one: 01101
• Arithmetic shift right by one: 11101
• Rotate left by one: 10111
• Combinational shift circuits are usually constructed using a number
of levels of multiplexeres.
EECC341 - Shaaban
#3 Lec # 12 Winter 2001 1-23-2002
Example: Combinational 8-Bit Right Shifter
Basic Building Block 2-to-1 Mux A B
S2 S1 S0
1 0 Mux shift amount from 0 to 7
select S
Three levels of Muxes used
D
A7 A6 A5 A4 A3 A2 A1 A0 S2 S1 S0
Connect to:

{
0 for logic
right shift 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
or to A7
for arithmetic
right shift
or to A0 - A6 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
for rotate right

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

R7 R6 R5 R4 R3 R2 R1 R0

• Propagation delay: 2 gate delays per level x 3 levels = 6 gate delays


• How many Mux levels for 32-bit shifter? Propagation delay?

EECC341 - Shaaban
#4 Lec # 12 Winter 2001 1-23-2002
Sequential Logic Circuits
• Unlike combinational logic circuits, the output of sequential
logic circuits not only depends on current inputs but also on the
past sequence of inputs.
• Sequential circuits are constructed using combinational logic
and a number of memory elements with some or all of the
memory outputs fed back into the combinational logic forming
a feedback path or loop.

• A very simple sequential circuit with no inputs created using


inverters to form a feedback loop:

QN

When this circuit is powered up it randomly outputs Q = 0 or Q =1

EECC341 - Shaaban
#1 Lec # 13 Winter 2001 1-29-2002
Sequential Logic Circuits
Combinational
outputs Memory outputs

Combinational Memory
logic elements

Inputs

Sequential circuit = Combinational logic + Memory Elements


Current State of A sequential Circuit: Value stored in memory
elements (value of state variables).
State transition: A change in the stored values in memory elements
thus changing the sequential circuit from one state to another state.

EECC341 - Shaaban
#2 Lec # 13 Winter 2001 1-29-2002
Sequential Circuit Buliding Blocks:
Generic Memory Elements
• A Memory Element: A logic device that can remember a single-bit
value indefinitely, or change its value on command from its inputs.

Memory Q
command Memory Element Output:
element
stored single-bit value

• The output Q of the memory element represents the value stored in the
memory element. This is also called the state variable of the memory
elements. A memory element can be in one of two possible states:
– Q = 0 (the memory element has 0 stored), also said be in state 0.
– Q =1 (the memory element has 1 stored), also said to be in state 1.
• The commands to the memory element formed by its input(s) may include:
– Set: Store 1 (Q=1) in the memory element.
– Reset: Store 0 (Q=0) in the memory element.
– Flip: Change stored value from 0 to 1 or from 1 to 0.
– Hold value: Memory value does not change.
• Memory Element state transition: A change in the stored value from 0 to 1, or from
1 to 0 such as that caused by a flip command.

EECC341 - Shaaban
#3 Lec # 13 Winter 2001 1-29-2002
The State of A sequential Circuit
• A state variable in a sequential circuit represents the
single-bit variable Q stored in a memory element in
circuit.
– Each memory element may be in state 0 or state 1 depending on
the current value stored in the memory element.
• The State of A sequential Circuit:
– The collection of all state variables (memory element stored
values) that at any time contain all the information about the
past necessary to account for the circuit’s future behavior.
– A sequential circuit that contains n memory elements could be
in one of a maximum of 2n states at any given time depending
on the stored values in the memory elements.
– Sequential Circuit State transition: A change in the stored
values in memory elements thus changing the sequential circuit
from one state to another.

EECC341 - Shaaban
#4 Lec # 13 Winter 2001 1-29-2002
Clock Signals & Synchronous Sequential Circuits
• A clock signal is a periodic square wave that indefinitely switches
values from 0 to 1 and 1 to 0 at fixed intervals.
1
Clock signal
0

Clock Cycle
Rising edges of Falling edges Time
the clock of the clock

• Clock cycle time or clock period: The time interval between two
consecutive rising or falling edges of the clock.
• Clock Frequency = 1 / clock cycle time (measured in cycles per second or Hz)
– Example: Clock cycle time = 1ms clock frequency = 1000Hz
• Synchronous Sequential Circuits: Sequential circuits that have a clock
signal as one of its inputs:
– All state transitions in such circuits occur only when the clock value is
either 0 or 1 or happen at the rising or falling edges of the clock depending
on the type of memory elements used in the circuit.
EECC341 - Shaaban
#5 Lec # 13 Winter 2001 1-29-2002
Sequential Circuit Memory Elements: Latches, Flip-Flops
• Latches and flip-flops are the basic single-bit memory
elements used to build sequential circuit with one or two
inputs/outputs, designed using individual logic gates and
feedback loops.
• Latches:
– The output of a latch depends on its current inputs
and on its previous inputs and its change of state
can happen at any time when its inputs change.
• Flip-Flop:
– The output of a flip-flop also depends on current
and previous input but the change in output
(change of state or state transition) occurs at
specific times determined by a clock input.
EECC341 - Shaaban
#6 Lec # 13 Winter 2001 1-29-2002
Sequential Circuit Memory Elements: Latches, Flip-Flops
• Latches:
– S-R Latch
– S-R Latch With Enable
– D-Latch
• Flip-Flops:
– Edge-Triggered D Flip-Flop
– Master/Slave S-R Flip-Flop
– Master/Slave J-K Flip-Flop
– Edge-Triggered J-K Flip-Flop
– T Flip-Flop With Enable
EECC341 - Shaaban
#7 Lec # 13 Winter 2001 1-29-2002
S-R Latch
• An S-R (set-reset) latch can be built using two NOR-
gates forming a feedback loop.
• The output of the S-R latch depends on current as well as
previous inputs or state, and its state (value stored) can
change as soon as its inputs change.

R Function Table
Q
S R Q QN
0 0 last Q Last QN
0 1 0 1
1 0 1 0
1 1 0 0
QN
S

Circuit

EECC341 - Shaaban
#8 Lec # 13 Winter 2001 1-29-2002
S-R Latch With Enable
• Since the S-R latch is responsive to its inputs at all times an enable line
C is used to disable or enable state transitions.
• Behaves similar to a regular S-R latch when enable C=1
S
Circuit

Q
Enable C

QN
R Function Table

S R C Q QN
0 0 1 last Q last QN
S Q 0 1 1 0 1
C 1 0 1 1 0
R Q
1 1 1 0 0
x x 0 last Q last QN
Logic Symbol

EECC341 - Shaaban
#9 Lec # 13 Winter 2001 1-29-2002
D-Latch
• Similar to S-R latch with an enable line, but both S, R
are generated from one input D (data) and an inverter.
• Stores the value of its input D when enable C =1.

Function Table C D Q QN
1 0 0 1
1 1 1 0
D
0 x Last Q Last QN

Q
C
D Q
C Q
QN

Logic Symbol

Circuit
EECC341 - Shaaban
#10 Lec # 13 Winter 2001 1-29-2002
Edge-Triggered D Flip-Flop
• Uses a pair of D latches and inverters.
• Similar in behavior to a D latch except that output and state changes
happen at the rising or falling edge of an input clock.
• A D Flip-Flop triggered on the rising edge of the clock is given by:

Master Latch Slave Latch


QM D Q
D D Q D Q Q
CLK Q
C Q C Q QN
Logic Symbol

CLK Function Table

Clock D CLK Q QN
0 0 1
Circuit
1 1 0
x 0 Last Q Last QN
x x Last Q Last QN

EECC341 - Shaaban
#11 Lec # 13 Winter 2001 1-29-2002
Master/Slave S-R Flip-Flop
• S-R latches are substituted for the D latches in the
negative-edge triggered D flip flop
Master Latch Slave Latch
Circuit
QM
S S Q S Q Q
C C
R R Q R Q QN

CLK Function Table

S R C Q QN
x x 0 last Q last QN
0 0 last Q last QN
S Q 0 1 0 1
C
R Q 1 0 1 0
1 1 undef. undef.
Logic Symbol

EECC341 - Shaaban
#12 Lec # 13 Winter 2001 1-29-2002
Master/Slave J-K Flip-Flop
• Solves the problem in the problem when both S=R=1
• When J=K=1 the last state is inverted.
Master Latch Slave Latch Circuit

QM
S Q S Q Q
J C C
R Q R Q QN
K

CLK
Function Table

J K C Q QN
x x 0 last Q last QN
S Q 0 0 last Q last QN
C 0 1 0 1
R Q
1 0 1 0
Logic Symbol 1 1 last QN last Q

EECC341 - Shaaban
#13 Lec # 13 Winter 2001 1-29-2002
Edge Triggered J-K Flip-Flop
• Created from an edge-triggered D flip-flop
Circuit

J
D Q Q
K
CLK Q QN

CLK

J K C Q QN Logic Symbol
Function Table
x x 0 last Q last QN
x x 1 last Q last QN j Q
0 0 last Q last QN CLK Q
0 1 0 1 k
1 0 1 0
1 1 last QN last Q

EECC341 - Shaaban
#14 Lec # 13 Winter 2001 1-29-2002
T Flip-Flop With Enable
• Changes state on every clock cycle (rising edge of T).

En D Q Q Circuit

CLK Q QN
T

OR
Function Table

EN j Q Q T En Q QN
T CLK Q x 0 last Q last QN
QN
k 1 last QN last Q

EECC341 - Shaaban
#15 Lec # 13 Winter 2001 1-29-2002
Clocked Synchronous State-Machines
• Such machines have the characteristics:
– Sequential circuits designed using flip-flops.
– All flip-flops use a common clock (clocked synchronous).
– A machine using n flip-flops (state memory) has n state variables
(the outputs of the flip-flops) and 2n states.
– In general, the next state and output of the machine both depend
on the current state of the machine and on the current input:
Next state = F(current state, input)
output = G(current state, input)
This type of state machine is called Mealy Machine
– In some cases the next output depends only on the current state
and not directly on the current input

Next state = F(current state, input) output = G(current state)


Such machines are called Moore machines.
EECC341 - Shaaban
#1 Lec # 14 Winter 2001 1-30-2002
Clocked Synchronous State-Machine Model
(Mealy machine)

inputs Next-state excitation State Output outputs


current state
Logic Memory Logic

F G
clock

State memory:
Usually edge-triggered
clock
D or JK flip-flops

Moore Machine

EECC341 - Shaaban
#2 Lec # 14 Winter 2001 1-30-2002
Latch/Flip-Flop Characteristic Equations
• The next output of a flip flop (or next state) can be
obtained from the function table of each type of flip-flop.
• This latch/flip-flop next output behavior is expressed in as
a characteristic function which gives the next state in
terms of the current state and output:

Q* = f (Q , inputs)
(Q* is the next state of Q).
• Vary important in state machine analysis and design.

EECC341 - Shaaban
#3 Lec # 14 Winter 2001 1-30-2002
Characteristic Equations
D latch or flip-flop

present next S-R latch


input state state
S R Q(t) Q*
____________________________________________________

0 0 0 0
D Q(t) Q* 0 0 1 1
________________________________________

0 0 0 0 1 X 0
0 1 0 1 0 X 1
1 0 1 1 1 X X
__________________________________________________

1 1 1
________________________________________ Characteristic Equation:
Characteristic Equation: Q* = S + R’. Q
Q* = D

EECC341 - Shaaban
#4 Lec # 14 Winter 2001 1-30-2002
Characteristic Equations

J-K flip-flop
T flip-flop with enable
J K Q Q*
_______________________________________________________
T Q Q*
0 0 0 0 ________________________________________

0 0 1 1 = hold 0 0 0
0 1 0 0 0 1 1
0 1 1 0 = reset 1 0 1
1 0 0 1 1 1 0
________________________________________

1 0 1 1 = set
Characteristic Equation:
1 1 0 1
1 1 1 0 = flip Q* = T. Q’ + T’ .Q
______________________________________________________

Characteristic Equation:
Q* = J . Q’ + K’. Q

EECC341 - Shaaban
#5 Lec # 14 Winter 2001 1-30-2002
Latch/Flip-Flop Characteristic Equations

Device Characteristic Equations

S-R latch Q* = S+R’.Q


D latch Q* = D
Edge-triggered D flip-flop Q* = D
Master/Slave S-R flip-flop Q* = S+R’.Q
Master/Slave J-K flip flop Q* = J.Q’ + K’.Q
Edge Triggered J-K flip-flop Q* = J.Q’ + K’.Q
T flip-flop Q* = Q’
T flip-flop with enable Q* = EN.Q’ + EN’.Q

EECC341 - Shaaban
#6 Lec # 14 Winter 2001 1-30-2002
Clocked Synchronous State-machine Analysis
Given the circuit diagram of a state machine:
1 Analyze the combinational logic to determine flip-flop input (excitation)
equations: Di = Fi (Q, inputs)
– The input to each flip-flop is based upon current state and circuit
inputs.
2 Substitute excitation equations into flip-flop characteristic equations, giving
transition equations: Qi* = Hi( Di )
3 From the circuit, find output equations: Z = G (Q, inputs)
– The outputs are based upon the current state and possibly the inputs.
4 Construct a state transition/output table from the transition and output
equations:
– Similar to truth table.
– Present state on the left side.
– Outputs and next state for each input value on the right side.
– Provide meaningful names for the states in state table, if possible.
5 Draw the state diagram which is the graphical representation of state table.

EECC341 - Shaaban
#7 Lec # 14 Winter 2001 1-30-2002
Basic Format:
State Diagram
State
Format:
Moore Arc = input X Output
Node = state/output Q
0
1
Input
A B
0 1
0, 1 Mealy

1/1
0/0

A B

0 / 1, 1 / 0
Format:
Arc = input X / mealy output Y
Node = state

EECC341 - Shaaban
#8 Lec # 14 Winter 2001 1-30-2002
State Machine Analysis Example
Analyze the state machine:
1 Input (or excitation) equations:
D0 = Q1’. X
x D Q D1 = Q1 . x + Q0 . x
Q1

Q' Q1' 2 Characteristic equations:


Q0* = D0
Q1* = D1
D Q Q0 Find State equations:

Q' Q0' Q0* = Q1’. x


CP
Q1* = Q1 . x + Q0 . x
y
3 Output equation:
y = (Q0 + Q1) . x'

This is a Mealy Machine since output = G(current state, input)

EECC341 - Shaaban
#9 Lec # 14 Winter 2001 1-30-2002
State Machine Analysis Example
4 From the state equations and output equation, construct the state
transition/output table:

x Input
State equations:
Q0* = Q1’. x Q1 Q0 0 1
Q1* = Q1 . x + Q0 . x
0 0 00,0 01,0
Output equation:
y = (Q0 + Q1) . x' 0 1 00,1 11,0
1 0 00,1 10,0
1 1 00,1 10,0
Current State
Q1* Q0* , y
Output for current
Next State when x =0 Next State state when x =1
Output for current when x =1
state when x =0

EECC341 - Shaaban
#10 Lec # 14 Winter 2001 1-30-2002
State Machine Analysis Example
5 Draw the state diagram of the state machine.

state transition/output table state diagram

x 0/0 1/0
0/1
00 10
Q1 Q0 0 1
0 0 00,0 01,0 1/0 0/1 0/1 1/0
0 1 00,1 11,0
1 0 00,1 10,0 1/0 11
01
1 1 00,1 10,0

Q1* Q0* , y Arc = input x / output y


Node = state

EECC341 - Shaaban
#11 Lec # 14 Winter 2001 1-30-2002
Clocked Synchronous State-machine Analysis
Given the circuit diagram of a state machine:
1 Analyze the combinational logic to determine flip-flop input (excitation)
equations: Di = Fi (Q, inputs)
– The input to each flip-flop is based upon current state and circuit
inputs.
2 Substitute excitation equations into flip-flop characteristic equations, giving
transition equations: Qi* = Hi( Di )
3 From the circuit, find output equations: Z = G (Q, inputs)
– The outputs are based upon the current state and possibly the inputs.
4 Construct a state transition/output table from the transition and output
equations:
– Similar to truth table.
– Present state on the left side.
– Outputs and next state for each input value on the right side.
– Provide meaningful names for the states in state table, if possible.
5 Draw the state diagram which is the graphical representation of state table.

EECC341 - Shaaban
#1 Lec # 15 Winter 2001 2-5-2002
State Machine Analysis Example
Analyze the state machine:
1 Input (or excitation) equations:
D0 = Q1’. X
x D Q D1 = Q1 . x + Q0 . x
Q1

Q' Q1' 2 Characteristic equations:


Q0* = D0
Q1* = D1
D Q Q0 Find State equations:

Q' Q0' Q0* = Q1’. x


CP
Q1* = Q1 . x + Q0 . x
y
3 Output equation:
y = (Q0 + Q1) . x'

This is a Mealy Machine since output = G(current state, input)

EECC341 - Shaaban
#2 Lec # 15 Winter 2001 2-5-2002
State Machine Analysis Example
4 From the state equations and output equation, construct the state
transition/output table:

x Input
State equations:
Q0* = Q1’. x Q1 Q0 0 1
Q1* = Q1 . x + Q0 . x
0 0 00,0 01,0
Output equation:
y = (Q0 + Q1) . x' 0 1 00,1 11,0
1 0 00,1 10,0
1 1 00,1 10,0
Current State
Q1* Q0* , y
Output for current
Next State when x =0 Next State state when x =1
Output for current when x =1
state when x =0

EECC341 - Shaaban
#3 Lec # 15 Winter 2001 2-5-2002
State Machine Analysis Example
5 Draw the state diagram of the state machine.

state transition/output table state diagram

x 0/0 1/0
0/1
00 10
Q1 Q0 0 1
0 0 00,0 01,0 1/0 0/1 0/1 1/0
0 1 00,1 11,0
1 0 00,1 10,0 1/0 11
01
1 1 00,1 10,0

Q1* Q0* , y Arc = input x / output y


Node = state

EECC341 - Shaaban
#4 Lec # 15 Winter 2001 2-5-2002
Clocked State-machine Analysis:
State Naming
• State Naming:
– Optionally name the states and substitute state
names S for state-variable combinations in
transition/output table and in state diagram.
– Example: For a circuit with two flip-flops:
Q1 Q0 State Name
0 0 A
0 1 B
1 0 C
1 1 D
EECC341 - Shaaban
#5 Lec # 15 Winter 2001 2-5-2002
Clocked State-machine Analysis Example:
Transition/Output Table Using State Names
For the last example Q1 Q0 State Name
0 0 A
naming The States: 0 1 B
1 0 C
1 1 D
Transition/output Table:
Transition/output Table using state names:

x x
Q1 Q0 0 1 S 0 1
A 0 0 00,0 01,0 A A,0 B,0
B 0 1 00,1 11,0 B A,1 D,0
C 1 0 00,1 10,0 C A,1 C,0
D 1 1 00,1 10,0 D A,1 C,0

Q1* Q0* , y S* , y

EECC341 - Shaaban
#6 Lec # 15 Winter 2001 2-5-2002
Clocked State-machine Analysis Example:
State Diagram Using State Naming
Q1 Q0 State Name
0 0 A
Naming The States: 0 1 B
1 0 C
1 1 D
State Diagram without state naming: State Diagram with state naming:

0/0 1/0
0/1 0/0 1/0
00 10 0/1
A C

1/0 0/1 0/1 1/0


1/0 0/1 0/1 1/0

1/0 11
01 1/0
B D

Arc = input x / output y


Node = state
EECC341 - Shaaban
#7 Lec # 15 Winter 2001 2-5-2002
Clocked State-machine Analysis:
State Machine Timing Diagram
• The timing diagram for a state machine graphically shows the state machine response in
terms of state variables and output signals vs. time for given time-varying input signals
and a given initial state.
• State machine timing diagrams can be generated using transition/output tables or state
diagrams.
• Timing diagrams can be used to account for both combinational and flip-flop
propagation delays.

• Example: For the state machine in the previous example show the timing diagram for
the following input, assuming an initial state A and ignoring propagation delays:
Cycle: 0 1 2 3 4 5 6 7
1
Clock
0

Time

Input X
0

EECC341 - Shaaban
#8 Lec # 15 Winter 2001 2-5-2002
State Machine Timing Diagram Example
Cycle: 0 1 2 3 4 5 6 7

1
Clock
0

Time

Input X
0

Q1
0

A B D C A A B A
1

Q0
0

Output Y

EECC341 - Shaaban
#9 Lec # 15 Winter 2001 2-5-2002
State Machine Analysis Example 2
Analyze the state machine:

X
D0 Q0 Z1
Y D Q
Q2’
CLK Q

D1 Q1
D Q
Q0
CLK Q

D2 Q2 Z2
D Q
Q1
Q2’
CLK Q
CLK
Input Logic State Memory Output Logic
F G
EECC341 - Shaaban
#10 Lec # 15 Winter 2001 2-5-2002
State Machine Analysis Example 2
Excitation Equations 1
Characteristic Equations
D0 = X . Y’.Q2
Q0* = D0
D1 = X . Q0
Q1* = D1
D2 = Y’ + Q1
Q2* = D2
2

State or Transition Equations


Q0* = D0 = X . Y’ . Q2’
Q1* = D1 = X . Q0
Q2* = D2 = Y’ + Q1

3 Output Equations
Z1 = X . Q0 + Q1’
Z2= (Q1 . Q2)’

EECC341 - Shaaban
#11 Lec # 15 Winter 2001 2-5-2002
State Machine Analysis Example 2
4 From the state equations and output equation, construct the state
transition/output table:
state XY
name Q2 Q1 Q0 00 01 11 10
A 0 0 0 100, 11 000, 11 000, 11 101, 11
B 0 0 1 100, 11 000, 11 010, 11 111, 11
C 0 1 0 100, 01 100, 01 100, 01 101, 01
D 0 1 1 100, 01 100, 01 110, 11 111, 11
E 1 0 0 100, 11 000, 11 000, 11 100, 11
F 1 0 1 100, 11 000, 11 010, 11 110, 11
G 1 1 0 100, 00 100, 00 100, 00 100, 00
H 1 1 1 100, 00 100, 00 110, 10 110,10

Q2* Q1* Q0*, Z1 Z2


(Next State, Outputs)
Transition Equations
Q0* = D0 = X . Y’ . Q2’ Output Equations
Q1* = D1 = X . Q0 Z1 = X . Q0 + Q1’
Q2* = D2 = Y’ + Q1 Z2= (Q1 . Q2)’
EECC341 - Shaaban
#12 Lec # 15 Winter 2001 2-5-2002
State-machine Analysis Example 2:
Transition/Output Table Using State Names

XY
S 00 01 11 10
A E, 11 A, 11 A, 11 F, 11
B E, 11 A, 11 C, 11 H, 11
C E, 01 E, 01 E, 01 F, 01
D E, 01 E, 01 G, 11 H, 11
E E, 11 A, 11 A, 11 E, 11
F E, 11 A, 11 C, 11 G, 11
G E, 00 E, 00 E, 00 E, 00
H E, 00 E, 00 G, 10 G,10
S*, Z1 Z2

EECC341 - Shaaban
#13 Lec # 15 Winter 2001 2-5-2002
State-machine Analysis Example 2:
State Diagram (incomplete)
Y (11) (11) X’ Y B X Y (11)

X Y’ X’ Y’
A C
(11) (11)

XY’ XY’ X’+Y


(11) X’Y’ (01) (01)
(11) XY’
H D
(11)
XY
(11) X’
(01)

G E

Arc: input expression (outputs) = expression (Z1 /Z2)


EECC341 - Shaaban
#14 Lec # 15 Winter 2001 2-5-2002
State Machine Analysis Example 3
Analyze the state machine:

X J Q Z
J1 Q1

K Q
Y K1

J2 Q2
J Q

K2 K Q

CLK

EECC341 - Shaaban
#15 Lec # 15 Winter 2001 2-5-2002
State Machine Analysis Example 3
Excitation Equations Characteristic Equations
J1 = X 1 Q*= J·Q’ + K’·Q
K1 = X·Y Q1*= J1·Q1’ + K1’·Q1
J2 = X’ 2 Q2* = J2·Q2’ + K2’·Q2
K2 = 0

Transition Equations
Q1* = X·Q1’ + (X·Y)’ ·Q1 = X·Q1’ + X’·Q1 + Y’·Q1
Q2* = X’·Q2’ + 0’·Q2 = X’·Q2’ + Q2

3
Output Equation
Z = X·Q1 + Q2

EECC341 - Shaaban
#16 Lec # 15 Winter 2001 2-5-2002
State Machine Analysis Example 3
4 From the state equations and output equation, construct the state
transition/output table:

XY
S Q1 Q2 00 01 11 10
A 0 0 01,0 01,0 10,0 10,0
B 0 1 01,1 01,1 11,1 11,1
C 1 0 11,0 11,0 00,1 10,1
D 1 1 11,1 11,1 01,1 11,1
Q1* Q2*, Z

Transition Equations Output Equation


Q1* = X·Q1’ + X’·Q1 + Y’·Q1 Z = X·Q1 + Q2
Q2* = X’·Q2’ + Q2
EECC341 - Shaaban
#17 Lec # 15 Winter 2001 2-5-2002
State-machine Analysis Example 3:
Transition/Output Table Using State Names

XY
S 00 01 11 10
A B,0 B,0 C,0 C,0
B B,1 B,1 D,1 D,1
C D,0 D,0 A,1 C,1
D D,1 D,1 B,1 D,1
S*, Z

EECC341 - Shaaban
#18 Lec # 15 Winter 2001 2-5-2002
State-machine Analysis Example 3:
State Diagram

Arc Format: 00,01


inputs xy 0 00,01
output z A B
1

10,11 11 10,11
11 1
1 0
1
00,01 C
D 10
00,01,10 0
1
1

EECC341 - Shaaban
#19 Lec # 15 Winter 2001 2-5-2002
State Machine Design Procedure
1. Build state/output table (or state diagram) from word
description using state names.
2. Minimize number of states (optional).
3. State Assignment: Choose state variables and assign bit
combinations to named states.
4. Build transition/output table from state/output table (or state
diagram) by substituting state variable combinations instead
of state names.
5. Choose flip-flop type (D, J-K, etc.)
6. Build excitation table for flip-flop inputs from transition table.
7. Derive excitation equations from excitation table.
8. Derive output equations from transition/output table.
9. Draw logic diagram with excitation logic, output logic, and
state memory elements.
EECC341 - Shaaban
#1 Lec # 16 Winter 2001 2-6-2002
State Machine Design Example 1:
110 Detector
• Word description (110 input sequence detector):
– Design a state machine with input A and output Y.
– Y should be 1 whenever the sequence 1 1 0 has been detected on
A on the last 3 consecutive rising clock edges (or ticks).
– Otherwise, Y = 0
– Note: this is a Moore machine, that is the output, Y, depends only
on inputs at previous clocks rising edges , not on the current
input.
• Timing diagram interpretation of word description (only
rising clock edges are shown):
A 0 1 1 0 0 1 1 1 0 1 1 1

CLK
Y

EECC341 - Shaaban
#2 Lec # 16 Winter 2001 2-6-2002
State Machine Design Example 1: 110 Detector
Step1: Choosing States
• Possible states (What does the state machine need to
remember?):
– Initial : power up, no clocks yet Y=0
– No1s : first 1 not found Y=0
– First1 : first 1 found Y=0
– Two1s : at least 2 consecutive 1s found Y=0
– ALL : found 1 1 0 Y=1

• Are all the states needed?


– Notice: Initial is equivalent to NO1s
– We can drop the state Initial and replace it with state No1s

EECC341 - Shaaban
#3 Lec # 16 Winter 2001 2-6-2002
State Machine Design Example 1: 110 Detector
Step 1: State/Output Table and Diagram
Reset
State Diagram

State Table 0 1
NO1s 0 First1
A
S 0 1 Y 0 0

No1s No1s First1 0 1

First1 No1s Two1s 0


0
1
Two1s ALL Two1s 0
ALL Two1s 1
ALL No1s First1 1
1 0 0
S* Format:
Arc: input A
Node: state/output Y

EECC341 - Shaaban
#4 Lec # 16 Winter 2001 2-6-2002
Step3: State Assignment Considerations
• Why does the choice of state assignment matter?
– Has a big effect on the complexity of excitation and output equations
and thus on the amount of combinational logic needed.
• How to find the best state assignment?
– The only known way is to try all assignments and determine the
resulting equations.
• N = 2: (22)! = 4! = 24 assignments for 2 state bits
• N = 3: (23)! = 8! = 40,320 assignments for three state bits.
• N = 4: (24)! = 16! = 20,922,789,888,000
assignments for 4 state bits!!!
THIS IS NOT PRACTICAL APPROACH!
∴ Use heuristic guidelines for pretty good assignments.
This is still an active area of research!
• There is no effective way to guarantee a “best” assignment. The
heuristic methods sometimes perform poorly!
EECC341 - Shaaban
#5 Lec # 16 Winter 2001 2-6-2002
State Assignment Strategies
• Simplest Assignment:
– Straight binary, not best; purely arbitrary assignment.
• One Hot Assignment:
– Redundant encoding, each flip-flop is assigned a state.
– Uses the same number of bits as there are states (not useful in large
designs).
– Simple to assign; simple next state logic (no state decoding required)
– Output logic is simple! One OR gate per Moore output!
• Almost One Hot Assignment:
– Almost same as One Hot, but one less state bit.
– Use all 0’s to represent a state (usually INIT).
– Must now decode state 0 if it is needed.
• Decomposed Assignment:
– Use the “structure” of the state table to simplify next-state and output
logic.
– An “art” which requires much practice.
EECC341 - Shaaban
#6 Lec # 16 Winter 2001 2-6-2002
Example: State Assignment Strategies
Alternative Assignments AB
Q1..Q4 Q1..Q5 Q1Q2Q3 Q1Q2Q3 S 00 01 11 10 Z
0000 00001 000 000 INIT A0 A0 A1 A1 0
0001 00010 100 001 A0 OK0 OK0 A1 A1 0
0010 00100 101 010 A1 A0 A0 OK1 OK1 0
0100 01000 110 011 OK0 OK0 OK0 OK1 A1 1
1000 10000 111 100 OK1 A0 OK0 OK1 OK1 1
Almost One Decomposed Simplest
One Hot
Hot

– Example decomposition:
• Initial State = all 0’s for easy RESET
• INIT state is different, so use Q 1 = 1 for non-INIT states; thus D1=1
• Z = 1 in only 2 states, so use Q 2 =1 for states when Z = 1; thus Z = Q2
• Use Q3 = 1 for state transitions caused by A having the value of 1 (all
destination states cause by A = 1, i.e. states A1 and OK1); thus D3=A
THUS, simpler next state and output logic!
EECC341 - Shaaban
#7 Lec # 16 Winter 2001 2-6-2002
State Assignment Heuristic Guidelines
Starting from the highest priority to the lowest:
• Choose initial coded state that’s easy to produce at reset: (all 0’s
or 1’s)
– This simplifies the initialization circuitry.
• Freely use any of the 2n state codes for best assignment
(i.e.. with s states, don’t just use the first s integers 0,1,…,s-1)
• Define specific bits or fields that have meaning with respect to
input or output variables (decomposed codes).
• Consider using more than minimum number of state variables to
allow for decomposed codes.
• Minimize number of state variables that change at each transition
• Simplify output logic.

EECC341 - Shaaban
#8 Lec # 16 Winter 2001 2-6-2002
State Machine Design Example 1: 110 Detector
Step 3: State Assignment
• Choose state variable assignments:
– Initial state all 0s
– Q2 = last A, so Q2* = A
– minimize number of transitions

A
Q1 Q2 S 0 1 Y
0 0 No1s No1s First1 0
0 1 First1 No1s Two1s 0
1 1 Two1s ALL Two1s 0
1 0 ALL No1s First1 1

S*

EECC341 - Shaaban
#9 Lec # 16 Winter 2001 2-6-2002
State Machine Design Example 1: 110 Detector
Step 4: Transition/Output Table
• Step 4: Build transition/output table from state/output table by
substituting state variable combinations instead of state names.
A
Q1 Q2 0 1 Y
0 0 00 01 0
0 1 00 11 0
1 1 10 11 0
1 0 00 01 1
Q1* Q2*
=D1 D2 Step 6
• Step 5: Choose D Flip-Flops , so Q*= D
• Step 6: Excitation table:
– Same as Transition/output table with Q1*=D1, Q2*=D2
EECC341 - Shaaban
#10 Lec # 16 Winter 2001 2-6-2002
State Machine Design Example 1: 110 Detector
Steps 7, 8 : Excitation/Output Equations
• Step 7: Excitation equations: D1, D2 = F (A, Q1, Q2)

Q1 Q2 Q1•Q2 Q1 Q2
A 00 01 11 10 A 00 01 11 10
0 0 0 1 0 0 0 0 0 0
D1 : D2 :
1 0 1 1 0 1 1 1 1 1
Q2•A
D1 = Q1•Q2 + Q2•A D2 = A (as planned!)

• Step 8: Output equation: Y = G (Q1, Q2)


Y = Q1•Q2’ (directly read from transition table)

EECC341 - Shaaban
#11 Lec # 16 Winter 2001 2-6-2002
State Machine Design Example 1: 110 Detector
Step 9: Logic Diagram
1

D1 Q1
D P Q Y
CLK
A > C Q

1
D2 Q2
D P Q

CLK
> C Q P = Preset
CLK C = Clear
Both active low

RESET_L
RESET_L reset to initial state (active low)

EECC341 - Shaaban
#12 Lec # 16 Winter 2001 2-6-2002
State Machine Design Example 2:
110/101 Detector
• Word description (110/101 input sequence detector):
– Design a state machine with input A and output Y.
– Y = 1 when either sequence 1 1 0 or 1 0 1 has been detected on
input A on the last 3 consecutive rising clock edges (or ticks).
– Otherwise Y = 0
– Note: Correct sequences may overlap and still be accepted.

• Timing diagram interpretation of word description (only


rising clock edges are shown):

A 0 1 0 1 0 1 1 0 1 0 0 0

CLK
y

EECC341 - Shaaban
#13 Lec # 16 Winter 2001 2-6-2002
State Machine Design Example 2: 110/101 Detector
Step1: Choosing States
• Possible states (What does the state machine need to
remember?):
– Idle : Initial state, no starting 1 yet Y=0
– Got1 : A = 1 on last tick Y=0
– Got10 : Sequence A = 10 on last two ticks Y=0
– Got101 : Sequence A = 101 on last three ticks Y=1
– Got11 : Sequence A = 11 on last two ticks Y=0
– Got110 : Sequence A = 110 on last three ticks Y=1

A 0 1 0 1 0 1 1 0 1 0 0 0
Idle Got10 Got10 Got11 Got101 IDLE
CLK
Idle Got1 Got101 Got101 Got110 Got10
y

EECC341 - Shaaban
#14 Lec # 16 Winter 2001 2-6-2002
State Machine Design Example 2: 110/101 Detector
Step 1: State/Output Table
A
S 0 1 Y
IDLE IDLE Got1 0
Got1 Got10 Got11 0
Got10 IDLE Got101 0
Got101 Got10 Got11 1
Got11 Got110 Got11 0
Got110 IDLE Got101 1

S*

EECC341 - Shaaban
#15 Lec # 16 Winter 2001 2-6-2002
State Machine Design Example 2: 110/101 Detector
Step 1: State Diagram
Reset

0 1
IDLE Got1
0 0
0
0
0

Got110 1 Got10
1 0
1 0
0 Format:
1
Arc: input A
Got11 Got101
Node: state/output Y
1 0 1
1
EECC341 - Shaaban
#16 Lec # 16 Winter 2001 2-6-2002
State Machine Design Example 2: 110/101 Detector
Steps 3: State Assignment
• Step 3: Choose state variable assignments :
– Initial state all 0s
– Q1 = Y From Step 1:
– Q3 = last A, so Q3* = A A
– minimum number Q1 Q2 Q3
S 0 1 Y
of transitions
0 0 0 IDLE IDLE Got1 0
0 0 1 Got1 Got10 Got11 0
0 1 0 Got10 IDLE Got101 0
1 1 1 Got101 Got10 Got11 1
0 1 1 Got11 Got110 Got11 0
1 1 0 Got110 IDLE Got101 1

S*
EECC341 - Shaaban
#17 Lec # 16 Winter 2001 2-6-2002
State Machine Design Example 2: 110/101 Detector
• Step 4: Transition/output table A
• Step 5: Choose D Flip-flops Q1 Q2 Q3 0 1 Y
• Step 6: Excitation table 0 0 0 000 001 0
– Same as Transition table 0 0 1
010 011 0
0 1 0 000 111 0
1 1 1 010 011 1
0 1 1 110 011 0
1 1 0 000 111 1
1 0 0 ddd ddd d
Unused states?
1 0 1 ddd ddd d
Q1*Q2* Q3*
=D1 D2 D3

EECC341 - Shaaban
#18 Lec # 16 Winter 2001 2-6-2002
State Machine Design Example 2: 110/101 Detector
Steps 7: Excitation Equations
Q1 Q2
• Step 7: Excitation equations Q3 A 00 01 11 10
– D1, D2, D3 = F (A, Q1, Q2, Q3) 00 d
D1 :
D1 = Q1’•Q2•Q3•A’ + Q2•Q3’•A 01 1 1 d
D2 = Q2•A + Q3 11 d
D3 = A (as planned!) 10 1 d
Q1 Q2 Q1 Q2
Q3 A 00 01 11 10 Q3 A 00 01 11 10
00 d 00 d
D2 : D3 :
01 1 1 d 01 1 1 1 d
11 1 1 1 d 11 1 1 1 d
10 1 1 1 d 10 d

EECC341 - Shaaban
#19 Lec # 16 Winter 2001 2-6-2002
State Machine Design Example 2: 110/101 Detector
Step 8: Output Equations

• Step 8: Output equation


– Y = Q1 (as planned!)

• Step 9: Logic diagram


– (3) D-Flip-flops + (3) 2-input gates + (1) 3-input AND gate +
(1) 4-input AND gate
– Draw the diagram.
D1 = Q1’•Q2•Q3•A’ + Q2•Q3’•A
D2 = Q2•A + Q3
D3 = A

EECC341 - Shaaban
#20 Lec # 16 Winter 2001 2-6-2002
State Machine Design Procedure
1. Build state/output table (or state diagram) from word
description using state names.
2. Minimize number of states (optional).
3. State Assignment: Choose state variables and assign bit
combinations to named states.
4. Build transition/output table from state/output table (or state
diagram) by substituting state variable combinations instead
of state names.
5. Choose flip-flop type (D, J-K, etc.)
6. Build excitation table for flip-flop inputs from transition table.
7. Derive excitation equations from excitation table.
8. Derive output equations from transition/output table.
9. Draw logic diagram with excitation logic, output logic, and
state memory elements.
EECC341 - Shaaban
#1 Lec # 17 Winter 2001 2-7-2002
State Machine Design Using J-K Flip-Flops
• State machine design step 6 (building excitation table for
flip-flop inputs from transition table):
– When using D flip-flops, since the next state Q* = D, the excitation
table is the same as the transition table with Q* replaced with D.
– In the case of J-K flip-flops, the next state is given by:
Q* = J . Q’ + K’. Q
– In this case we cannot rearrange the characteristic equation to find
separate equations for J, K.
– Instead an application (or excitation) table for J-K flip-flops is used to
obtain the corresponding values of J, K for a given Q to Q* transition:

Q Q* J K
0 0 0 d
0 1 1 d
1 0 d 1
1 1 d 0
J-K Flip-Flop Excitation Table
EECC341 - Shaaban
#2 Lec # 17 Winter 2001 2-7-2002
State Machine Design Example 1:
110 Detector (Repeated Using J-K Flip-Flops)

• Word description (110 input sequence detector):


– Design a state machine with input A and output Y.
– Y should be 1 whenever the sequence 1 1 0 has been detected on
A on the last 3 consecutive rising clock edges (or ticks).
– Otherwise, Y = 0

• Timing diagram interpretation of word description (only


rising clock edges are shown):

A 0 1 1 0 0 1 1 1 0 1 1 1

CLK
Y

EECC341 - Shaaban
#3 Lec # 17 Winter 2001 2-7-2002
State Machine Design Example 1: 110 Detector
Step 1: State/Output Table and Diagram
Reset
State Diagram

State Table 0 1
NO1s 0 First1
A
S 0 1 Y 0 0

No1s No1s First1 0 1

First1 No1s Two1s 0


0
1
Two1s ALL Two1s 0
ALL Two1s 1
ALL No1s First1 1
1 0 0
S* Format:
Arc: input A
Node: state/output Y

EECC341 - Shaaban
#4 Lec # 17 Winter 2001 2-7-2002
State Machine Design Example 1: 110 Detector
Using J-K Flip-flops
Q Q* J K
• Steps 1-4: No change.
0 0 0 d
Transition Table (step 4): 0 1 1 d
A 1 0 d 1
Q1 Q2 0 1 Y 1 1 d 0
0 0 00 01 0 J-K Flip-Flop Excitation Table

0 1 00 11 0 Excitation table (Step 6):


A
1 1 10 11 0 Q1 Q2 0 1 Y
1 0 00 01 1 0 0 0d, 0d 0d, 1d 0

Q1* Q2* 0 1 0d, d1 1d, d0 0


1 1 d0, d1 d0, d0 0
• Step 5: Choose J-K Flip-Flops 1 0 d1, 0d d1, 1d 1
• Step 6: Excitation table: Use J-K
Flip-Flop Excitation Table. J1 K1, J2 K2
EECC341 - Shaaban
#5 Lec # 17 Winter 2001 2-7-2002
State Machine Design Example 1: 110 Detector Using J-K FF
Steps 7, 8 : Excitation/Output Equations
• Step 7: Excitation equations: J1, K1, J2, K2 = F (A, Q1, Q2)
Q1 Q2
Q1 Q2
A 00 01 11 10 A 00 01 11 10
0 0 0 d d 0 0 d d 0
J1 : J2 :
1 0 1 d d 1 1 d d 1
J1 = Q2•A J2 = A
Q1 Q2
Q1 Q2
A 00 01 11 10 A 00 01 11 10
0 d d 0 1 0 d 1 1 d
K1 : K2 :
1 d d 0 1 1 d 0 0 d
K1 = Q2’ K2 = A’
• Step 8: Output equation: Y = G (Q1, Q2)
Y = Q1•Q2’ (directly read from transition table)
EECC341 - Shaaban
#6 Lec # 17 Winter 2001 2-7-2002
Registers & Counters
• Registers.
• Shift Registers:
– Serial in, serial out shift register
– Serial in, parallel out shift register
– Parallel in, serial out shift register
– Parallel in, parallel out shift register
– Shift Register Applications

• Counters:
– Ripple Counters
– Synchronous Counters
– Counter Applications

EECC341 - Shaaban
#1 Lec # 18 Winter 2001 2-13-2002
Registers
• An n-bit register is a collection of n D flip-flops with a
common clock used to store n related bits.
74LS175
1D D
Q 1Q Example: 74LS175
CLR
Q
/1Q 4-bit register

2Q
74LS175
Q
2D D CLK
Q
CLR /2Q CLR

Q 3Q 1D 1Q
3D D
1Q
Q
CLR /3Q 2D 2Q
2Q
3D 3Q
Q 4Q
4D D 3Q
CLR
Q
/4Q 4D 4Q
CLK 4Q

/CLR
EECC341 - Shaaban
#2 Lec # 18 Winter 2001 2-13-2002
Shift Registers
• Multi-bit register that moves stored data bits left/right
( 1 bit position per clock cycle)
– Shift Left is towards MSB
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
0 1 1 1 LSI 1 1 1 LSI

– Shift Right (or Shift Up) is towards MSB

Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
RSI 0 1 1 1 RSI 0 1 1

EECC341 - Shaaban
#3 Lec # 18 Winter 2001 2-13-2002
Serial In, Serial Out Shift Register
SERIN D Q SRG n
>
CLOCK CLK
SI SO

D Q For a n-bit SRG:


Serial Out = Serial In delayed
CLK
by n clock period

• 4-bit shift register example:


• serin: 1 0 1 1 0 0 1 1 1 0
• serout: - - - - 1 0 1 1 0 0
clock:
D Q SEROUT

CLK

EECC341 - Shaaban
#4 Lec # 18 Winter 2001 2-13-2002
Serial In, Parallel Out Shift register
SRG n
>
SERIN D Q 1Q SI 1Q
CLOCK CLK 2Q


D Q 2Q •
nQ (SO)
CLK

• Serial to Parallel Converter



• 4-bit shift register example:
serin: 1 0 1 1 0 0 1 1 1 0
1Q: - 101100111
D Q nQ 2Q: - - 10110011
CLK 3Q: - - - 1011001
4Q: - - - - 101100
clock:

EECC341 - Shaaban
#5 Lec # 18 Winter 2001 2-13-2002
Parallel In, Serial Out Shift Register
CLOCK
LOAD/SHIFT
SERIN S 1Q
D Q
1D L CLK

S 2Q
D Q
2D L CLK
Parallel to Serial
Converter
• •
Load/Shift=1 • •
Di Qi • •
Load/Shift=0
Qi Qi+1 NQ
S D Q SEROUT
ND L CLK

EECC341 - Shaaban
#6 Lec # 18 Winter 2001 2-13-2002
Parallel In, Parallel Out Shift Register
CLOCK
LOAD/SHIFT
SERIN S D Q 1Q
1D L CLK

S D Q 2Q
2D L CLK

General Purpose: • •
Makes any kind of • •
• •
(left) shift register
S D Q NQ
ND L CLK

EECC341 - Shaaban
#7 Lec # 18 Winter 2001 2-13-2002
Bi-directional Universal Shift Registers
11
1
CLK
CLR 74x194
10
Modes: S1
9
Hold S0
Load 7
Shift Right LIN R L
6 12
Shift Left 5
D QD 13
4 C QC
14
3 B QB
15
2
A QA
RIN

4-bit Bi-directional Universal (4-bit) PIPO


Mode Next state
Function S1 S0 QA* QB* QC* QD*
Hold 0 0 QA QB QC QD
Shift right/up 0 1 RIN QA QB QC
Shift left/down 1 0 QB QC QD LIN
Load 1 1 A B C D

EECC341 - Shaaban
#8 Lec # 18 Winter 2001 2-13-2002
(11)
CLK
(1) S1 S0
/CLR 74x194
RIGHT
(7)
LIN SL
10 LEFT
HO
00 (12)
D Q QD
(6) LD
D 11
CLK
SR
01
CLR

(10)
S1

10
(9)
S0
00
(15)
D Q QA
(3)
A 11
(2) CLK
RIN 01
CLR

Universal SR Circuit
EECC341 - Shaaban
#9 Lec # 18 Winter 2001 2-13-2002
Shift Register Applications
• State Registers
– Shift registers are often used as the state register in a sequential
device. Usually, the next state is determined by shifting right and
inserting a primary input or output into the next position (i.e. a finite
memory machine)
– Very effective for sequence detectors
• Serial Interconnection of Systems
– keep interconnection cost low with serial interconnect
• Bit Serial Operations
– Bit serial operations can be performed quickly through device
iteration
– Iteration (a purely combinational approach) is expensive (in terms of
# of transistors, chip area, power, etc).
– A sequential approach allows the reuse of combinational functional
units throughout the multi-cycle operation
EECC341 - Shaaban
#10 Lec # 18 Winter 2001 2-13-2002
Shift Register Applications:
Serial Interconnection of Systems
CLOCK
Transmitter Receiver
Control Control
Circuits /SYNC Circuits

Parallel
Parallel
Data
Data to
from
Serial-to- D-to-A
A-to-D Parallel- Serial DATA
parallel converter
converter to-serial
converter converter
One bit
n n

EECC341 - Shaaban
#11 Lec # 18 Winter 2001 2-13-2002
Shift Register Applications Example:
8-Bit Serial Adder
x7 x6 x5 x0
CTL Sequential Implementation of:
7 6 5 ... 0
CLK > Z[7..0] = X[7..0] + Y[7..0]

y7 y6 y5 y0

7 6 5 ... 0
>

D Q Cin A B
CLK FA
Cout S
CLR 7 6 5 ... 0
>
CLEAR_C
z7 z6 z5 ... z0
V
EECC341 - Shaaban
#12 Lec # 18 Winter 2001 2-13-2002
Counters
• Clocked sequential circuit with single-cycle state
diagram
– Modulo-m counter = divide-by-m counter

S1

– Sm S2

S3
– Most Common:
n-bit binary counter, where m = 2n Ù n flip-flops,
counts 0 … 2n-1
EECC341 - Shaaban
#13 Lec # 18 Winter 2001 2-13-2002
4-bit Ripple Counter
1 bit
Q Q0
CLK T divide-by-2
Q
2 bit
Q Q1
divide-by-4
T Uses
Q Minimal
3 bit Logic
Q Q2
divide-by-8
T
Q
4 bit
Q Q3
T divide-by-16
Q
EECC341 - Shaaban
#14 Lec # 18 Winter 2001 2-13-2002
Ripple Counter Timing

CLK

1∆
Q0

Q1 2∆

Q2 3∆

0 1 2 3 4

EECC341 - Shaaban
#15 Lec # 18 Winter 2001 2-13-2002
Ripple Counter Problem
n • TCQ for MSB change for n-bit ripple counter => minimum clk period

CLK

1∆
Q0

Q1 2∆

Q2 3∆

7 Should be 0 1 2

EECC341 - Shaaban
#16 Lec # 18 Winter 2001 2-13-2002
Synchronous Counters

• All clock inputs connected to common CLK


signal
– All flip-flop outputs change simultaneously
tCQ after CLK
– Faster than ripple counters
– More complex logic
– Most frequently used type of counter

EECC341 - Shaaban
#17 Lec # 18 Winter 2001 2-13-2002
Synchronous Serial Counter
CNTEN EN Q Q0
• Flip-flops enabled
when all lower CLK >T
flip-flops = 1.
∆t EN Q Q1
• Enable propagates
serially — limits
>T
speed
• Requires ∆t EN Q Q2
(n-1) ∆ t < TCLK
• All outputs change >T
simultaneously tCQ
∆t EN Q Q3
after CLK
>T
EECC341 - Shaaban
#18 Lec # 18 Winter 2001 2-13-2002
Synchronous Parallel Counter
CNTEN EN Q Q0

CLK >T

• Single-level enable logic EN Q Q1


per flip-flop
• Fastest and most >T
complex type of counter
• Requires ∆ t < TCLK EN Q Q2
• All outputs change
simultaneously tCQ after
CLK >T

EN Q Q3

>T

EECC341 - Shaaban
#19 Lec # 18 Winter 2001 2-13-2002
74X163 4-bit Synchronous Parallel Counter

74X163
Common Clock >CLK
Synchronous Clear CLR
Synchronous Load LD
Count Enable = ENP • ENT ENP
ENT
A
Load Data Inputs B
QA LSB
C
QB
D
QC
QD MSB
RCO RCO = Ripple Carry Out,
when Count = 1111 and ENT
=1

EECC341 - Shaaban
#20 Lec # 18 Winter 2001 2-13-2002
74X163 State Table
Inputs Current State Next State

/CLR /LD ENT ENP QD QC QB QA QD* QC* QB* QA*


0 X X X Clear X X X X 0 0 0 0
1 0 X X Load X X X X D C B A
1 1 0 X Hold X X X X QD QC QB QA
1 1 1 0 Hold X X X X QD QC QB QA
1 1 1 1 Count 0 0 0 0 0 0 0 1
1 1 1 1 . 0 0 0 1 0 0 1 0
1 1 1 1 . 0 0 1 0 0 0 1 1
1 1 1 1 . 0 0 1 1 0 1 0 0
1 1 1 1 0 1 0 0 0 1 0 1
1 1 1 1 0 1 0 1 0 1 1 0
1 1 1 1 0 1 1 0 0 1 1 1
1 1 1 1 0 1 1 1 1 0 0 0
1 1 1 1 1 0 0 0 1 0 0 1
1 1 1 1 1 0 0 1 1 0 1 0
1 1 1 1 1 0 1 0 1 0 1 1
1 1 1 1 1 0 1 1 1 1 0 0
1 1 1 1 1 1 0 0 1 1 0 1
1 1 1 1 1 1 0 1 1 1 1 0
1 1 1 1 1 1 1 0 1 1 1 1
1 1 1 1 1 1 1 1 0 0 0 0

EECC341 - Shaaban
#21 Lec # 18 Winter 2001 2-13-2002
74X169 Up/Down Counter

74X169 UP/DN = 1 = up Ù RCO = 15


>CLK UP/DN = 0 = down Ù RCO = 0
UP/DN
LD
ENP up down up
ENT
A Ex: 0,1,2, 1,0,15,14, 15,0,1,2
B
QA
RCO RCO
C
QB
D
QC
QD
RCO

EECC341 - Shaaban
#22 Lec # 18 Winter 2001 2-13-2002
Counter Applications
• Count the number of times an event takes place
• Control the number of steps in a sequence of fixed
actions (a sequencer)
• Generate timing signals (frequency divider, etc.)
ENTER
UP Decoder
CLK > CTR DIV 6
COUNTER CLR_R
EXIT DOWN 0
1 IN_A
EN IN_B
2
3 EXE
1 4 EXE
# of spaces Comparator 2 OUT_C
5
< = 4 6
7

Lot Lot
>
Open Full

EECC341 - Shaaban
#23 Lec # 18 Winter 2001 2-13-2002
Memory Devices
• Read Only Memory (ROM)
– Structure of diode ROM
– Types of ROMs.
– ROM with 2-Dimensional Decoding.
– Using ROMs for Combinational Logic

• Read/Write Memory
(Random Access Memory, RAM):
– Types of RAM:
• Static RAM (SRAM)
• Dynamic RAM (DRAM)
– SRAM Timing
– DRAM Timing
EECC341 - Shaaban
#1 Lec # 19 Winter 2001 2-14-2002
Read-Only Memory (ROM)
• A combinational circuit with n inputs and b outputs:

Address n 2n x b b Data
inputs ROM outputs
A(n-1, ... , 0) D(b-1, ... , 0)

• Programmable  values determined by user


• Nonvolatile  contents retained without power
• Uniform (Random) Access  delay is uniform for all addresses

EECC341 - Shaaban
#2 Lec # 19 Winter 2001 2-14-2002
Read-Only Memory (ROM)

• Two views of ROM:


– ROM stores 2n words of b bits each, or
– ROM stores an n-input, b-output truth table
n=2 b=4
Example: A1 A0 D3 D2 D1 D0
0 0 0 1 0 1 Stores 4 4-bit words, or
0 1 1 1 1 1 stores 4 functions of 2
1 0 0 0 0 1 input variables
1 1 1 0 0 0

EECC341 - Shaaban
#3 Lec # 19 Winter 2001 2-14-2002
Internal Structure of 4×4 Diode ROM
+5 V

R3 R2 R1 R0

/w0 0101 1 of n Word Lines


A1
/w1 1111
2 to 4
A0
Decoder /w2
0001
/w3 1000
Bit Lines
D0
Diode 1 D1
D2
No Diode 0
D3

EECC341 - Shaaban
#4 Lec # 19 Winter 2001 2-14-2002
• Mask ROM
Types Of ROMs
– Connections made by the semiconductor vendor
– Expensive setup cost, Several weeks for delivery. High volume only
– Bipolar or MOS technology
• PROM
– Programmable ROM
– Vaporize (blow) fusible links with PROM programmer using high voltage/current pulses
– Bipolar technology
– One-time programmable
• EPROM
– Erasable Programmable ROM
– Charge trapped on extra “floating gate” of MOS transistors
– Exposure to UV light removes charge. Limited number of erasures (10-100)

• EEPROM (E2ROM)
– Electrically Erasable ROM
– Not RAM (relatively slow charge/discharge)
– limited number of charge/discharge cycles (10,000)
• Flash Memory
– Electronically erasable in blocks
– 100,000 erase cycles
– Simpler and denser than EEPROM
EECC341 - Shaaban
#5 Lec # 19 Winter 2001 2-14-2002
ROM Type Summary

Type Technology Read Cycle Write Cycle Comments


Mask ROM NMOS,CMOS 20-200 ns 4 weeks Write once; low power
Mask ROM Bipolar <100 ns 4 weeks Write once; high power; low density

PROM Bipolar <100 ns 5 minutes Write once; high power; no mask


charge
EPROM NMOS, CMOS 25-200 ns 5 minutes
Reusable; low power; no mask charge
EEPROM NMOS 50-200 ns 10 µs/byte 10,000 writes/location limit
FLASH CMOS 25-200 ns 10 µs/block 100,000 erase cycles

EECC341 - Shaaban
#6 Lec # 19 Winter 2001 2-14-2002
Internal Structure of Transistor ROM
• Replace diodes with MOS transistors
• Change decoder to active-high outputs
+5 V

R3 R2 R1 R0
w3
1000
Transistor 1

No transistor 0
/D3 /D2 /D1 /D0

EECC341 - Shaaban
#7 Lec # 19 Winter 2001 2-14-2002
EPROM and EEPROM Structure
VDD

Floating gate

Active-high
word lines

Active-low
bit lines

EECC341 - Shaaban
#8 Lec # 19 Winter 2001 2-14-2002
64 x 1 ROM with 2-Dimensional Decoding
+5 V

• • •
/w0
A5 /w1
3 to 8 8x8

A3 Decoder • Diode Array
/w7 •

A2
0 7
A0 8 to 1 mux
D0

Almost square chip

EECC341 - Shaaban
#9 Lec # 19 Winter 2001 2-14-2002
A0
A1
Row Storage
decoder array
Power Power
Am-1 on on

Am Power
Am+1 on
Column
multiplexer
An-1

/CS
/OE

Internal 2n x b ROM Structure


Db-1 Db-2 D0

EECC341 - Shaaban
#10 Lec # 19 Winter 2001 2-14-2002
Using ROMs for Combinational Logic
Example A 3-input, 4-output combinational logic function:

Inputs Outputs
A2 A1 A0 D3 D2 D1 D0
8 × 4 ROM
0 0 0 1 1 1 0
0 0 1 1 1 0 1
0 1 0 1 0 1 1 I0 A0 D0 Y0
0 1 1 0 1 1 1 I1 A1 D1 Y1
1 0 0 0 0 0 1 A2 D2
POL Y2
1 0 1 0 0 1 0 D3 Y3
1 1 0 0 1 0 0
1 1 1 1 0 0 0

Function: 2-to-4 Decoder with Polarity Control


A2 = Polarity (0 = active Low, 1= active High)
A1, A0 = I1, I0 (2-bit input )
D3...D0 = Y3...Y0 (4-bit decoded output)

EECC341 - Shaaban
#11 Lec # 19 Winter 2001 2-14-2002
Read/Write Memory (RWM / RAM)
• RWM = RAM (Random Access Memory)
• Highly structured like ROMs
• Can store and retrieve data at (relatively) the same speed

• Static RAM (SRAM) retains data in latches (while powered)


• Dynamic RAM (DRAM) stores data as capacitor charge; all
capacitors must be recharged periodically (refresh).

• Volatile Memory: Both Static and Dynamic RAM


• Nonvolatile Memory: Data retained when power lost
= ROMs, NVRAM (w/battery), Flash Memory

EECC341 - Shaaban
#12 Lec # 19 Winter 2001 2-14-2002
Basic Structure of SRAM
2n x b RAM
A0
A1

An-1

DIN 0 DOUT0
DIN 1 DOUT1
DIN b-1 DOUTb-1

CS
OE
WE

• Address/Control/Data Out lines like a ROM (Reading)


+ Write Enable (WE) and Data In (DIN)
(Writing)
EECC341 - Shaaban
#13 Lec # 19 Winter 2001 2-14-2002
One Bit of SRAM

IN D Q OUT IN OUT
SEL
/SEL WR
/WR C

• SEL and WR asserted → IN data stored in D-latch (Write)


• SEL only asserted → D-latch output enabled (Read)
• SEL not asserted → No operation

EECC341 - Shaaban
#14 Lec # 19 Winter 2001 2-14-2002
DIN3 DIN2 DIN1 DIN0
0
IN OUT IN OUT IN OUT IN OUT
SEL SEL SEL SEL
WR WR WR WR
1

8x4 IN
SEL
OUT IN
SEL
OUT IN
SEL
OUT IN
SEL
OUT

WR WR WR WR
SRAM 2
IN OUT IN OUT IN OUT IN OUT
SEL SEL SEL SEL
WR WR WR WR
3
3-to-8 IN OUT IN OUT IN OUT IN OUT
Decoder SEL SEL SEL SEL
WR WR WR WR
4
A2 2 IN OUT IN OUT IN OUT IN OUT
A1 1 SEL SEL SEL SEL
A0 0 WR WR WR WR
5
IN OUT IN OUT IN OUT IN OUT
SEL SEL SEL SEL
WR WR WR WR
6
IN OUT IN OUT IN OUT IN OUT
SEL SEL SEL SEL
WR WR WR WR
7
IN OUT IN OUT IN OUT IN OUT
SEL SEL SEL SEL
WR WR WR WR

/WE
/CS

/OE DOUT3 DOUT2 EECC341


DOUT1 - Shaaban
DOUT1
#15 Lec # 19 Winter 2001 2-14-2002
SRAM Timing
• During READ, outputs are combinational functions of ADDR,
CS, OE (like ROM)
– Inputs can freely change without problems (except for
propagation delay from last input change to output)
• During WRITE, data stored in latches, NOT FF’s.
– Thus, Setup & Hold on Data IN relative to trailing edge of
/WR
• Address must be stable
– for setup time before /WR asserted, and
– for hold time after /WR deasserted
• to prevent “spraying” data to multiple rows

• /WR asserted when BOTH /CS and /WE asserted


• /WR deasserted when EITHER /CS or /WE deasserted
EECC341 - Shaaban
#16 Lec # 19 Winter 2001 2-14-2002
READ Timing (SRAM)
max(tAA, tACS)

ADDR stable stable stable


≥tAA
/CS
t OH
tACS

/OE

tOZ tOE
tAA t OZ t OE

DOUT valid valid valid

Primary Spec
for SRAMs
EECC341 - Shaaban
#17 Lec # 19 Winter 2001 2-14-2002
WRITE Timing (SRAM)
(WE-controlled write) (CS-controlled write)
ADDR stable stable

tCSW tAS tCSW


/CS

tAS tWP tWP tAH


tAH
/WE
tDS tDH tDS tDH

DIN valid valid

EECC341 - Shaaban
#18 Lec # 19 Winter 2001 2-14-2002
Example: 16 x 1 SRAM → 4 x 4 Array
D1

0
2-to-4 IN OUT IN OUT IN OUT IN OUT
SEL SEL SEL SEL
Decoder
WR WR WR WR
1
IN OUT IN OUT IN OUT IN OUT
A1 1
SEL SEL SEL SEL
A0 0
WR WR WR WR
2
IN OUT IN OUT IN OUT IN OUT
SEL SEL SEL SEL
WR WR WR WR
3
IN OUT IN OUT IN OUT IN OUT
SEL SEL SEL SEL
WR WR WR WR
A3-A2
/WE
/CS
2-to-4
Decode
/OE r
S
4-to-1 Mux
E

DO
EECC341 - Shaaban
#19 Lec # 19 Winter 2001 2-14-2002
64K x 8 RAM with 2-D Decoding

9 512 512 512 512 512


9 to 512 ×
A × × • • • ×
Decoder 1024
128 128 128
Array
128 128 128

7 128 128 128


A to 1 to 1 • • • to 1
Mux Mux Mux

D0 D1 D7

EECC341 - Shaaban
#20 Lec # 19 Winter 2001 2-14-2002
Classic DRAM Organization

EECC341 - Shaaban
#21 Lec # 19 Winter 2001 2-14-2002
Logical Diagram of A Typical DRAM

EECC341 - Shaaban
#22 Lec # 19 Winter 2001 2-14-2002
64K x 1 DRAM bit line
word line
256 x 256
Row
array
decoder

1-bit DRAM cell


Row ADDR

8 Control Col ADDR


ADDR / Row register,
/RAS Control Data mux/demux 64K x 1 DRAM
/CAS
8
/WE / ADDR
Din

RAS
CAS Dout
WE

EECC341 - Shaaban
#23 Lec # 19 Winter 2001 2-14-2002
Standard Asynchronous DRAM Read Timing

Valid Data

tRAC: Minimum time from RAS (Row Access Strobe) line falling to the valid data output.
Usually quoted as the nominal speed of a DRAM chip. For a typical 4Mb DRAM tRAC = 60 ns

tRC: Minimum time from the start of one row access to the start of the next.
tRC = 110 ns for a 4Mbit DRAM with a tRAC of 60 ns

EECC341 - Shaaban
#24 Lec # 19 Winter 2001 2-14-2002
Four Key DRAM Timing Parameters
• tRAC: Minimum time from RAS (Row Access Strobe) line
falling to the valid data output.
– Usually quoted as the nominal speed of a DRAM chip
– For a typical 4Mb DRAM t RAC = 60 ns
• tRC: Minimum time from the start of one row access to the
start of the next.
– tRC = 110 ns for a 4Mbit DRAM with a t RAC of 60 ns
• tCAC: minimum time from CAS (Column Access Strobe) line
falling to valid data output.
– 15 ns for a 4Mbit DRAM with a tRAC of 60 ns
• tPC: minimum time from the start of one column access to
the start of the next.
– About 35 ns for a 4Mbit DRAM with a tRAC of 60 ns

EECC341 - Shaaban
#25 Lec # 19 Winter 2001 2-14-2002
Simplified Asynchronous DRAM Read Timing

EECC341 - Shaaban
Source: http://arstechnica.com/paedia/r/ram_guide/ram_guide.part2-1.html
#26 Lec # 19 Winter 2001 2-14-2002
Modern DRAM Timing

• Fast-Page Mode, FPM DRAM (One RAS, multiple CAS)


– Multiple bits of a row can be written before rewrite
– Complex control, but much faster
• Extended Data Out, EDO DRAM (One RAS, multiple CAS)
– Latches the column address so that the next address can be prepared
while the output is read
– Saves ~10ns/read, and increase of 10-15%
– Even more complex control.
• SDRAM - Synchronous DRAM
– Unlike normal DRAM, SDRAM is clocked.
– Multiple signals and banks (row-address registers) allow “pipelined”
operation

EECC341 - Shaaban
#27 Lec # 19 Winter 2001 2-14-2002
Page Mode DRAM: Motivation

EECC341 - Shaaban
#28 Lec # 19 Winter 2001 2-14-2002
Fast Page Mode DRAM: Operation

EECC341 - Shaaban
#29 Lec # 19 Winter 2001 2-14-2002
Simplified Asynchronous Fast Page Mode
(FPM) DRAM Read Timing
FPM DRAM speed rated using tRAC ~ 50-70ns

Typical timing at 66 MHZ : 5-3-3-3


For bus width = 64 bits = 8 bytes Max. Bandwidth = 8 x 66 / 3 = 176 Mbytes/sec

EECC341 - Shaaban
Source: http://arstechnica.com/paedia/r/ram_guide/ram_guide.part2-1.html
#30 Lec # 19 Winter 2001 2-14-2002
Simplified Asynchronous Extended Data Out (EDO)
DRAM Read Timing
• Extended Data Out DRAM operates in a similar fashion to Fast Page Mode
DRAM except the data from one read is on the output pins at the same time
the column address for the next read is being latched in.
EDO DRAM speed rated using tRAC ~ 40-60ns

Typical timing at 66 MHZ : 5-2-2-2


For bus width = 64 bits = 8 bytes Max. Bandwidth = 8 x 66 / 2 = 264 Mbytes/sec

EECC341 - Shaaban
Source: http://arstechnica.com/paedia/r/ram_guide/ram_guide.part2-1.html #31 Lec # 19 Winter 2001 2-14-2002
Synchronous
Dynamic RAM
(SDRAM)
Organization

SDRAM speed is rated at max.


clock speed supported:
66MHZ = PC66
100MHZ = PC100
133MHZ = PC133
150MHZ = PC150

EECC341 - Shaaban
#32 Lec # 19 Winter 2001 2-14-2002
Simplified SDRAM Read Timing

Typical timing at 133 MHZ (PC133 SDRAM) : 4-1-1-1


For bus width = 64 bits = 8 bytes Max. Bandwidth = 133 x 8 = 1064 Mbytes/sec

EECC341 - Shaaban
Source: http://arstechnica.com/paedia/r/ram_guide/ram_guide.part2-6.html #33 Lec # 19 Winter 2001 2-14-2002
RAM Summary
SRAM:
• Fast
• Simple Interface Small systems
or
• Moderate bit density (4 gates → 4 to 6
very fast
transistors) applications
• Moderate cost/bit (cache memory)

DRAM (Dynamic RAM):


• moderate speed Large Memories:
PC’s
• complex interface Mainframes
• High bit density (1 transistor cell)
• Low cost/bit
EECC341 - Shaaban
#34 Lec # 19 Winter 2001 2-14-2002

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