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Unit-I / Part-A

This document outlines the course units and topics for the computer architecture course CS6303. The course is divided into 5 units covering instruction set architecture, CPU performance, floating point representation, pipelining, parallelism, caches, virtual memory, and I/O. Unit 1 discusses instruction sets, addressing modes, and CPU performance calculation. Unit 2 covers floating point representation, addition/subtraction overflow, and multiplication/division algorithms. Unit 3 examines pipelining, hazards, exceptions, and MIPS implementation. Unit 4 presents instruction level parallelism, superscalar processors, and parallel hardware classifications. Finally, unit 5 discusses caches, memory hierarchies, interrupts, and standard I/O interfaces.

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Shyam Sundar
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88 views2 pages

Unit-I / Part-A

This document outlines the course units and topics for the computer architecture course CS6303. The course is divided into 5 units covering instruction set architecture, CPU performance, floating point representation, pipelining, parallelism, caches, virtual memory, and I/O. Unit 1 discusses instruction sets, addressing modes, and CPU performance calculation. Unit 2 covers floating point representation, addition/subtraction overflow, and multiplication/division algorithms. Unit 3 examines pipelining, hazards, exceptions, and MIPS implementation. Unit 4 presents instruction level parallelism, superscalar processors, and parallel hardware classifications. Finally, unit 5 discusses caches, memory hierarchies, interrupts, and standard I/O interfaces.

Uploaded by

Shyam Sundar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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CS6303 Computer Architecture

Department of CSE & IT

2016-2017

UNIT-I / PART-A
1
2
3
4
5
6
7
8

What is Instruction set architecture?

1
2

Describe the MIPS Instruction set in detail with suitable examples.

How CPU execution time for a program is calculated?


Distinguish pipelining from parallelism.
Define Relative mode addressing.
What are the eight great ideas invented by computer architects?
State Amdahls Law.
Define Little Endian arrangement.
What is uniprocessor?

UNIT-I / PART-B

3
4

What is an addressing mode? What is the need for addressing in a computer system? Explain the various
addressing modes with suitable examples.
What are the various logical operations and explain the instructions supporting the logical operations.
i)
ii)

Explain in detail the various components of a computer system with neat diagram.
State the CPU performance equation and discuss the factors that affect performance.

UNIT-II / PART-A
1
2
3
4
5
6
7
8

State the representation of double precision floating point number.


What do mean by Subword Parallelism?
What are the overflow/underflow conditions in addition and subtraction?
Define Full Adder (FA) with logic diagram.
What is guard bit? What are the ways to truncate the guard bits?
Write Restoring and Non-Restoring division algorithm.
Define Chopping.
What is Carry Save addition?

UNIT-II / PART-B
1
2
3
4

Draw and explain the block diagram of floating point adder subtractor unit with an example.
Explain in detail about the multiplication algorithm with suitable example and diagram.
i)
Explain the Booths algorithm for multiplication of signed twos complement numbers.
ii)
Briefly Explain Carry Lookahead adder.
Discuss in detail about the division algorithm in detail with diagram and examples.

UNIT-III / PART-A
1
2
3
4
5
6
7
8

What is a hazard? What are its types?


Define exception.
What is a branch prediction buffer.
What are R-type instructions?
What is meant by branch prediction?
What are the major characteristics of a pipeline?
Define Pipeline speedup.
What is meant by pipeline bubble?

UNIT III / PART-B


1
2
3
4

Explain the basic MIPS implementation with necessary multiplexers and control lines.
i)
Describe the techniques for handling control hazards in pipelined datapath.
ii)
Explain in detail how exceptions are handled in MIPS architecture.
Explain Data path and its control in detail.
Explain how the instruction pipeline works? What are the various situations where an instruction pipeline
can stall? Illustrate with an example.

St. Josephs College of Engineering & St. Josephs Institute of Technology

Page 1 of 2

CS6303 Computer Architecture

Department of CSE & IT

2016-2017

UNIT-IV / PART-A
1

What is Instruction level parallelism?

Define a superscalar processor.

Differentiate between Strong scaling and weak scaling.

What is Loop unrolling?

Define Register renaming.

What is the need for Speculation?

Compare UMA and NUMA multiprocessors.

Define Out of order execution.

UNIT-IV/PART-B
1

Explain in detail Flynns classification of parallel hardware.

Explain the Dynamic & static multiple issue processor and their scheduling with block diagram.

Explain Instruction Level Parallel Processing. State the challenges of parallel processing.

Explain the terms:


i)

Multicore Processor.

ii)

Hardware Multithreading.

UNIT-V/PART-A
1

Define write through.

What is the principle of locality?

Differentiate Programmed I/O and Interrupt I/O.

What is the purpose of the Dirty / Modified bit in Cache memory?

Define Hit ratio.

What is DMA?

How does a processor handle an interrupt?

Compare Static RAM and Dynamic RAM.

UNIT-V / PART-B
1

Draw the typical block diagram of a DMA controller and explain how it is used for direct data transfer
between memory and peripherals?

2
3

What is virtual memory? Explain in detail about how virtual memory is implemented with neat diagram?
i)

Explain mapping functions in cache memory to determine how memory blocks are placed in
cache.

ii)

Explain in detail about the basic structure of a memory level hierarchy with suitable diagram

i)

What is an interrupt? Explain the different types of interrupts and the different ways of
handling the interrupts.

ii)

Explain in detail about any two standard input and output interfaces required to
connect the I/O device to the Bus.

St. Josephs College of Engineering & St. Josephs Institute of Technology

Page 2 of 2

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