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Sequential Circuits

This document discusses sequential circuits and finite state machines. It describes how a Mealy machine works by mapping input sequences to output sequences based on its internal state. The key aspects are: 1) A Mealy machine is defined by its inputs/outputs, states, and functions relating them. 2) It can be implemented using logic gates by encoding its components and constructing combinational logic for its next state and output functions. 3) Flip-flops are used as delay elements to represent the state and ensure the circuit operates correctly over time based on a clock. 4) For the circuit implementation to be correct, the timing of signals through the logic and flip-flops must satisfy setup and hold

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Goutham Ramakrishnan
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40 views11 pages

Sequential Circuits

This document discusses sequential circuits and finite state machines. It describes how a Mealy machine works by mapping input sequences to output sequences based on its internal state. The key aspects are: 1) A Mealy machine is defined by its inputs/outputs, states, and functions relating them. 2) It can be implemented using logic gates by encoding its components and constructing combinational logic for its next state and output functions. 3) Flip-flops are used as delay elements to represent the state and ensure the circuit operates correctly over time based on a clock. 4) For the circuit implementation to be correct, the timing of signals through the logic and flip-flops must satisfy setup and hold

Uploaded by

Goutham Ramakrishnan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Sequential Circuits

Madhav Desai

February 18, 2016

Sequential Functions

A one-sided sequence from a finite set A is a set of elements


{x(0), x(1), x(2), . . .}
and is represented by {x(k)}.

A sequential function f maps sequences to sequences:


f ({x(k)}) = {y (k)}

f is a causal sequential function if, given that


f ({x1 (k)}) = {y1 (k)} and f ({x2 (k)}) = {y2 (k)}, and that
x1 (k) = x2 (k) for k M, it is also true that y1 (k) = y2 (k)
for k M.

Sequential Functions: Finite State Machines

We are interested in those implementations of causal


sequential functions that need a finite amount of memory.

A Mealy machine (Q, , , , , q0 ) is a system with an input


sequence {x(k)} with x(k) , and output sequence {y (k)}
with y (k) , an internal state sequence {q(k)} with
q(k) Q, and the following relations between the sequences
{x(k)}, {y (k)} and {q(k)}.
q(k + 1) = (x(k), q(k))
y (k) = (x(k), q(k)
Here, , , Q are finite sets and , are functions from
Q Q and Q respectively.

Implementing a Mealy Machine

The sets , , Q are encoded with bit-vectors (note: there


are many possible encodings). After this step, x(k), y (k) and
q(k) are viewed as bit-vectors. Thus, and become
Boolean functions which we know how to implement as
combinational functions. We implement the following
y (k) = (x(k), q(k))
nq(k) = (x(k), q(k))

where nq(k) is introduced to represent the next state.


We need a concept of a sequential delay element to implement
q(k + 1) = nq(k)

Some questions:

How are the instants k defined?


Using logic gates, how can we construct the delay element?
Under what conditions will a logic circuit faithfully implement
the equations describing a Mealy machine?

Defining the time instants: a clock

To define the time instants k, we can use a periodic


waveform, for example a square wave, and associate the rising
edges of the square wave with the time-instants.

The simplest clock is a square wave with 50% duty-cycle. We


denote the period of the clock by T .

If x is a wire in a logic circuit, then x(k) is the voltage on the


wire at the k th rising edge on the clock.

A delay element: the data flip-flop (DFF)

Two inputs: a data input d, a clock input clk, one output q.

The d input is sampled at the rising edge of clock, and


sampled value appears at q after a delay (dclkq ).

The data input must be stable for a period S before the


sampling clock edge and a period H after the sampling clock
edge (the setup time S and the hold time H).

Implementation of a Mealy machine

Encode the states in Q using a set of state variables


s = (s0 s1 . . . sk ). You will need at least log2 |Q| state variables.

Encode the input and output symbol sets and using


variables x = (x0 x1 . . . xm ) and y = (y0 y1 . . . yp ) repectively.

Implement the next-state and output functions and using


logic gates.

Use one flip-flop for each state variable and connect the
next-state variables to the flip-flop inputs (outputs are
connected to state variables).

Implementation of a Mealy machine


x(k)

y(k)
lambda
(combinational logic)

s(k)

delta

ns(k)

Clock
Figure: Mealy machine circuit structure

Implementation of a Mealy machine: timing correctness

The paths of interest start from clock, proceed through a


D-FF (the launch D-FF), continue through combinational
logic and end at the input of a D-FF (the capture D-FF).

Let m and M be the minimum and maximum possible delays


of paths of interest (including the Clock Q delay of the
launch flip-flop.

The circuit will correctly implement the Mealy machine if


m H
M T S

If the clock at the capture flip-flop is delayed by an amount


relative to the clock at the launch flip-flop, then
m H +
M T (S )

Summary: design procedure for a Mealy machine

Choose input, state and output encodings.

Some common encodings: binary and variants (e.g. Gray


codes), one-hot encodings, k-hot encodings etc.

Implement the and function blocks.

Introduce the delay elements to close the loop.

Confirm that the circuit works correctly at some clock period


(and calculate the minimum clock period and circuit setup
and delay times).

Signoff: Specification of a CMOS positive-edge-triggered


Sequential Circuit Block
To finish the design process, you must characterize your
implementation and find:
The input set-up time relative to the rising edge of the clock
(could be different for each input).
The minimum and maximum delays from an input of the
system to an input of a flip-flop (the input-to-flop delay,
which could be different for each input).
The minimum and maximum values of the clock to output
delay (could be different for each output bit, both minimum
and maximum delays should be specified).
The minimum and maximum values of the clock to flip-flop
input delay.
The minimum and maximum values of the input to output
delay.
For CMOS circuits, the input capacitance at all inputs
(including clock) and the maximum load capacitances that
can be connected at the outputs.

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