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Floating Nodes and Capacitors: 599 5.27 Spice Notes

This document discusses several important considerations for running SPICE simulations successfully, including: 1) Setting appropriate tolerance values for voltage and current based on the circuit's operating levels to ensure convergence. 2) Adding high-value resistors across floating nodes and capacitors to define a DC path to ground. 3) Including finite resistances in series with voltage sources and inductors to prevent infinite currents from occurring. 4) Defining behavioral models carefully using mathematical expressions and line breaks when needed for accurate simulations.

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21 views1 page

Floating Nodes and Capacitors: 599 5.27 Spice Notes

This document discusses several important considerations for running SPICE simulations successfully, including: 1) Setting appropriate tolerance values for voltage and current based on the circuit's operating levels to ensure convergence. 2) Adding high-value resistors across floating nodes and capacitors to define a DC path to ground. 3) Including finite resistances in series with voltage sources and inductors to prevent infinite currents from occurring. 4) Defining behavioral models carefully using mathematical expressions and line breaks when needed for accurate simulations.

Uploaded by

opacheco
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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599

5.27 Spice notes

current to amps of drain current. The default values of VNTOL (for voltage)
and ABSTOL (for current) are set to be generally appropriate for low current
systems, but if you are interested in high power circuits then it is probably of
little signicance whether the gate current is known to a picoamp resolution
in comparison with a drain current of many amps (ABSTOL should be no
more than 109 of the highest current). It is sometimes helpful to add highish
value resistors around the FET to increase currents associated with the gate
but without aecting actual operation. Diodes can also cause problems and
often need to be paralleled with high value resistors to enable successful bias
point computation. For a full discussion of matters relating to convergence
reference may be made to Vladimirescu (1994, Chapter 10). The various settings are to be found under ANALYSIS/SETUP/OPTIONS which will
provide a list of parameters and their (default) values, and the means to alter
them. Do not set RELTOL greater than 0.01. Doing so may seriously aect
the simulation. Options ITL1 and ITL2 can often be increased to help nd an
initial bias point.
(c) Floating nodes and capacitors: All nodes must have some d.c. path to
common. If not, the initial bias point cannot be determined and an error will
be reported. Capacitors are the main culprits and you will need to add, if necessary a very large resistor, e.g. 1 G, to allow simulation to proceed. Diodes
can also cause the same problem and can be shunted or otherwise treated if
need be.
(d) Series voltage sources and inductors: Any voltage source must feed a nite
(rather than zero) impedance as otherwise you will have an innite current
and PSpice will object. Inductors are handled like voltage sources and will
lead to the same objection. Thus you should always include some resistance
in series with an inductor that can represent its inescapable resistance both for
the above reason and since with perfect inductors you may get perfect but
impossible outputs.
(e) Analog behavioural model (ABM) devices: There a number of these devices
providing either voltage or current output with either none, one or two input
pins. The function of the device is dened by a user-written mathematical
algorithm, so they are very exible. The simplest, for example, appears with
only one pin (for the output signal), but there is an implied hidden pin connected to common. The prescription is typed in in the normal form for mathematical expressions and it is wise to use dening brackets to ensure you get
what you intended. The text can continue over several lines in the attributes
input window and the lines are simply concatenated. An example is given in
Section 5.15 where we wished to dene a particular form of pulse. An ABM
denition will accept reference to V(netname) or to I(Vdevice) but not to say
I(R#).

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