28/04/2015

VLSI placement: CMOS part 7

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VLSI placement
This is a blog for people preparing for placement and company interviews in the field of vlsi and electronics. this blog contains important
questions which are generally asked in company written and interview exams
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CMOS part 7
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Dynamic logic
Dynamic logic requires a minimum clock rate fast enough that the output state of each dynamic gate is used before it leaks
out of the capacitance holding that state, during the part of the clock cycle that the output is not being actively driven.
Static logic has no minimum clock ratethe clock can be paused indefinitely. While it may seem that doing nothing for long
periods of time is not particularly useful, it leads to two advantages:
being able to pause a system at any time makes debugging and testing much easier, enabling techniques such
as single stepping.
being able to run a system at extremely low clock rates allows low-power electronics to run longer on a given
battery.

Advantages
Dynamic logic (properly designed) is over twice as fast as normal logic.

Most electronics running at over 2 GHz these days uses dynamic logic, although some manufacturers, such as
Intel, have completely switched to static logic to save on power[2]. However, dynamic logic too has techniques for
reducing power consumption. A dynamic logic circuit running at 1/2 voltage could consume 1/4 the power of
normal.
Smaller area

NAND gate using Dynamic logic.

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The dynamic logic circuit requires two phases. The first phase, when Clock is low, is called the setup phase or the
precharge phase and the second phase, when Clock is high, is called the evaluation phase. In the setup phase, the output
is driven high unconditionally (no matter the values of the inputs A and B). The capacitor, which represents the load
capacitance of this gate, becomes charged. Because the transistor at the bottom is turned off, it is impossible for the output
to be driven low during this phase.
During the evaluation phase, Clock is high. If A and B are also high, the output will be pulled low. Otherwise, the output
stays high (due to the load capacitance).
Problem
Dynamic logics, this logic is subject to the charge-sharing problem
Monotonocity -> solve by domino
In practical use, however, dynamic logic still greatly increases the number of transistors that are switching at any given
time, which greatly increases power consumption over static CMOS.
Only non inverting

Domino logic
Dynamic logic has a few potential problems that static logic does not. For example, if the clock speed is too slow, the
output will decay too quickly to be of use.
A popular implementation is domino logic.
Domino logic is a CMOS-based evolution of the dynamic logic techniques which were based on either PMOS or NMOS
transistors. It allows a rail-to-rail logic swing. It was developed to speed up circuits.

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VLSI placement: CMOS part 7

In Dynamic Logic, a problem arises when cascading one gate to the next. The precharge "1" state of the first gate may
cause the second gate to discharge prematurely, before the first gate has reached its correct state. This uses up the
"precharge" of the second gate, which cannot be restored until the next clock cycle, so there is no recovery from this error.
There are various solutions to the problem of how to cascade dynamic logic gates. One solution is Domino Logic, which
inserts an ordinary static inverter between stages.

Important Domino Logic features include:

1.
2.
3.
4.
5.

They have smaller areas than conventional CMOS logic (as does all Dynamic Logic).
Parasitic capacitances are smaller so that higher operating speeds are possible.
Operation is free of glitches as each gate can make only one transition.
Only non-inverting structures are possible because of the presence of inverting buffer.
Charge distribution may be a problem.

embedded system core - 2

embedded system core - 1
microprocessor part 3
embedded hardware questions
HR rount part 1
Digital logic design - part 1
VLSI testing part 3
Computer architecture Part 3
Computer architecture Part 2
Computer architecture Part 1
vlsi-timing interview question and
answer - part 6...

General Domino logic

vlsi-timing interview question and

answer - part 5...
vlsi-timing interview question and
answer - part 4...
vlsi-timing interview question and
answer - part 3...
vlsi-timing interview question and
answer - part 2...
vlsi-timing interview question and
answer - part 1...
CMOS part 9
CMOS part 8
CMOS part 7
CMOS part 6
CMOS part 5
CMOS part 4
CMOS part 3
CMOS interview and job questions
part 2
VLSI - STA advance terms
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PAL

Any body want to be contributor to this blog :

contact :
sumit.raj.iiit@gmail.com

PAL devices consisted of a small PROM (programmable read-only memory) core and additional output logic used to
implement particular desired logic functions with few components. March 1978
PAL devices have arrays of transistor cells arranged in a "fixed-OR, programmable-AND" plane used to implement "sum-ofproducts" binary logic equations for each of the outputs in terms of the inputs and either synchronous or asynchronous
feedback from the outputs.
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A programmable logic array (PLA) is a programmable device used to implement combinational logic circuits. The PLA has
a set of programmable AND gate planes, which link to a set of programmable OR gate planes, which can then be
conditionally complemented to produce an output. This layout allows for a large number of logic functions to be synthesized
in the sum of products (and sometimes product of sums) canonical forms.

Comments

PLDs
A programmable logic device or PLD is an electronic component used to build reconfigurable digital circuits. Unlike a

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Contributors

satish verma
RaJ

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VLSI placement: CMOS part 7

logic gate, which has a fixed function, a PLD has an undefined function at the time of manufacture. Before the PLD can be
used in a circuit it must be programmed, that is, reconfigured.
Before PLDs were invented, read-only memory (ROM) chips were used to create arbitrary combinational logic functions of a
number of inputs.

PLD types can classified into the following groups

PROMs (Programmable Read Only Memory) - offer high speed and low cost for relatively small
designs
PLAs (Programmable Logic Array) - offer flexible features for more complex designs
PAL/GALs (Programmable Array Logic/Generic Array Logic) - offer good flexibility and are
faster and less expensive than PLAs

rishabh

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A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer
after manufacturinghence "field-programmable". The FPGA configuration is generally specified using a hardware
description language (HDL), similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were
previously used to specify the configuration, as they were for ASICs, but this is increasingly rare).

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Microcode
(1) The lowest-level instructions that directly control a microprocessor. A single machine-language instruction typically
translates into several microcode instructions.
In modern PC microprocessors, the microcode is hardwired and can't be modified. Some RISC designs go one step further
by completely eliminating the microcode level so that machine instructions directly control the processor. At the other end of
the spectrum, some mainframe and minicomputer architectures utilize programmable microcode. In this case, the
microcode is stored in EEPROM, which can be modified. This is called microprogramming.
Microcode simplified the job by allowing much of the processor's behaviour and programming model to be defined via
microprogram routines rather than by dedicated circuitry. Even late in the design process, microcode could easily be
changed, whereas hard wired CPU designs were very cumbersome to change, so this greatly facilitated CPU design.

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Example : Jump and Add, block memory transfer

Always used in CISC, but RICS dont use microcode.

Depletion-mode MOSFETs
There are depletion-mode MOSFET devices, which are less commonly used than the standard enhancement-mode devices
already described. These are MOSFET devices that are doped so that a channel exists even with zero voltage from gate to
source. In order to control the channel, a negative voltage is applied to the gate (for an n-channel device), depleting the
channel, which reduces the current flow through the device. In essence, the depletion-mode device is equivalent to a
normally closed (on) switch, while the enhancement-mode device is equivalent to a normally open (off) switch.[1]
Due to their low noise figure in the RF region, and better gain, these devices are often preferred to bipolars in RF front-ends
such as in TV sets.

Depletion mode is shown by solid lines.

Depletion mode
The depletion mode MOSFET can operate in a depletion mode, where a negative gate voltage increases the layer and hence reduces
the source-drain current, or in an enhancement mode, where a positive gate voltage reduces the depletion layer and hence increases
the source-drain current.

Leakage current
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VLSI placement: CMOS part 7

There are 3 types of leakage:

Higher subthreshold conduction
As MOSFET geometries shrink, the voltage that can be applied to the gate must be reduced to maintain reliability. To
maintain performance, the threshold voltage of the MOSFET has to be reduced as well. As threshold voltage is reduced, the
transistor cannot be switched from complete turn-off to complete turn-on with the limited voltage swing available; the circuit
design is a compromise between strong current in the "on" case and low current in the "off" case, and the application
determines whether to favor one over the other. Subthreshold leakage (including subthreshold conduction, gate-oxide
leakage and reverse-biased junction leakage), which was ignored in the past, now can consume upwards of half of the total
power consumption of modern high-performance VLSI chips.
Increased gate-oxide leakage
The gate oxide, which serves as insulator between the gate and channel, should be made as thin as possible to increase
the channel conductivity and performance when the transistor is on and to reduce subthreshold leakage when the transistor
is off. However, with current gate oxides with a thickness of around 1.2 nm (which in silicon is ~5 atoms thick) the quantum
mechanical phenomenon of electron tunneling occurs between the gate and channel leads to gate-oxide leakage, leading to
increased power consumption.
Increased junction leakage
To make devices smaller, junction design has become more complex, leading to higher doping levels, shallower junctions,
"halo" doping and so forth,[27][28] all to decrease drain-induced barrier lowering (see the section on junction design). To keep
these complex junctions in place, the annealing steps formerly used to remove damage and electrically active defects must
be curtailed[29] increasing junction leakage. Heavier doping is also associated with thinner depletion layers and more
recombination centers that result in increased leakage current, even without lattice damage.

Inverter layout
Lmin = 2* lambda
180nm then Lmin = 180nm and lambda = 90nm,

Typically we use P substrate

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Posted by RaJ at 12:18 PM

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Labels: CMOS and MOSFETs

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Sumit Raj, IIIT hyderabad. Simple template. Powered by Blogger.

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