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Circuit Description: Cenita, Villy Joi M. Design #2 Bsece / 3 Year 3ECE-A

This document describes the design of a two-stage amplifier circuit with the following specifications: - A low cutoff frequency (fL) of 20Hz - An AC source of 1kHz - Source resistance of 600ohms It provides the component value calculations to achieve the 20Hz fL for each stage using capacitors at the input, output, and bypass. Simulation results show the low and high frequency responses match the calculated values except for some deviation in the high frequency response of the first stage. Components used include resistors, capacitors, and two NPN transistors.

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Villy Cenita
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45 views9 pages

Circuit Description: Cenita, Villy Joi M. Design #2 Bsece / 3 Year 3ECE-A

This document describes the design of a two-stage amplifier circuit with the following specifications: - A low cutoff frequency (fL) of 20Hz - An AC source of 1kHz - Source resistance of 600ohms It provides the component value calculations to achieve the 20Hz fL for each stage using capacitors at the input, output, and bypass. Simulation results show the low and high frequency responses match the calculated values except for some deviation in the high frequency response of the first stage. Components used include resistors, capacitors, and two NPN transistors.

Uploaded by

Villy Cenita
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Cenita, Villy Joi M.

#2

Design

BSECE / 3rd Year


3ECE-A

1. Circuit Description
This documentation is the second part of my previous design. Using the
same circuit, I need to calculate the right values of my capacitors with a
source resistance and an AC source with 1kHz to have a cut-off frequency of
20Hz. I also need to have a source resistance after the AC source. I need to
have a low cut off frequency and observe/calculate the high cut off frequency
at a given value of input frequency by analysis and computation. By using
the bode plotter, I can see the frequency response of my amplifier.
2 - Schematic Diagram

3 - Design and Analysis


Required Specification:
o fL = 20Hz
o AC source with 1kHz frequency
o Compute the value of capacitors used at input, interstage (for multistage), bypassed, and output coupling
o Analyze the high frequency response
o Source Resistance of 600ohm
Computations:
RS = 600
re 1st stage= 33

Low Frequency Response:

re 2nd stage = 7.61

C1 = 1/2(fL)(Zi+RS)

Cbc = 12pF

=1/2(20Hz)
(17116+600)=0.449F(use 0.47F)

Cbe = 5pF
Cce = 16pF
Cw = 10pF
Beta = 260
st

1 stage

fL(C1) = 1/2(C1)(Zi+RS)

= 1/2(0.47uF)(17696 ) =

19.14Hz
C2(coupling) = 1/2(fL)(re)

Zi = Rth ll B(RE) = 17116

= 1/2(20Hz)(33 ) = 241.14uF
(use 220uF)

Zo = re = 33

fL(C2) = 1/2(C2)(re)

2nd stage

= 1/2(220uF)(33) = 21.9Hz

Zi = Rth II B(re) = 1661

C3(bypass) = 1/2(fL)(re)

Zo = Rc = 2.4k

= 1/2(20Hz)(7.31) = 1.09mF (use


1mF)
fL(C3) = 1/2(C3)(re)

= 1/2(1mF)(7.31) =

21.77Hz
C4 = 1/2(fL)(Zo)
= 1/2(20Hz)(2400) = 3.32uF
(use 3.3uF)
fL(C4) = 1/2(C4)(Zo)

= 1/2(3.3uF) (2400) =

20.1Hz

High Frequency Response


st

1 Stage

High Frequency Response


2nd Stage

Ci(total) = Cbe+ Cw
= 5pF+10pF

Ci(Miller) =Cbc (Av+1) = 12pF


(315.4+1)

= 15pF
fHi = 1/2(Cintotal)(ZiIIRS)

= 3.7968nF
Ci(total) = Cbe+Ci(Miller)+Cw

=1/2(15pF)(17116II600)

= 5pF+3.7968nF+10pF

= 18.3MHz

= 3.8118nF

Co(total) = Cce+ Cw
= 16pF+10pF
= 26pF
fHo = 1/2(Cototal)(ZoIIZi)
= 1/2(26pF)(2400)
= 189.2MHz

fHi = 1/2(Cintotal)(Zi)
=1/2(3.8118nF)(1661) =
25.14kHz

Co(Miller)=Cbc(1+(1/Av))
=12pF(1+(1/315.4))=
12.04pF
Co(total) = Cce + Co(Miller) + Cw

Mid Gain (dB) =20 log( )


Mid Gain (dB) = 20 log(1) = 0 dB

= 16pF+12.04pf + 10pF =
38.04pF

Cut-off Gain (dB) = 20 log(0.707 ) fHo = 1/2(Cototal)(Rc)


Cut-off Gain (dB) = 20 log(0.707 x1)=
-3dB

= 1/2(38.04pF)(2400)
= 1.74MHz
Mid Gain (dB) =20 log( )
Mid Gain (dB) = 20 log(315.4) =
49.98 dB
Cut-off Gain (dB) = 20 log(0.707 )

Cut-off Gain (dB) = 20 log(0.707 x


315.4)= 46.97dB

4. Simulation Results

Low Frequency Response 1st Stage


Response 2nd Stage

Low

Cut-off Gain: -3.19dB -3dB


46.97dB

Cut-off Gain: 46.883dB

Cuf-off Frequency: 20.309 Hz 20Hz


22.855 Hz 20Hz

Cuf-off Frequency:

High Frequency Response 1st Stage


Response 2nd Stage

High Frequency

Cut-off Gain: -3.031dB -3dB


46.97dB
Cuf-off Frequency: 1.537 MHz (not 18.3MHz)
1.701MHz 1.74MHz

Frequency

Cut-off Gain: 47.002dB


Cuf-off Frequency:

5 - Discussion of Results
The analysis and simulation result of the frequency response is almost similar when it
comes to calculation values but the bode plot graph is not that good compare to the
ideal bode plot graph. It is because of the multisim simulator simulating the circuit in
an ideal environment.
6. List of materials

Resistors 20% tolerance 1/4watt


2 105k
2 21k
1 3k
1 2.4k
1 - 600
Capacitor
1 0.47uF
1 220uF
1 1mF
1 3.3uF
Transistor
2 NPN BC337

7. Specifications

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