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4541 775 9 CGRA Introduction PDF

This document introduces coarse-grained reconfigurable architectures (CGRAs) which provide high performance computation at low power compared to general purpose processors. CGRAs consist of arrays of larger programmable blocks and routing resources compared to fine-grained FPGAs. Several CGRA examples are described, including PipeRench, MorphoSys, and ADRES, which combine CGRAs with VLIW processors. Compiling for CGRAs typically involves modulo scheduling without control flow, followed by placement and routing of operations on the architecture.

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0% found this document useful (0 votes)

205 views18 pages

4541 775 9 CGRA Introduction PDF

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chayanpathak

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4541.

775
TopicsonCompilers

Introduction
to
CGRA

Spring2011
IntroductiontoCGRA

ReconfigurableArchitectures

reconfigurablehardware(reconfigware)
implementspecifichardwarestructuresdynamicallyandondemand

highperformanceatlowpower

outperformgeneralpurposeprocessorsinmanyapplications
byprovidingspacial,parallelandspecializedcomputation

veryinterestingformobile&embeddedsystems

typicalorganization

logicblocksina2Darray

routingresources
IntroductiontoCGRA

ReconfigurableArchitectures

reconfigurablehardware(reconfigware)
bestknownreconfigurablearchitectures:FPGAs

configurationblock:bitlevel

dataroutingthemajorchallenge

reconfigurationisslow

automaticmappingofsequentialCprogramsverydifficult

usuallypartofaSoCdesign

(imagesource:CompilingforReconfigurableComputing:ASurvey,CSUR)
IntroductiontoCGRA

ReconfigurableArchitectures

finegrainedvs.coarsegrainedreconfigurablearchitectures
finegrained

programmableblocksandroutingresourcesatthebitlevel

canbuildanything
12bitfixedpointarithmeticforasignalprocessingapp
14bitbutterflyroutingnetworkforaFFT

coarsegrainedreconfigurablearchitectures(CGRA)

sometimesalsoreferredtoascoarsegrainedreconfigurablearray

programmableblocksandroutingresources>1bit,e.g.,32bit

lessflexiblethanfinegrainedreconfigurablearchitectures

but
easiertoprogram
fastreconfiguration
IntroductiontoCGRA

ReconfigurableArchitectures

finegrainedvs.coarsegrainedreconfigurablearchitectures
finegrained

coarsegrainedreconfigurablearchitectures(CGRA)

(imagesource:CompilingforReconfigurableComputing:ASurvey,CSUR)
IntroductiontoCGRA

Coarsegrainedreconfigurablearchitectures

programmabilityandflexibility
runmultiplekernelsonthesame
silicondie
supportseveralstandards
CGRA upgradability
fasttimetomarket

(source:FineandCoarseGrainReconfigurableComputing,Springer)
IntroductiontoCGRA

Coarsegrainedreconfigurablearchitectures
Power
Efficiency
(GOPS/W)

ASIC

100
efficiency
ASIP
CGRA lowpowerconsumption
highperformance
10

DSP

1
0.1 1 10
Performance
(GOPS)
IntroductiontoCGRA

Coarsegrainedreconfigurablearchitectures

PipeRench(Goldsteinetal.,1999)
naturallymapapplicationstagestoapipelinedreconfigurable
architecture

virtualpipelinestages

physicalpipelinestages

(imagesource:PipeRench:AReconfigurableArchitectureandComputer,IEEE)
IntroductiontoCGRA

Coarsegrainedreconfigurablearchitectures

PipeRench(Goldsteinetal.,1999)
architecturedescriptionflexible
sourcelanguage:dataflowintermediatelanguage

(imagesource:PipeRench:AReconfigurableArchitectureandComputer,IEEE)
IntroductiontoCGRA

Coarsegrainedreconfigurablearchitectures

MorphoSys(Singhetal.,2000)
8/16bitFU(reconfigurablecell)array

(imagesource:MorphoSys:AnIntegratedReconfigurableSystemforDataParallelandComputationIntensiveApplications,IEEETC)
IntroductiontoCGRA

Coarsegrainedreconfigurablearchitectures

MorphoSys(Singhetal.,2000)
detailviewofoneRC(reconfigurablecell)

(imagesource:MorphoSys:AnIntegratedReconfigurableSystemforDataParallelandComputationIntensiveApplications,IEEETC)
IntroductiontoCGRA

Coarsegrainedreconfigurablearchitectures

MorphoSys(Singhetal.,2000)
configurationofanRC

(imagesource:MorphoSys:AnIntegratedReconfigurableSystemforDataParallelandComputationIntensiveApplications,IEEETC)
IntroductiontoCGRA

Coarsegrainedreconfigurablearchitectures

MorphoSys(Singhetal.,2000)
systemintegration

(imagesource:MorphoSys:AnIntegratedReconfigurableSystemforDataParallelandComputationIntensiveApplications,IEEETC)
IntroductiontoCGRA

Coarsegrainedreconfigurablearchitectures

ADRES(Meietal.,2003)
combinedVLIW/CGRAprocessor

(imagesource:ADRES:AnArchitecturewithTightlyCoupledVLIWProcessorandCoarseGrainedReconfigurableMatrix,SpringerLNCS)
IntroductiontoCGRA

Coarsegrainedreconfigurablearchitectures

ADRES(Meietal.,2003)
reconfigurablecell

(imagesource:ADRES:AnArchitecturewithTightlyCoupledVLIWProcessorandCoarseGrainedReconfigurableMatrix,SpringerLNCS)
IntroductiontoCGRA

Coarsegrainedreconfigurablearchitectures

ADRES(Meietal.,2003)
VLIW/CGAinteraction

(imagesource:ADRES:AnArchitecturewithTightlyCoupledVLIWProcessorandCoarseGrainedReconfigurableMatrix,SpringerLNCS)
IntroductiontoCGRA

CompilingforCGRA

typicallynocontrolflow
innermostloops
ifconversion

moduloscheduling
softwarepipelining
computeIIbasedondataflowgraph

placement&routing
mappingofthedataflowgraphtothearchitecturegraph
severaltechniques

nodecentric:simulatedannealing

edgecentric
IntroductiontoCGRA

FurtherReading:

CompilingforReconfigurableComputing:ASurvey
J.Cardoso,P.Diniz,M.Weinhardt,ACMComputingSurveys

Piperench:AReconfigurableArchitectureandComputer
S.Goldsteinetal.,IEEEComputer

MorphoSys:anintegratedreconfigurablesystemfordataparalleland
computationintensiveapplications
H.Singh,IEEETransactionsonComputers

ADRES:AnArchitecturewithTightlyCoupledVLIWProcessorand
CoarseGrainedReconfigurableMatrix
B.Meietal.,SpringerLNCS

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4541 775 9 CGRA Introduction PDF

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