International Journal of Engineering and Technical Research (IJETR)

ISSN: 2321-0869 (O) 2454-4698 (P), Volume-5, Issue-2, June 2016

Implementation of High Performance FIR filter using

High Speed & Low Area Multiplier
Bhawana Datwani, Himanshu Joshi

performance system, requires components which are as small

Abstract In current scenario, low power consumption and high as possible and covering low space.
speed are some of the most important criteria for the fabrication
of DSP systems and any high performance systems. Optimizing
the speed and power of the multiplier is a major design issue. II. FIR FILTER THEORY
However, area and speed are usually conflicting constraints so
that improving speed results mostly in larger areas. In our Finite Impulse Response (FIR) filter are type of digital
project we are trying to determine the best solution to this filter and consist of impulse response among non-recursive
problem by comparing a few multipliers and choosing perfect digital filters which is finite in length [3]. FIR filters are
multiplier for implementation of FIR filter. So in this paper
non-recursive digital filters such that the current output is
designing a FIR filter, which is efficient not only in terms of
delay and speed but also in terms of power. The simulations have
calculated solely from the current and previous input values.
been carried out using the Xilinx ISE tool. FIR filter has been selected for this thesis due to their good
characteristics.[3][9] FIR filter has no feedback and its
Index Terms. DSP, FIR filter, Multiplier, Xilinx ISE input-output relation is given by

(1)
I. INTRODUCTION Here, x [n] and y [n] are the filter input and filter output
The multiplier [1]-[3], [5] is one of the key hardware blocks in respectively, a [k] is the filter coefficients, N is the filter
most of high performance systems such as digital signal coefficient number. The denotes summation from = 0 to k
processors and microprocessors [2]. With the fast advances in = n where n is the number of feed forward taps in the FIR
technology, many researchers are working on the most filter. Transfer function of FIR filter can be represented as [3]
efficient multipliers [5]. They key requirement is not only [9]:
higher speed and lower power consumption but also
occupying reduced silicon area. This makes them well-suited (2)
for various complex and portable VLSI circuit [6]
implementations. However, the reality is that the area and The frequency response realized in the time domain is of
speed are two conflicting performance factors. Thus, more concern for FIR filter realization (both hardware and
increased speed always results in larger area. In this paper, we software). The transfer function can be calculated via the
found a better trade-off between the two, by realizing a z-transform of a FIR filter frequency response [9].
marginally decreased delay which increases the speed
performance [3] through a small rise in area such that increase
III. DIGITAL ADDERS
in the number of transistors [6]. The new design lowers the
delay of the widely approved Wallace tree multiplier [7]. On
the conventional multiplier, the structural optimization is In digital electronics, adder is a type of digital circuit that
performed, in such a way that the latency of the total circuit performs addition of two numbers. As described in [10], many
reduces significantly. The Wallace tree basically multiplies computers and other kinds of processors, adders are common
two unsigned integers [7]. In this project we compare the not only in the ALU(s), but also in other parts of the
working & the characteristics of different multiplier [8] processor, where they calculate addresses, table indices, and
individually and then choosing the perfect multiplier by many more.
implementing each of them separately in FIR filter. A. Ripple Carry Adder
The parallel multipliers like radix 2 and radix 4,Wallace
multiplier[8] perform the computations using less number A ripple carry adder is a digital circuit that produces the
adders and thus have lesser iterative steps which results in arithmetic sum of two binary numbers. Full adders [12] are
requiring lesser space as compared to the serial multiplier. cascaded to construct ripple carry adder, with the carry output
Here now we are comparing Booth and Wallace multiplier from each full adder linked to the carry input of the next full
[13] [15] to find the efficient one. Area is a very important adder in the chain. As shown in Figure 1 the interconnection
factor because in the fabrication of chips [1] and high of four full adder (FA) circuits to provide a 4-bit ripple carry
adder [9] [12]. It can be seen from Figure the input is coming
from the right side because the first cell traditionally
Manuscript received .
Bhawana Datwani, M.Tech. Scholar, Department of ECE, Jagannath
represents the least significant bit (LSB). Bits a0 and b0 in the
University, Jaipur, India, (e-mail: bhawana2190@gamil.com). figure represent the least significant bits of the numbers to be
added. The s0-s3 expressing the sum output.
Himanshu Joshi, Assistant Professor, Department of ECE, Jagannath
University, Jaipur, (Himanshu.joshi@jagannathuniversity.org)

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 Implementation of High Performance FIR filter using High Speed & Low Area Multiplier

Figure 1 Ripple Carry Adder

B. Carry Look Ahead Adder

Carry- Look Ahead Adder (CLA) is designed to eliminate Figure 3 Carry Select Adder
the latency introduced by the repelling effect of the carry bits
in RCA. The CLA improves speed by reducing the amount of D.Carry Save Adder
time required to determine carry bits [12]. The concepts of
A Carry Save Adder (CSA) is type of digital adder[9][10]
generating (G) and propagating (P) carries is used in CLA.
which generates low carry signal propagation delay, but in
Two signals called P and G are used in this adder for each bit
place of adding two input numbers to a single sum output, it
position [9] [12]. The P and G are shown below.
adds three input numbers to an output pair of numbers. When
its two outputs are then summed by using a carry-look a head
Ci+1 = Gi + Pi. Ci (3)
or ripple-carry adder[12], we obtain the sum of all three
inputs.
Here, Gi = Ai. Bi and Pi = (Ai xor Bi)
Si = Ai xor Bi xor Ci = Pi xor C i.
The Si and Ci+1 represent the sum and carry for ith full adder
IV. DIGITAL MULTIPLIERS
respectively.
A Binary multiplier is an electronic digital hardware device
used in digital electronics or a computer or other electronic
device to perform rapid multiplication of two numbers in
binary representation [5] [11]. It is built using binary adders
[10]. Multiplier plays an important role in todays digital
signal processing and various other applications [2]. In high
performance systems such as microprocessor, DSP etc.
addition and multiplication of two binary numbers is essential
and most often used in arithmetic operations. Statics shows
that addition and multiplication is performed in almost 70%
instructions in microprocessor and most of DSP algorithms
perform [2].

Figure 2 Carry Look ahead Adder A. Array Multiplier

The carry-look ahead adder can be splited in two modules:

(1) The Partial Full Adder , PFA, which generates Si, Pi and
Gi.
(2) The Carry Look-Ahead Logic, which generates the
carry-out bits.

C. Carry Select Adder

A Carry Select Adder employ a logic element that evaluate
the (n+1) bit addition of two n-bit numbers. The carry select
adder [10] [12] usually includes two ripple carry adder and a
multiplexer. With a carry select adder sum of two n-bit
numbers is done by using two adders (therefore two ripple
carry adders) in order to perform the adding up twice, one tie
with the appropriation of the carry existence zero and the Figure 4 Array Multiplier
other assuming one.

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 International Journal of Engineering and Technical Research (IJETR)
ISSN: 2321-0869 (O) 2454-4698 (P), Volume-5, Issue-2, June 2016
Array multiplier is well recognized because of its regular Table 3Partial Products generation
structure. Multiplication process is based on repeated
addition and shifting procedure. Each partial product is
generated by the multiplication of the multiplicand with one
multiplier digit then these partial product are shifted
according to their bit sequences and then added [9] [13]. The
summation can be performed with normal carry propagation
adder. Total N-1 adders are required where N is the no. of
multiplier bits. The n-operand array consists of n-2
compressor.
Table 4 Final Shift
B. Radix-2 Booth Multiplier
This is technique that allows for smaller, faster
multiplication circuits by recoding the numbers that are
multiplied. Partial products is reduced by factor 2which
implies that it allows only half of product which is needed
during computation. The Booths algorithm is for multiplying
binary signed number in 2s complement [9] [13]-[14]. Let R
and M are the multiplicand and multiplier respectively; and
let n and q represent the number of bits in R and M. Take the
Arithmetically shift the value calculate in step1-4 by signal
2s complement of R which is given as R. For calculation,
place of right.
make the table of U, V, X and X-1 variable, respectively.
b) Take U & V together and arithmetically right shift which
Step1: store the sign bit of 2s complement number. Hence a positive
a) Fill M value in the table. number and a negative number remains unchanged.
b) Fill 0 for M-1 value it should be the previous first least c) Right shift circulate M due to this not use of two for the M
significant bit of M. value.
c) Fill 0 in U and V rows which show the product of M and X d) Repeat the same steps until the n cycles are completed. So
at the end of multiplication operation. the answer is shown, in the last rows of U and V.
d) Take n rows for every cycle; this is because we are
multiplying n bits numbers.
C. Radix-4 Booth Multiplier
Table 1 Making of Booth table The shortcomings of Radix-2 can get overcome by Radix-4
[13] [14] [15] in which it handle more than one bit of
multiplier in each cycle. The modified Booth's algorithm
starts by appending a zero to right of LSB of multiplier. This
recoding scheme applied to a parallel multiplier halves the no.
of partial products so the multiplication time & hardware
requirement can get reduce [8] [14].
Radix-4 Booth algorithm examines strings of three bits
according to the following algorithm given below[14]:
Step2: Booth algorithm requires evaluation of the multiplier a) Increase the sign bit 1 position if required to verify that n is
bits, and shifting of the partial product. Use the first least even.
significant bits of the multiplier M, and the previous least b) The right side of the LSB of the multiplier adds with 0.
significant bits of the multiplier M - 1 to determine the c) As per the value of all vectors, all Partial Product will be 0,
arithmetic action. +y, -y, +2y or -2y.
The values of y are comes negative due to taking the 2s
Table 2 Shift in Booth table complement. The multiplication of y performs by left shifting
y by one bit. As a result implementing of n-bit parallel
multipliers, only n/2 partial products are created[9][14].

D. Wallace Tree Multiplier

A Wallace tree multiplier[7][15] is an proficient hardware
implementation of a digital circuit that multiplies two
integers. Number of partial products gets reduced and for the
a) Determine the two least significant (right most) bits of M. addition of partial products uses carry select adder.
Wallace tree is known for their good computation time,
1. If they are 00, no change.
when adding multiple operands to two outputs using 3:2 or
2. If they are 11, no change.
4:2 compressors or both. Wallace tree ensures the lowest
3. If they are 01, add X+A. whole delay [15]
4. If they are 10, add (-X)+A.

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 Implementation of High Performance FIR filter using High Speed & Low Area Multiplier

Wallace 27 47 21 23 8.51
Multiplier 1ns

VI. CONCLUSION
This paper is the clear model of different multiplier and their
implementation in tap delay FIR filter. We found that the
Wallace multipliers are much option than the serial multiplier.
We concluded this from the result of delay and the total area.
In case of Wallace multipliers, the total area is much less than
that of boothl multipliers. Hence the power consumption is
also less. This is clearly depicted in our results. This speeds
up the calculation and makes the system faster. While
Figure 5 Structure of Wallace Multiplier comparing the radix 2 and the radix 4 booth multipliers we
found that radix 4 consumes lesser power than that of radix 2.
V. RESULTS we found that Wallace multiplication method is better than
other multipliers in terms of speed, area and power. So by
After analyzing both the multipliers, and compare their using Wallace multiplier we can achieve the fast and efficient
characteristics in terms of multiplication speed, no of multiplication.
computations required, no of hardware, we come on finding
that Wallace multipliers is much better than Booth
VII. FUTURE WORK
multipliers. By implementing both Radix-2 & Radix -4 and
Wallace multiplier and we analysis that their computation One possible direction is to increase the number of bit of
speed of Wallace multiplier is faster. multiplier. We have only considered 8 bit for encoding as it is
In this project these multipliers are implemented with FIR a simple and popular choice. Higher number of bits recoding
filters to compare some characteristics like the speed, power further reduces the number of LUT's and thus has the potential
consumption, computations, hardware requirement of the of reducing the area.
system. Coding of all the multipliers have done separately in
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 International Journal of Engineering and Technical Research (IJETR)
ISSN: 2321-0869 (O) 2454-4698 (P), Volume-5, Issue-2, June 2016
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Bhawana Datwani M.tech. scholar, Jagannath University. I have

completed my B.Tech. in Electronics & Communication from RTU in 2012.
I have experience of 3 years of teaching. I am doing my research work in
VLSI field.

Himanshu Joshi Assistant Professor Department of ECE in Jagannath

University, Jaipur, India. He has completed his M.Tech (VLSI and
Embedded system) in 2011 from Gyan Vihar University, Jaipur, and B.E
degree in 2007 from Rajasthan University. He is currently working in the
VLSI and Communication Field.

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