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CMOS Cascode Transconductance Amplifier: Basic Topology

The document describes the operation of a CMOS cascode transconductance amplifier. It consists of four stages: 1) a common source stage with a cascoded current supply for high output resistance, 2) a common base stage, 3) a common drain stage, and 4) a common collector stage. Key aspects are the high output resistance of the common source/common base cascode stage, and ensuring sufficient output voltage swing passes through each preceding stage by biasing transistors in their high gain regions.

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76 views10 pages

CMOS Cascode Transconductance Amplifier: Basic Topology

The document describes the operation of a CMOS cascode transconductance amplifier. It consists of four stages: 1) a common source stage with a cascoded current supply for high output resistance, 2) a common base stage, 3) a common drain stage, and 4) a common collector stage. Key aspects are the high output resistance of the common source/common base cascode stage, and ensuring sufficient output voltage swing passes through each preceding stage by biasing transistors in their high gain regions.

Uploaded by

Priyantanu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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CMOS Cascode Transconductance Amplifier

* Basic topology.

* Current supply must have a very high source resistance roc since otherwise it
will limit the output resistance of the amplifier

EE 105 Spring 2000 Page 1 Week 15, Lecture 34


Current Supply Topology

* p-channel cascode current supply is an obvious solution

* need to design a totem pole voltage supply to generate VG2, VG3, and VG4

EE 105 Spring 2000 Page 2 Week 15, Lecture 34


Totem Pole Voltage Reference

* Match device sizes of M2B, M3B, and M4B to M2, M3, and M4

EE 105 Spring 2000 Page 3 Week 15, Lecture 34


Complete Transconductance Amplifier

* VBIAS: user must supply a very precise DC voltage V BIAS 1.2 V so that the
CS/CG cascode is biased so that it is in the high gain region

CS-CG two-port parameters: Gm = gm1


Output resistance: Rout = ro2(1 + gm2 ro1) || ro3(1 + gm3 ro4)
Output swing:
VOUT(max) = VD4 - VSD3(sat) = VDD - VSG4B - VSG3B + VSG3 - VSD3(sat)
VOUT(max) = 5 V - 1.5 V - 1.5 V + 1.5 V - 0.5 V = 3.0 V
VOUT(min) = VD1 + VDS2(sat) = VG2 - VGS2 + VDS2(sat) = 2 V - 1.4 V + 0.4 V = 1 V

EE 105 Spring 2000 Page 4 Week 15, Lecture 34


Multistage Voltage Amplifier

Example to understand a complicated circuit

* 10 MOSFETs, 3 BJTs, 1 resistor ... must identify building blocks


Step-by-step approach to identifying the important transistors --
1. replace all transistor current sources and voltage sources by their symbols -- look
for diodes and current mirrors! (M5, M6/M6B, M7/M7B, and M10 and Q2B are part
of current sources or a totem pole voltage reference.)
2. for the (few) remaining transistors, identify the type and use two-port small-
signal models to understand the circuits operation. (For the above amplifier, the
remaining transistors are M1, Q2, M3, and Q4.)

EE 105 Spring 2000 Page 5 Week 15, Lecture 34


Eliminating Current and Voltage Sources

* Replace current and voltage sources with symbols

VDD = 5 V

-ID5

-ID6
Q4

M3
VB2 Q2
vOUT

RS
+ M1
vs ID10
_
VBIAS+
_

EE 105 Spring 2000 Page 6 Week 15, Lecture 34


Identifying Amplifier Stages

n-channel MOSFET M1 has its source grounded --> common source


npn BJT Q2 has its gate tied to a voltage source (from totem pole string of
diode-connected transistors) --> common base
p-channel MOSFET M3 has its drain connected to ground --> common drain
npn BJT Q4 has its collector tied to the positive supply --> common collector

Voltage amplifier is a cascade of two-port models:

CS CB CD CC

Rin Rout(CS/CB) Rout

1. common source/common base with cascoded current-source supply: very high


output resistance Rout(CS/CB) --> can get extremely high output resistance, with
a transconductance equal to that of the CS stage
2. common drain: no loading on previous stage since infinite input resistance
3. common collector: low output resistance

EE 105 Spring 2000 Page 7 Week 15, Lecture 34


Cascode Stage Output Resistance

* Cascode input stage output resistance determines gain

VDD = 5 V

-ID6

Rout,CB/CS

VB2 Q2

RS2
RS
M1
VBIAS +_

n Output resistance: note that RS2 = ro1 >> r2

R out,CB = ( o2 r o2 ) r oc6 = ( o r o2 ) ( r o6 ( 1 + g m6 r o7 ) )

EE 105 Spring 2000 Page 8 Week 15, Lecture 34


CS-CB-CD-CC Two-Port Parameters

* Since CC and CD stages have unity gain (approximately), we can quickly


estimate the voltage gain by finding vin3/vin where vin3 is the input to the CD
stage
n Voltage gain:

A v ( g m1 )R out,CB = g m1 ( ( o r o2 ) ( r o6 ( 1 + g m6 r o7 ) ) )

n Output resistance: source resistance of CC output stage is relatively small, since


it preceded by a CD stage.

1 R S,CC 1 1
R out = R out,CC --------- + ----------------- = --------- + -------------------
g m4 o4 g m4 g m3 o4

EE 105 Spring 2000 Page 9 Week 15, Lecture 34


DC Bias and Output Swing

* Assuming all n-channel devices have VGS = 1.5 V and p-channel devices have
VSG = 1.5 V, we can find all the node voltages ... we also assume that VBIAS has
been adjusted such that the circuit is in the high-gain region

* Output swing: must consider the limited swing of previous stages (back to
cascode) since the the CD/CC output stages are DC level shifters

EE 105 Spring 2000 Page 10 Week 15, Lecture 34

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