Datasheet synopsys’ Silicon to Software SpyGlass Lint Early Design Analysis for Logic Designers Overview Inefficiencies during RTL design usually surface as critical design bugs during the late stages of design implementation. If detected, these bugs will often lead to iterations, and if left undetected, they will lead to silicon respins. The SpyGlass* product family is the industry standard for early design analysis with the most in-depth analysis at the RTL design phase SpyGlass provides an integrated solution for analysis, debug and ‘fixing with a comprehensive set of capabilities for structural and electrical issues all tied to the RIL description of design Introduction With soaring complexity and size of chips, achieving predictable design closure has become a challenge. A multitude of coding style, structural and electrical design issues can manifest themselves as design bugs and result in design iterations, or worst stillsilicon respins. Other tools may detect design bugs but often at late stages of design implementation, after a significant investment in time and effort has already been made. As design teams become geographically dispersed, consistency and correctness of design intent becomes a key challenge for chip integration teams. Emphasis on design reuse and IP integration requires that design elements be integrated and meet guidelines for correctness. and consistency. SpyGlass RTL Signoff Crete Power estimation & reduction hee a n Figure 1, SpyGlass RTL Signott solutionSpyGlass Lint: Structural RTL Checks ‘SpyGlass linting integrates industry-standard best practices, as well as Synopsys’ own extensive experience working with industry-leading customers, Lint checks include design reuse compliance checks such as STARC and OpenMORE to enforce a consistent style throughout the design, ease the integration of multi- ‘team and multi-vendor IP and promote design reuse. Traditional Flow With SpyGlass E--- E23 Figure 2. The SpyGlass solution accelerates and economizes IC development by minimizing costly, ‘time-consuming design-and-debug iterations SpyGlass Lint Turbo: Smarter, Faster and Deeper Design Analysis ‘Synopsys’ next generation SpyGlass Lint Turbo Solution provides a three-pronged attack on the issues facing SoC RTL signott, > Smarter analysis in Turbo mode with violation categorization by root-cause for faster debug > Faster hierarchical flow with abstract models with up to 10X performance gain > Deeper analysis using formal technology to mitigate functional errors on corresponding structural lint rules and to remove uncertainty with conclusive results Using advanced formal analysis, SpyGlass pinpoints deeper functional problems in RTL designs without requiring test benches or assertions. ‘Structural Lint (Syntax, Semantics, Synthesis, Simulation etc) v ‘Turbo Structural (improved root cause analysis, faster debus) v Functional Lint (Bit-widt, Signed-unsigned assignment etc) v Hierarchical Flew with abstract models (Top-down/Battom-up), vSn Figure 3. SpyGlass Lint for RTL Analysis Early Detection of Implementation Challenges ‘Synopsys’ SpyGlass solution greatly reduces the risk of developing complex multimilln-gate, nanometer scale ICs by accurately detecting design issues at RTL. The SpyGlass solution flags areas of the design that are likely to present implementation challenges. Sophisticated static and dynamic analysis identifies critical design issues at RTL > A comprehensive set of electrical rules check to ensure nets integrity > Includes design reuse compliance checks, such as STARC and OpenMORE to enforce a consistent style ‘throughout the design > Customizable framework to capture and automate company expertise > Integrated debug environment enables easy cross-probing among violation reports, schematic and RTL source > The most comprehensive knowladge base of design expertise and industry best practices > Supports Verilog, VHDL, V2K, SysterVerilog and mixed-language designs > Tel shall for efficient rule execution and design query > S0C abstraction flow for faster performance and low noise Advanced Methodology SpyGlass Lint provides a structured, easy-to-use and comprehensive method for solving RTL design issues, thereby ensuring high-quality RTL with fewer but meaningful violations > GuideWare methodology documentation and rule-sets included > Infrastructure for rule selection and customization aligned with design milestones > Walks users through a series of recommended steps to ensure design compliance to HDL standards, coding style, synthesis, simulation, verification, connectivity, clock and reset issues » Step-by-step approach detects and fixes design bugs in alignment with design milestones, and ensures predictable design closure without any last minute surprises or high volume of violations.Seamless Integration Increases Efficiency SpyGlass Lint supports “correct-by-construction” design, leading to early design closure and minimizing costly back-end debugging and iterations, > Integrates with advanced SpyGlass capabilites ike CDC, Constraints, Power, DFT and Physical feasibilty analysis ~ Easy to ramp up and begin productive use within half a day, even for non-experts. ~ Structured methodology enables quick adoption by engineers and constraints-optimized designs > Reduces or eliminates need for respins, potentially saving millions of dollars > Enables early closure of hand-off ready RTL design itis most cost effective > Elevates design optimization from gate-level to RTL, whe) > Helps dispersed design teams to create more consistent, high-quality designs > Enables effective design reuse and IP integration > Integrates seamlessly into existing design environments, dramatically enhancing efficiency of installed tools and methodologies SpyGlass Predictive Analyzer® significantly improves design efficiency for the world’s leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system-on-chips (SoCs) fueling today’s consumer electronics. SYNOPSYS" 222e3resjne avons sees tyesnnnavedenanarsyom Fe nies bn deere Att ony ater Sian vosonnne Seatapanrtaantie! werwnnarnevacanonserormesrantontcartn etn oe