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Physics Project On Logic Gates For Class 12

This document is a project report submitted by Dishanto Dasgupta, a class 12 student at Bhavan's Netaji Subhash Chandra Bose Vidyani ketan, to design appropriate logic gate combinations using a given truth table. The report details the objective, apparatus used, theory of logic gates, examples, conclusions, precautions, sources of error, and bibliography. It was guided by Mr. Kalyanasis Acharjya, the physics teacher, over the course of 1 month.

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Dishanto Dasgupta
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2K views

Physics Project On Logic Gates For Class 12

This document is a project report submitted by Dishanto Dasgupta, a class 12 student at Bhavan's Netaji Subhash Chandra Bose Vidyani ketan, to design appropriate logic gate combinations using a given truth table. The report details the objective, apparatus used, theory of logic gates, examples, conclusions, precautions, sources of error, and bibliography. It was guided by Mr. Kalyanasis Acharjya, the physics teacher, over the course of 1 month.

Uploaded by

Dishanto Dasgupta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 12

BHAVANS NETAJI SUBHASH CHANDRA BOSE

VIDYANIKETAN

TOPIC: TO DESIGN AN APPROPRIATE


LOGIC GATE COMBINATION USING A GIVEN
TRUTH TABLE.

A PROJECT WORK SUBMITTED TO BHAVANS N.S.C.B.


VIDYANIKETAN IN PARTIAL FULFILMENT FOR THE
A.I.S.S.C. EXAMINATION 2017-2018.

GUIDED BY PREPARED BY
Mr. Kalyanasis Acharjya Name: Dishanto Dasgupta

(Physics Teacher) Roll:


Bhavans N.S.C.B. Vidyaniketan|Page 2
NAME DISHANTO DASGUPTA
CLASS XII
SECTION SCIENCE

TOPIC: TO DESIGN AN APPROPRIATE LOGIC


GATE COMBINATION USING A GIVEN TRUTH
TABLE.

ROLL NO.
REGISTRATION NO.

TOTAL TIME REQUIRED FOR COMPLETION OF


PROJECT 1 MONTH.

DATE OF SUBMISSION

Bhavans N.S.C.B. Vidyaniketan|Page 3


THIS IS TO CERTIFY THAT DISHANTO DASGUPTA
OF CLASS XII (SCIENCE), ROLL: ,
REGISTRATION NO. -- ,
OF BHAVANS N.S.C.B. VIDYANIKETAN, HALDIA
TOWNSHIP HAS COMPLETED THIS
INVESTIGATORY PROJECT TO DESIGN AN
APPROPRIATE LOGIC GATE COMBINATION
USING A GIVEN TRUTH TABLE UNDER MY
DIRECT SUPERVISION AND GUIDANCE.

SIGNATURE
Mr. Kalyanasis Acharjya
(ASSISTANT PHYSICS TEACHER)

SIGNATURE
Mrs. Subhra Chatterjee
(PRINCIPAL)

Bhavans N.S.C.B. Vidyaniketan|Page 4


I would like to express my sincere thanks and
gratitude to Mr. Kalyanasis Acharjya, Physics teacher,
Bhavans N.S.C.B. Vidyaniketan, for his worthy
guidance, valuable counselling and encouragement for
bringing this humble piece of work to light.
I am extremely grateful to Mrs. Subhra
Chatterjee, Principal, Bhavans N.S.C.B. Vidyaniketan,
Haldia for her kind cooperation, valuable suggestion
and extending facilities in the school to study this
project.
I am also indebted to Mr. Soumendranath Ari
and Mr. Arun Khatia, Lab assistant, for their constant
help and cooperation.

Finally, I will express my sincere thanks to one


and all who have directly or indirectly assisted me for
the completion of this investigatory project.

Dishanto Dasgupta,
(Class XII).

Bhavans N.S.C.B. Vidyaniketan|Page 5


Topics Page No.

OBJECTIVE. 7

APPARATUS 7

THEORY 8

EXAMPLES.. 10

CONCLUSION 11

PRECAUTIONS. 12

SOURCES OF ERROR 12

BIBLIOGRAPHY.. 13

Bhavans N.S.C.B. Vidyaniketan|Page 6


To design appropriate logic gate combination of a given
truth table.

A Battery of 6V
Two Switches
Torch Bulb
Connecting wires

Bhavans N.S.C.B. Vidyaniketan|Page 7


THE THREE BASIC LOGIC GATES ARE:

AND GATE
OR GATE
NOT GATE

Bhavans N.S.C.B. Vidyaniketan|Page 8


Functionality of Gates can be expressed by a truth
table
A truth table lists output for each
possible combination.

If the two input values for AND gate are both 1, the
output is 1; otherwise the output is zero.
o F=A.B (AND GATE)

If the two input values for OR gate are both 0, the


output is 0; otherwise the output is one.
o F=A+B (OR GATE)
Bhavans N.S.C.B. Vidyaniketan|Page 9
A NOT gate inverts input value so it is referred
as inverter sometimes.
o F=A' (NOT GATE)

(A)

(B)

Bhavans N.S.C.B. Vidyaniketan|Page 10


Bhavans N.S.C.B. Vidyaniketan|Page 11
1. Connections should be neat, clean and tight.

2. The apparatus must be handled carefully.

3. The diagram must be neat, clean and labelled.

Connections may have some faults.

Bhavans N.S.C.B. Vidyaniketan|Page 12


Books Consulted:

Comprehensive Lab Manual Physics


Publisher: Laxmi Publications

Srijans Lab Manual Physics


Publisher: Srijan Publications

Websites Referred:

www.wikipedia.org/wiki/logic_gates

www.all-science-fair-projects.com

Signature Signature
INTERNAL EXAMINER EXTERNAL EXAMINER

Bhavans N.S.C.B. Vidyaniketan|Page 13

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