7-1

Control signals

Control Control Status signals

Datapath
inputs unit
Data
outputs

Control Data
outputs inputs

Fig. 7-1 Interaction between Datapath and Control Unit

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-2

R 7 6 5 4 3 2 1 0

(a) Register R (b) Individual bits of 8-bit register

15 0 15 8 7 0

R2 PC (H) PC (L)

(c) Numbering of 16-bit register (d) Two-part 16-bit register

Fig. 7-2 Block Diagrams of Registers

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-3

K1
Transfer occurs here
Load
t t+1
n
R1 R2 Clock

K1
Clock

Fig. 7-3 Transfer from R 1 to R 2 when K1 = 1

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-4

TABLE 7-1
Basic Symbols for Register Transfers

Symbol Description Examples

Letters Denotes a register AR, R2, DR, IR

(and numerals)
Parentheses Denotes a part of a register R2(1), R2(7:0), AR(L)
Arrow Denotes transfer of data R1 ← R2
Comma Separates simultaneous transfers R1 ← R2 , R2 ← R1
Square brackets Specifies an address for memory DR ← M[ AR]

Table 7-1 Basic Symbols for Register Transfers

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-5

TABLE 7-2
Textbook RTL, VHDL, and Verilog Symbols for Register Transfers

Operation Text RTL VHDL Verilog

Combinational Assignment = <= (concurrent) assign = (non-blocking)

Register Transfer ← <= (concurrent) <= (non-blocking)
Addition + + +
Subtraction – – –
Bitwise AND ^ and &
Bitwise OR ∨ or |
Bitwise XOR ⊕ xor ^
Bitwise NOT not ~
Shift left (logical) sl sll <<
Shift right(logical) sr srl >>
Vectors/Registers A(3:0) A(3 downto 0) A[3:0]
Concatenation || & {,}

Table 7-2 Textbook RTL, VHDL, and Verilog Symbols for Register Transfers

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-6

TABLE 7-3
Arithmetic Microoperations

Symbolic
designation Description

R0 ← R1 + R2 Contents of R1 plus R2 transferred to R0

R2 ← R2 Complement of the contents of R2 (1’s complement)
R2 ← R2 + 1 2’s complement of the contents of R2
R0 ← R1 + R2 + 1 R1 plus 2’s complement of R2 transferred to R0 (subtraction)
R1 ← R1 + 1 Increment the contents of R1 (count up)
R1 ← R1 – 1 Decrement the contents of R1 (count down)

Table 7-3 Arithmetic Microoperations

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-7

R2

n
n

Cn–1 Adder-Subtractor
Select (S) X
• Cn

V C R1 Load • K1

Fig. 7-4 Implementation of Add and Subtract Microoperations

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-8

TABLE 7-4
Logic Microoperations

Symbolic
designation Description

R0 ← R1 Logical bitwise NOT (1’s complement)

R0 ← R1 ∧ R2 Logical bitwise AND (clears bits)
R0 ← R1 ∨ R2 Logical bitwise OR (sets bits)
R0 ← R1 ⊕ R2 Logical bitwise XOR (complements bits)

Table 7-4 Logic Microoperations

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-9

TABLE 7-5
Examples of Shifts

Eight-bit examples

Symbolic After shift:

Type designation Source R2 Destination R1

shift left R1 ← sl R2 10011110 00111100

shift right R1 ← sr R2 11100101 01110010

Table 7-5 Examples of Shifts

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-10
K2
4 K1 •
R2
S Load
0
MUX 4 R0
1

R1 4

(a) Block diagram

K2
K1 •
R2
REGISTER
LOAD R0
2 – to – 1 MUX
• C REGISTER
S LOAD
D0 Q0 A0
D1 Q1 C
A1
D2 Q2 A2 Y0 D0 Q0
D3 Q3 A3 Y1 D1 Q1
B0 Y2 D2 Q2
R1 B1 Y3 D3 Q3
REGISTER B2
LOAD B3
Clock • C

D0 Q0
D1 Q1
D2 Q2
D3 Q3

(b) Detailed logic

Fig. 7-5 Use of Multiplexers to Select between Two Registers

© 2001 Prentice Hall, Inc.
M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-11

Select Load Load

S0S1S2 L0L1L2 L0L1L2

0 S n
2 – to– 1 n
1 MUX
R0 R0
n n

Select

0 S n SS11 S0 n
2 – to– 1 0
1 MUX n
R1 1 3 – to – 1 Bus R1
n MUX
2
0

0 S n n
2 – to– 1
1 MUX
R2 R2
n n

(a) Dedicated multiplexers

(b) Single Bus

Fig. 7-6 Single Bus versus Dedicated Multiplexers

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-12

TABLE 7-6
Examples of Register Transfers Using the Single Bus
in Figure 7-6(b)

Select Load

Register Transfer S1 S0 L2 L1 L0

R0 ← R2 1 0 0 0 1
R0 ← R1 , R2 ← R1 0 1 1 0 1
R0 ← R1 , R1 ← R0 Impossible

Table 7-6 Examples of Register Transfers Using the Single Bus in Figure 7-6(b)

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-13

Load Load
L0 L1 L2 L2 L1 L0
Enable
E2 E1 E0

n
Load
R0 n Bus
R0
n
LOAD
n n
Select En
R n
n 2

n
n n
En 3ñtoñ1 Bus R1 R1
MUX

Load En
n n

n
R n
n
R2
R2
n
En
En

(a) Register with bidirectional (b) Multiplexer bus (c) Three-state bus using registers
input-output lines and symbol with bidirectional lines

Fig. 7-7 Three-State Bus versus Multiplexer Bus

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-14
0
Data bus 1
Timing destination Load
Address and 2
bus decoder
control
decoder 3

0 1 2
0
Data bus 1
source Enable
decoder 2
Enable 3

A0 A1 A2 D2 D1 D0

k n
Address bus Data bus

Read Write

Memory
2k x n

Fig. 7-8 Memory Unit Connected to Address and Data Buses

© 2001 Prentice Hall, Inc.
M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-15 Load enable A select B select

Write A address B address

D data n

Load R0
2 2

n n

Load R1
0
n 1
MUX
2
n
3
0
1
Load MUX
R2 2
3
n n

Load R3
n n
0 1 2 3 n
Decoder Register file
D address A data B data
2 n n
Constant in

Destination select n 1 0
MB select S MUX B
Bus A n
Address Out
Bus B n
Data Out
A B n

G select H select
4 A B 2 B
S2:0 || C in S
V Arithmetic/logic 0 IR Shifter IL 0
unit (ALU)
C
G H
N n
n
Z Zero Detect
0 1
MF select
MUX F Function unit
F
Data In
n n
0 1
MD select
MUX D
n Bus D

Fig. 7-9 Block Diagram of a Datapath

© 2001 Prentice Hall, Inc.
M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-16

A0
Data A1
input A •
•
• G0
An – 1
G1 Data
• output G
B0 n-bit •
B1 arithmetic/ Gn – 1
•
Data
input B • logic
• unit
• (ALU)
Bn – 1

Carry input Cin Cout Carry output

S0
Operation
select { S1
Mode select S2

Fig. 7-10 Symbol for an n -Bit ALU

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-17

Cin

n
A X

n-bit
n parallel n G = X + Y + Cin
B
adder
B input n
Y
S0 logic

S1

Cout

Fig. 7-11 Block Diagram of an Arithmetic Circuit

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-18

TABLE 7-7
Function Table for Arithmetic Circuit

Select Input G = A +Y + C in

S1 S0 Y Cin = 0 C in = 1

0 0 all 0’s G = A (transfer) G = A + 1 (increment)

0 1 B G = A + B (add) G = A +B +1
1 0 B G = A +B G = A + B + 1 (subtract)
1 1 all 1’s G = A – 1 (decrement) G = A (transfer)

Table 7-7 Function Table for Arithmetic Circuit

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-19

Inputs Output
S1 S0 Bi Yi

0 0 0 0 Yi = 0 S0
0 0 1 0
00 01 11 10
0 1 0 0 Yi = Bi
0 1 1 1 0 1
1 0 0 1 Yi = Bi
1 0 1 0 S1 1 1 1 1
1 1 0 1 Yi = 1
1 1 1 1 Bi
(b) Map Simplification:
(a) Truth table Yi = Bi S0 + Bi S1

Fig. 7-12 B Input Logic for One Stage of Arithmetic Circuit

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-20

Cin
S1
C0
S0
A0 X0
B0 • FA G0
•
Y0
•
•
C1
A1 X1
B1 • FA G1
•
Y1
•
•
C2
A2 X2
B2 • FA G2
•
Y2
•
•
C3
A3 X3
B3 •
FA G3
Y3
• C4
Cout

Fig. 7-13 Logic Diagram of a 4-Bit Arithmetic Circuit

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-21

S0 S0 4 – to– 1
MUX
S1 S1

S1 S0 Output Operation
Ai •
0 G=A B AND
Bi • 0 0 ^
Gi ^
• 0 1 G=A B OR
1
• 1 0 G=A B XOR
• 2 1 1 G=A NOT

(b) Function Table

• 3

(a) Logic Diagram

Fig. 7-14 One Stage of Logic Circuit

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-22

Ci Ci + 1
Ai • One stage of
Bi • arithmetic
circuit
2 – to– 1
0 MUX
Gi
1
S
One stage of
logic circuit
S0 •
S1 •
S2

Fig. 7-15 One Stage of ALU

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-23

TABLE 7-8
Function Table for ALU

Operation Select

S2 S1 S0 Cin Operation Function

0 0 0 0 G=A Transfer A
0 0 0 1 G = A +1 Increment A
0 0 1 0 G = A +B Addition
0 0 1 1 G = A +B +1 Add with carry input of 1
0 1 0 0 G = A +B A plus 1’s complement of B
0 1 0 1 G = A +B +1 Subtraction
0 1 1 0 G = A –1 Decrement A
0 1 1 1 G=A Transfer A
1 0 0 X G = A∧B AND
1 0 1 X G = A∨B OR
1 1 0 X G = A⊕B XOR
1 1 1 X G=A NOT (1’s complement)

Table 7-8 Function Table for ALU

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-24

B3 B2 B1 B0
Serial •
output L
•
•
Serial
• output R
IR IL

0 1 2 M 0 1 2 M 0 1 2 M 0 1 2 M
S U S U S U S U
X X X X

2
S • • •

H3 H2 H1 H0

Fig. 7-16 4-Bit Basic Shifter

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-25

D3 D2 D1 D0

• • •
• •
• •
• • •
S0 • • •
S1 • • •
3 2 1 0 S 1 S0 3 2 1 0 S1 S0 3 2 1 0 S1 S0 3 2 1 0 S1 S0
M M M M
U U U U
X X X X

Y3 Y2 Y1 Y0

Fig. 7-17 4-Bit Barrel Shifter

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-26

TABLE 7-9
Function Table for 4-Bit Barrel Shifter

Select Output

S1 S0 Y3 Y2 Y1 Y0 Operation

0 0 D3 D2 D1 D0 No rotation
0 1 D2 D1 D0 D3 Rotate one position
1 0 D1 D0 D3 D2 Rotate two positions
1 1 D0 D3 D2 D1 Rotate three positions

Table 7-9 Function Table for 4-Bit Barrel Shifter

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-27

D data
Write
m
D address
2m x n
Register file
m m
A address B address

A data B data
Constant in n
n
n
1 0
MB select MUX B

Bus A n
Address out
Bus B n
Data out

5 A B
FS
V
C Function
unit
N
Z
F

n n
Data in

0 1
MD select
MUX D

Fig. 7-18 Block Diagram of Datapath Using the Register File and Function Unit

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-28

TABLE 7-10
G Select, H Select, and MF Select Codes Defined
in Terms of FS Codes

MF G H
FS Select Select Select Microoperation

00000 0 0000 00 F=A

00001 0 0001 00 F = A +1
00010 0 0010 00 F = A +B
00011 0 0011 00 F = A +B +1
00100 0 0100 s 01 F = A +B
00101 0 0101 01 F = A +B +1
00110 0 0110 01 F = A –1
00111 0 0111 01 F=A
01000 0 1000 0 F = A ∧B
01010 0 1010 10 F = A ∨B
01100 0 1100 10 F = A ⊕B
01110 0 1110 10 F=A
10000 1 0000 00 F=B
10100 1 0100 01 F = sr B
11000 1 1000 10 F = sl B

Table 7-10 G Select, H Select, and MF Select Codes Defined in Terms of FS Codes

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
 n
7-29
RW 0 Write D data

16
DA 15 D address
14 8xn
Register file
13 10
AA 12 A address B address 9 BA
11 8
A data B data
n n

n
Constant in

1 0
MB 7 MUX B
Bus A n
Address out
Bus B n
Data out

A B
6
V 5
C Function 4 FS
N unit
3
Z 2

n n Data in

0 1
MD 1 MUX D
Bus D

(a) Block Diagram

16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DA AA BA M FS M R
B D W

(b) Control word

Fig. 7-19 Datapath with Control Variables

© 2001 Prentice Hall, Inc.
M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-30

TABLE 7-11
Encoding of Control Word for the Datapath

DA, AA, BA MB FS MD RW

Function Code Function Code Function Code Function Code Function Code

R0 000 Register 0 F=A 00000 Function 0 No write 0

R1 001 Constant 1 F = A +1 00001 Data In 1 Write 1
R2 010 F = A +B 00010
R3 011 F = A +B +1 00011
R4 100 F = A +B 1 00100
R5 101 F = A +B +1 00101
R6 110 F = A –1 00110
R7 111 F=A 00111
F = A ∧B 01000
F = A ∨B 01010
F = A⊕B 01100
F=A 01110
F=B 10000
F = sr B 10100
F = sl B 11000

Table 7-11 Encoding of Control Word for the Datapath

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-31

TABLE 7-12
Examples of Microoperations for the Datapath, Using Symbolic Notation

Micro-
operation DA AA BA MB FS MD RW

R1 ← R2 + R3 + 1 R1 R2 R3 Register F = A +B +1 Function Write

R4 ← sl R6 R4 — R6 Register F = sl B Function Write
R7 ← R7 + 1 R7 R7 — Register F = A +1 Function Write
R1 ← R0 + 2 R1 R0 — Constant F = A +B Function Write
Data out ← R3 — — R3 Register — — No Write
R4 ← Data in R4 — — — — Data in Write
R5 ← 0 R5 R0 R0 Register F = A ⊕B Function Write

Table 7-12 Examples of Microoperations for the Datapath, Using Symbolic Notation

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-32

TABLE 7-13
Examples of Microoperations from Table 7-11, Using Binary Control Words

Micro-
operation DA AA BA MB FS MD RW

R1 ← R2 – R3 001 010 011 0 00101 0 1

R4 ← sl R6 100 000 110 0 11000 0 1
R7 ← R7 + 1 111 111 000 0 00001 0 1
R1 ← R0 + 2 001 000 000 1 00010 0 1
Data out ← R3 000 000 011 0 00000 0 0
R4 ← Data in 100 000 000 0 00000 1 1
R5 ← 0 101 000 000 0 01100 0 1

Table 7-13 Examples of Microoperations from Table 7-11, Using Binary Control Words

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-33 Clock 1 2 3 4 5 6 7 8

DA 1 4 7 1 0 4 5 ×

AA 2 6 7 0 ×

BA 3 0 3 0 ×

MB ×

RW ×

Constant in
× 2 ×

FS 05 24 01 02 00 0C ×

Data in × 18 ×

MD ×

R0 00

R1 01 FF 02

R2 02

R3 03

R4 04 0C 18

R5 05 00

R6 06

R7 07 08

Status bits 4 0 8 ×

Address out 02 00 07 00 ×

Data out 03 06 00 03 00 ×

Fig. 7-20 Simulation of the Microoperation

© 2001 Prentice Hall, Inc. Sequence in Table 7-13
M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-34

Clock
3 ns 3 ns
3
Clock WB
Register file OF Register file
3 ns 3 ns

1
MUX B 1 ns MUX B 1 ns

OF

EX 1 ns

Function unit 4 ns 2 Function unit 4 ns

EX
MUX D 1 ns
WB 1 ns

3 MUX D 1 ns

(a) Conventional (b) Pipelined

Fig. 7-21 Datapath Timing

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-35

Fig. 7-22 Assembly Line Analogy to Datapath Pipeline

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-36
Register
file
OF 1 AA A data B data BA
Operand Fetch (OF)
Constant in

MUX B MB

OF
EX Address out
Data out

A B
2 FS
Execute (EX) Function
V
unit
C
N
Z F

Data in

EX
WB
3 MD 0 1
MUX D
Write-back (WB)
WB RW D data
DA Register
file (same
as above)

Fig. 7-23 Block Diagram of Pipelined Datapath

© 2001 Prentice Hall, Inc.
M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-37

Clock cycle

1 2 3 4 5 6 7 8 9
R1 → R2 – R3 1 OF EX WB
R4 → sl R6 2 OF EX WB
R7 → R7 + 1 3 OF EX WB
R1 → R0 + 2 4 OF EX WB
Data out → R3 5 OF EX WB
R4 → Data in 6 OF EX WB
R5 → 0 7 OF EX WB
Microoperation

Fig. 7-24 Pipeline Execution Pattern for Microoperation Sequence in Table 7-13

© 2001 Prentice Hall, Inc.

M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.