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Unet Compact Datasheet v1.3

The document describes an integrated circuit for interfacing with audio and video signals. It provides specifications for input/output timing parameters when operating in master and slave modes. Timing parameters include clock periods, duty cycles, setup and hold times. It also provides specifications for interfacing with SPI signals. The document is a data sheet providing technical specifications and parameters for a audio/video interface IC.

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Lungu Cristian
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257 views11 pages

Unet Compact Datasheet v1.3

The document describes an integrated circuit for interfacing with audio and video signals. It provides specifications for input/output timing parameters when operating in master and slave modes. Timing parameters include clock periods, duty cycles, setup and hold times. It also provides specifications for interfacing with SPI signals. The document is a data sheet providing technical specifications and parameters for a audio/video interface IC.

Uploaded by

Lungu Cristian
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Archwave Technologies B.V. www.archwave.net


Archwave Technologies B.V. www.archwave.net
Archwave Technologies B.V. www.archwave.net
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Archwave Technologies B.V. www.archwave.net


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Archwave Technologies B.V. www.archwave.net


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IO loads: AVCLK,AVCTRL: 10 pF MASTER MODE
AVDATA: 10 pF
Nr. Parameter Symbol Min Typ Max Unit
1 Clock period tIxS,M,CY 20 ns
2 Clock duty cycle dIxS,M,DC 40 50 60 %
4 Input setup time (active edge sampling) tIxS,M,IS 7.5 ns
5 Input hold time (active edge sampling) tIxS,M,IH 0 ns
6 Input setup time (inactive edge sampling) tIxS,M,IS 7.5 ns
7 Input hold time (inactive edge sampling) tIxS,M,IH 0 ns
8 Clock to output valid time tIxS,M,OV 0.8 5 ns
9 Clock to output invalid time tIxS,M,OX 0.8 5 ns

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Archwave Technologies B.V. www.archwave.net


IO loads: SPIDIN: 10 pF
Nr. Parameter Symbol Min Typ Max Unit
2 Clock period (=S) tSPI,S,CY 3P ns
3 Clock high / low time tSPI,S,DC ns
st
4 NCS active to 1 clock edge tSPI,S,IS 1P ns
5 Last clock edge to NCS inactive tSPI,S,IS S/2 + P ns
6 Input setup time tSPI,S,IS 2 ns
7 Input hold time tSPI,S,IH 5+P ns
8 Clock to output valid time tSPI,S,OV 4.4 15 ns
9 Clock to output invalid time tSPI,S,OX 4.4 15 ns

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