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First Internal Sliding Result Letter

- The document is a first internal sliding result letter for Sameer Gupta for the CCMT 2018 admissions process. - Sameer has been allotted a seat in the VLSI Systems Design PG program at the National Institute of Technology in Warangal under the OPEN category. - Sameer has paid the seat confirmation fee and seat acceptance fee. - Sameer must report to NIT Warangal between June 25-28 with original documents and DVC or the allotted seat will be cancelled. He must also pay the balance of institute fees.

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0% found this document useful (0 votes)
62 views1 page

First Internal Sliding Result Letter

- The document is a first internal sliding result letter for Sameer Gupta for the CCMT 2018 admissions process. - Sameer has been allotted a seat in the VLSI Systems Design PG program at the National Institute of Technology in Warangal under the OPEN category. - Sameer has paid the seat confirmation fee and seat acceptance fee. - Sameer must report to NIT Warangal between June 25-28 with original documents and DVC or the allotted seat will be cancelled. He must also pay the balance of institute fees.

Uploaded by

sameerbset
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Centralized Counselling for M.Tech./M.Arch./M.Plan.

Admissions
CCMT - 2018 (Coordinated by NIT, Delhi)

FIRST INTERNAL SLIDING RESULT LETTER


Candidate's Details

GATE Registration ID : EC18S53002045 GATE Score : 652


GATE Examination Year : 2018 GATE Examination Paper Name : Electronics and Communication Engineering (EC)
Candidate Name : SAMEER GUPTA GATE Marks out of 100 : 45
Father's Name : PRAKASH CHANDRA GUPTA Mother's Name : NISHA GUPTA
Date of Birth : 10/10/1994 Gender : Male
Category : General Person with Disability (PwD) : NO
Complete Address: 507/33, Shiv Colony B, Tijara Highway, Alwar Pin Code : 301001
Nationality : INDIAN

Qualifying Degree Details

Qualifying Degree Passing Status : Passed Year of Passing or Appearing : 2014


Qualifying Degree : B.E./B.Tech. Qualifying discipline Name : B.E./B.Tech. in Electronics & Communication
Engineering
Qualifying Result Preparation Mode Percentage Percentage of Marks 70.91
:

Allotment Details

Choice No. : 2 Round No. : 4


Institute : National Institute of Technology, Warangal PG Programme : VLSI Systems Design
Allotted Seat Type : OPEN Group Id : G1

Payment of Seat Confirmation Fee Details:

Transaction No Transaction Amount Transaction Date Merchant Reference Number


CPH8705464     10000 18-6-2018 Time: 14:01:05 EC18S530020451806

Payment of Seat Acceptance Fee Details:

Transaction No Transaction Amount  Transaction Date Merchant Reference Number


CPH2133600 20000 21-5-2018 Time: 10:53:26 EC18S530020451805

Message

The Candidate has to report to the above allotted institute during 25 - 28 June, 2018 for final admission with all the original documents along with Document Verification Certificate
(DVC), failing which above allotted seat will be cancelled.
The candidate has to pay the balance of Institute's Fees at the time of admission in the allotted institute. For any further information, please contact the respective institute.

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