10.1117/2.1201211.

004539

Triple patterning in 10nm node

metal lithography
Kevin Lucas, Chris Cork, Bei Yu, Gerry Luk-Pat, Ben Painter,
Alex Miloslavsky, and David Pan

Next-generation lithographic methods will have major implications

for 10nm logic in terms of physical design, design rules, and mask
synthesis/electronic design automation algorithms.

The local metallization layers of logic products are histori-

cally the densest layouts to lithographically pattern and are
key drivers of product density (and therefore cost). Due to
delays in extreme-UV (EUV) lithography and difficulties in
applying other resolution-enhancement technologies (RETs)—
such as double-patterning methods—triple-patterning technol-
ogy (TPT) is a strong option for handling the local metal layers
Figure 1. Examples of metal routing configuration in design and with
of the upcoming 10nm logic technology node ( 44–48nm min-
double (DPT) and triple patterning technology (TPT), showing the po-
imum feature pitch). Several TPT methods, including ones de-
tentially large benefit for pattern density of triple patterning for 1D
veloped by us, are being considered in different product areas
features. The different colors of the polygon in the decomposed layouts
of semiconductor manufacturing.1, 2 For advanced logic metal
represent the different mask target layouts (two masks for DPT, three
layers, the main TPT option assumes a process flow known as
masks for TPT).
litho-etch-litho-etch-litho-etch (LELELE). In this flow, the final
substrate pattern is the logical OR of three successive lithog-
raphy+etch sequences, each sequence using a single traditional steps.3 Consequently, individual feature critical dimension (CD)
lithography exposure and a single etch step (see Figure 1). and overall control tolerances in a TPT process must be signifi-
The use of LELELE TPT in a product design and production cantly tighter than in a single-exposure process for the same de-
flow involves the following steps: design of TPT-compliant lay- vice layer.
out; design verification; decomposition of the layout into the Design and mask synthesis (i.e., decomposition, RET, OPC,
three TPT single-exposure wafer targets (via TPT decomposi- and OPC verification) pose different but related difficulties.
tion software); RET/optical proximity correction (OPC) steps for Designers must be able to confidently create and verify TPT-
each single-exposure wafer target; OPC verification; mask data compliant layouts. This requires accurate and sufficiently flexi-
preparation; mask manufacture; and wafer processing in the fab- ble design rules. Figure 2 shows examples of basic TPT design
rication facility (fab). There are many difficulties in achieving rules for the metal1 layer of standard cells. The design flow
a high-yielding, cost-effective TPT process. Here, we first look must also be able to quickly and accurately verify the physical
at problems in mask manufacture and wafer production flow, and electrical integrity of the full-chip final design target. Mask
especially cost, turn-around time, and the logistical challenges synthesis cost and turn-around time are definitely affected by
of tripling the number of mask and fab process steps per layer. the tripling of the number of processing steps. However, a big-
However, the complexity and process control requirements of ger risk would be if the increased accuracy requirements could
a TPT mask and wafer flow also increase substantially. More- not be met. Fortunately, the RET, OPC, and OPC verification
over, potential negative interactions can cause device failure
between feature edge placements from the different litho-etch Continued on next page
 10.1117/2.1201211.004539 Page 2/3

methods developed for DPT can be extended to successfully

handle TPT requirements in these areas.
An even more fundamental TPT mask synthesis challenge ex-
ists in the layout decomposition step. Production-worthy TPT
decomposition methods are not yet fully defined and validated.
Currently, the two most plausible approaches are extension of
existing DPT decomposition methods (see Figure 3), and devel-
opment of full TPT decomposition algorithms. The advantage of
the first approach is that DPT methods are well known, trusted,
available, and fast enough to run on full-chip layouts. A main
drawback is that it is less likely to result in a decomposition
solution for layouts that are TPT compliant. This can lead to
a TPT-compliant design being decomposed in an unmanufac-
turable manner. Another drawback of extending existing DPT Figure 3. Example showing how DPT methods can be reused to create
methods is difficulty in achieving similar feature density for all TPT decomposition. First, a traditional two-color DPT decomposition
three masks. Mask density imbalance can lead to degraded over- is run. Next, DPT conflicts are identified. Then, one polygon at each
lay and CD control. conflict area is transferred to the third mask (color). Finally, each color
We have proposed several TPT decomposition algorithms.2 is checked separately for conflicts (i.e., spacing violations).
The quality of results can vary strongly, as better algorithms
can enlarge the set of layouts that are TPT-compliant, leading
to solutions that have a smaller layout area and are more man-
ufacturable (see Figure 4).4 The main drawback of full TPT al-
gorithms is that their turn-around time/memory performance
is not yet sufficient for full-chip decomposition (see Figure 5).5
With these performance limitations, the industry must do TPT

Figure 4. Examples of complex layouts that require a sophisticated TPT

algorithm to find a compliant and manufacturable decomposition so-
lution. The need to resolve long-range TPT conflict interactions and
determine optimal stitching locations increases the solution space to
search and limits the usefulness of simpler TPT solvers.

decomposition individually on smaller cells and layout blocks,

then use correct-by-construction design rule and design practice
approaches to ensure the entire chip becomes TPT compliant.
Figure 2. Examples of design rules to detect TPT non-compliant lay- Fortunately, TPT full-chip compliance can be easily and quickly
out for a fictional 48nm minimum pitch process. X indicates a TPT verified using extensions of existing DPT software (e.g., design
conflict. The long-range TPT conflict at the lower left cannot be found rule constraints or OPC verification).
by conventional design rule constraint methods. It requires full TPT In summary, TPT patterning is a serious option for local metal
decomposition to be run before conflicts can be found. L/S: Line/space. layers in next-node logic processes. Several design and process
SE: Single exposure. CD: Critical dimension.

Continued on next page

 10.1117/2.1201211.004539 Page 3/3

Bei Yu and David Pan

Department of Electrical and Computer Engineering
University of Texas at Austin
Austin, TX

Gerry Luk-Pat and Alex Miloslavsky

Synopsys Inc.
Mountain View, CA

Ben Painter
Synopsys Inc.
Hillsboro, OR
Figure 5. Example of decomposition algorithm turn-around time (TAT)
References
vs. the number of nodes to color for a known TPT-compliant test 1. Y.-S. Chang, J. Sweis, J.-C. Lai, C.-C. Lin, and J. Yu, Full area pattern decomposition
pattern.5 Full TPT decomposition TAT shows a rapid increase with the of self-aligned double patterning for 30nm node NAND FLASH process, Proc. SPIE 7637,
p. 76371N, 2010.
number of linked nodes to color in a layout. Smart techniques—such as
2. K. Lucas, C. Cork, B. Yu, G. Luk-Pat, B. Painter, and D. Z. Pan, Implications of triple
those we have described elsewhere4 —can greatly reduce TAT. But full- patterning for 14nm node design and patterning, Proc. SPIE 8327, p. 832703, 2012.
chip TPT decomposition ability is far from certain. WCSP: Weighted 3. S. Sivakumar, EUV lithography: prospects and challenges, ICCAD Nanolithogr.
Wrkshp., 2011.
constraint satisfaction problem. SAT: Satisfiability. 4. B. Yu et al., Layout decomposition for triple patterning lithography, Proc. ICCAD,
pp. 1–8, 2011. doi:10.1109/ICCAD.2011.6105297
5. C. Cork, J.-C. Madre, and L. Barnes, Comparison of triple patterning decomposition
techniques developed for DPT can be reused in TPT. However, algorithms using aperiodic tiling patterns, Proc. SPIE 7028, p. 702839, 2008.

significant challenges remain. The biggest process challenges are

cost and control. The biggest design and mask synthesis chal-
lenges are the development and coordinated deployment of TPT
decomposition algorithms. Our current work focuses on im-
proving TPT algorithm applicability to larger layout sizes for
10nm node design rule and process integration development.

Sincere thanks for helpful discussions to Vincent Wiaux and Peter De

Bisschop from IMEC.

Author Information

Kevin Lucas
Synopsys Inc.
Austin, TX

Kevin Lucas joined Motorola Semiconductor in 1994 after com-

pleting his PhD in electrical and computer engineering at
Carnegie Mellon University. In 2006 he joined Synopsys, where
he currently is the RET and OPC product engineering manager.

Chris Cork
Synopsys Inc.
Montbonnot, France

c 2012 SPIE