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Q4

The document explains a 4-bit Manchester carry chain adder in dynamic logic. It consists of a chain of pass transistors used to implement the carry chain without gates between stages. Each stage precharges during CLK=0 and evaluates during CLK=1. The carry output depends on whether the propagate signal is 0 (carry doesn't pass) or 1 (carry passes). The adder has a minor ripple delay, threshold drop on propagate, and few transistors. However, the delay grows quadratically with the number of bits due to the distributed RC nature of the chain. Manchester carry chains generally do not exceed 4 bits due to the increasing capacitive load and resistance slowing propagation.

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1K views3 pages

Q4

The document explains a 4-bit Manchester carry chain adder in dynamic logic. It consists of a chain of pass transistors used to implement the carry chain without gates between stages. Each stage precharges during CLK=0 and evaluates during CLK=1. The carry output depends on whether the propagate signal is 0 (carry doesn't pass) or 1 (carry passes). The adder has a minor ripple delay, threshold drop on propagate, and few transistors. However, the delay grows quadratically with the number of bits due to the distributed RC nature of the chain. Manchester carry chains generally do not exceed 4 bits due to the increasing capacitive load and resistance slowing propagation.

Uploaded by

Skvk
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
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Q4. Explain 4 bit Manchester carry chain adder in dynamic logic .

The Manchester Carry-Chain Adder is a chain of pass-transistors that are used to implement
the carry chain. The good thing about Manchester Carry Chains is that there is no gate
between stages.
OPERATION OF SINGLE STAGE:
Precharge phase: CLK=0. the carry nodes precharge.
Evaluation Phase : evaluate when CLK= 1
!Ci+1 stays high unless •Gi= 1 (!Ci+1=0) or Pi= 1 (!Ci+1=!Ci)

Fig: 1 stage of Manchester carry chain Fig: Truth table arranged for pi

Fig: logic diagram

if Pi= 0 (Ci doesn’t pass) ----- !Ci+1= !Gi(NOT Gi)


–block ci, pass VDD or GND
•if Pi= 1 (Ci passes)----- !Ci+1= !Ci
–pass ci, block VDD & GND
Fig : 4 bit Manchester carry chain adder

Generate Gi= ai•bi

propagate Pi= ai⊕bi

There are four pass transistors in series (P3 P2 P1 P0) + Ci,0 and Me of first gate.

Capacitance per node on carry chain= 4 diffusion capacitance + 1 input capacitance from
inverter and wire capacitance.

Only 4 diffusion capacitances are present at each node, but the distributed RC -nature of the
chain results in a delay that is quadratic with the number of bits.

With 4 bit Manchester carry chain adder it has minor ripple delay, threshold drop on
propagate and very few transistors.

Tp=0.693N(N+1)RC/2. …. N = no of stages

Disadvantage:

The bad news is that the number of series transistors increases with the nubmer of stages (the
critical path involves a series propagate transistor for each bit); so the delay will grow like
n2.The worst case delay depends on the generation of carry-Propagate signals.

One of the major downsides of the Manchester carry chain is that the capacitive load of all of
these outputs, together with the resistance of the transistors causes the propagation delay to
increase much more quickly than a regular carry lookahead. A Manchester-carry-chain
section generally doesn't exceed 4 bits.
References:

1.https://en.wikichip.org/wiki/Special:RecentChangesLinked/Manchester_carry-chain_adder

2. https://slideplayer.com/slide/4896714/

3. https://www.youtube.com/watch?v=6Hl5lhgE9sc

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