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PIC Microcontroller Architecture

The PIC microcontroller uses a Harvard architecture with separate program and data memory. It has a 8-bit CPU, 8-bit ALU, and orthogonal instruction set. The instruction cycle is divided into four phases with a two-stage pipeline that overlaps fetch and execute. The general instruction format is 14-bit opcodes with optional operands.

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Peeyush Kp
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55 views

PIC Microcontroller Architecture

The PIC microcontroller uses a Harvard architecture with separate program and data memory. It has a 8-bit CPU, 8-bit ALU, and orthogonal instruction set. The instruction cycle is divided into four phases with a two-stage pipeline that overlaps fetch and execute. The general instruction format is 14-bit opcodes with optional operands.

Uploaded by

Peeyush Kp
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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PIC Microcontroller

Architecture
Von Neumann Architecture

„ Fetches instructions
and data from same
memory CPU
8-Bits
„ Limits operating
Program
bandwidth and Data
Memory
Harvard Architecture

„ Two separate
memory spaces for
instruction and data
CPU
„ Increases throughput 8-Bits
Data
„ Different program 12/14/16-Bits
Program
Memory

and data bus widths Memory

are possible
Instructions
„ Long Word Instructions
„ Wider instruction bus
Movlw #imm<8>
„ Single Word Instructions 1100XX k k k k k k k k
„ Opcodes are 14 bits wide
„ No multi byte instruction
„ Single Cycle Instruction
„ Entire instruction is fetched in a
single cycle
Instructions

„ Instruction Pipeline
{ Two stage pipeline
{ Overlaps Fetch & Execute Cycles
{ Each takes one Tcy
„ Orthogonal Instructions
{ Any operation on any register using any
addressing mode
Architecture

„ Register File Architecture


{ Register File/ Data Memory can be
accessed directly or indirectly
{ All SFRs are mapped in data memory
„ Reduced Instruction Set
{ Instruction set is well designed
{ Highly symmetric (orthogonal)
Instruction Cycle
„ OSC1 is internally divided to four non-
overlapping quadrature clock
{ Q1, Q2, Q3 and Q4
Clocking Scheme
Instruction Pipeline Flow
Instruction Cycle

„ Q1 : Instruction Decode Cycle or


Forced no operation
„ Q2 : Instruction Read Data Cycle or
No operation
„ Q3 : Process the data
„ Q4 : Instruction Write Data Cycle or
No operation
General Instruction Format
Arithmetic Logic Unit

„ 8 bit ALU
„ Capable of
ALU
{ Addition & Subtraction
{ Logical & Shift operations

„ Result affects the status flag bits


Inputs to Arithmetic Logic Unit
INDF 00
„ Two operand instructions TMR0 01
Operand 1 PCL 02
Working Register STATUS 03
Operand 2 FSR 04
ALU
File Register PORTA 05
Immediate constant Other SFRs 06

W Register
„ Single operand instruction
{ Working register General Purpose
20
Registers (RAM)
{ File Register
ALU & W Register
STATUS register

IRP RP1 RP0 TO PD Z DC C

CARRY
DIGIT CARRY
ZERO
POWER DOWN
TIMEOUT
REGISTER PAIR 0
REGISTER PAIR 1
INDIRECT REGISTER PAIR
STATUS Register
Architecture
RAM
Program Counter
Program
Memory File
Registers
8k x 14 8 Level Stack

WREG

Instruction Register

Instruction Decoder
Architecture – A
subset
OPTION Register
PCON Register

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