CHAPTER 12

Introduction to Programmable Logic Controllers

The development of Programmable Logic Controllers (PLCs) was driven primarily by

the requirements of automobile manufacturers who constantly changed their production
line control systems to accommodate their new car models. In the past, this required
extensive rewiring of banks of relays — a very expensive procedure. In the 1970s, with
the emergence of solid-state electronic logic devices, several auto companies challenged
control manufacturers to develop a means of changing control logic without the need to
totally rewire the system. The Programmable Logic Controller (PLC) evolved from this
requirement. (PLC™ is a registered trade mark of the Allen-Bradley Co. but is now
widely used as a generic term for programmable controllers.) A number of companies
responded with various versions of this type of control.

The PLCs are designed to be relatively “user-friendly” so that electricians can easily
make the transition from all-relay control to electronic systems. They give users the
capability of displaying and trouble-shooting ladder logic on a cathode ray tube (CRT)
that showed the logic in real time. The logic can be “rewired” (programmed) on the
CRT screen, and tested, without the need to assemble and rewire banks of relays.

The existing push-buttons, limit switches, and other command components continue to
be used, and become input devices to the PLC. In like manner, the contactors, auxiliary
relays, solenoids, indicating lamps, etc., become output devices controlled by the PLC.
The ladder logic is contained as software (memory) in the PLC, replacing the inter-
wiring previously required between the banks of relays. If one understands the interface
between the hardware and the software, the transition to PLCs is relatively easy to
accomplish. This approach to control allows “laymen” to use the control without
necessarily being expert computer programmers.

The following introduction to PLCs should be considered generic in content. The author
programmed at least five different brands of PLCs, under contract with original
equipment manufacturers (OEMs), when they were required by their customers to
convert their machines from relays to PLC control.

While each PLC manufacturer may have unique addressing systems, or varying
instruction sets, you will find that the similarities will out-number the differences. A
typical program appears on the CRT as a ladder diagram, with contacts, coils, and
circuit branching, very similar to that which appears on an equivalent schematic for
relay logic.

Our intent is to help one understand the transition from relays to PLC control, rather
than trying to teach the details of designing and programming a specific brand of
equipment. Manufacturers have numerous programming schools, from basic to
advanced training, and you should consider attending them if you plan to become a
proficient programmer.

PLC Hardware

Programmable controllers have a modular construction. They require a power supply,

1
control processor unit (CPU), input/output rack (I/O), and assorted input and output
modules. Systems range in size from a compact “shoe-box” design with limited memory
and I/O points, as shown in Figure 12-1, to systems that can handle thousands of I/O,
and multiple, inter-connected CPUs. A separate programming device is required, which
is usually an industrial computer terminal, a personal computer, or a dedicated
programmer.

Figure 12-1

Small logic controller, SLC 500, showing variety of modules (Courtesy

Allen-Bradley Co., Milwaukee WI)

Power Supply

The internal logic and communication circuitry usually operates on 5 and 15 volt DC
power. The power supply provides filtering and isolation of the low voltage power from
the AC power line. Power supply assemblies may be separate modules, or in some
cases, plug-in modules in the I/O racks. Separate control transformers are often used to
isolate inputs and CPU from output devices. The purpose is to isolate this sensitive
circuitry from transient disturbances produced by any highly inductive output devices.

CPU

This unit contains the “brains” of the PLC. It is often referred to as a microprocessor or
sequencer. The basic instruction set is a high level program, installed in Read Only
Memory (ROM). The programmed logic is usually stored in Electrically Erasable
Permanent Read Only

Memory (EEPROM). The CPU will save everything in memory, even after a power
loss. Since it is “electrically erasable”, the logic can be edited or changed as the need
arises. The programming device is connected to the CPU whenever the operator needs
to monitor, troubleshoot, edit, or program the system, but is not required during the
normal running operations.
I/O rack

2
This assembly contains slots to receive various input and output modules. The rack can
be local, combined with the CPU and power supply, or remote. Each rack is given a
unique address so that the CPU can recognize it. Within each rack, the slots have unique
addresses. Power and communication cables are required for remote installations. The
replaceable I/O modules plug into a back-plane that communicates directly with the
CPU or through the cable assembly. Field wiring terminates on “swing arms” that plug
into the face of the I/O modules. This allows a quick change of I/O modules without
disconnecting the field wiring. Every module terminal also has a unique address. Figure
12-2 shows a drawing of an Allen-Bradley PLC-5, with 128 I/O. (Power supply is not
shown.)

Figure 12-2
PLC-5 with 128 I/O (Courtesy Allen-Bradley Co., Milwaukee WI)

I/O modules are available in many different configurations, and voltages, (AC and DC).
Special modules are available to read analog signals and produce analog outputs,
provide communication capabilities, interface with motion control systems, etc. The
input modules provide isolation from the “real world” control voltages, and give the
CPU a continuous indication of the on/off status of each input termination. Inputs sense
the presence of voltages at their terminals, and therefore usually have very low current
requirements. A PLC-5 I/O rack is shown installed in the lower right compartment of
Figure 7-1

Output modules receive commands from the CPU and switch isolated power on and off
at the output terminals. Output modules must be capable of switching currents required
by the load connected to each terminal, so more attention must be given to current
capacity of output modules and their power supply.

Programming devices

Every brand of PLC has its own programming hardware. Sometimes it is a small hand-
held device that resembles an oversized calculator with a liquid crystal display (LCD).
See Figure 12-3.
Computer-based programmers typically use a special communication board, installed in
an industrial terminal or personal computer, with the appropriate software program
installed. Computer-based programming allows “off-line” programming, where the
programmer develops his logic, stores it on a disk, and then “down-loads” the program
to the CPU at his convenience. In fact, it allows more than one programmer to develop

3
different modules of the program. An industrial computer terminal is shown in Figure
12-4.

Programming can be done directly to the CPU if desired. When connected to the CPU
the programmer can test the system, and watch the logic operate as each element is
intensified in sequence on the CRT when the system is running. Since a PLC can
operate without having the programming device attached, one device can be used to
service many separate PLC systems. The programmer can edit or change the logic “on-
line” in many cases. Trouble shooting is greatly simplified, once you understand the
addressing system.

Every I/O point has a corresponding address in the CPU memory. To understand the
addressing scheme we need to examine the various number systems that may be
encountered in PLC products. Chapter 13 makes a comparison of these systems.

Figure 12-3
Hand-held programmer for small logic controller, SLC 100 (Courtesy Allen-Bradley Co., Milwaukee WI)

4
 Figure 12-4
Industrial computer terminal (Courtesy Allen-Bradley Co., Milwaukee WI)

CHAPTER 13

Number Systems

We are all familiar with our decimal numbering system. It probably originated from the
fact that people have 5 digits on each hand, and it was easy to count on our fingers. It
has been said that if we had only 4 digits on each hand, we might have had numbering
system based on 8 instead of 10. However, when working with computer-type
equipment, we find that there are several strange, but more efficient, number systems
that allow better utilization of resources. In Chapter 11, we introduced the binary system
when discussing methods of coding and decoding information. In this chapter we will
define and compare the most common systems.

Decimal

The use of decimal numbers is the most common system in the world. Metric
measurements are a good example of decimal notation. It is based upon the power of 10.
When written, the numbers are arranged in columns. The rightmost column contains the
least significant digit (LSD), having a weight of 100, so the numbers are multiplied by
1. The next column has a weight of 101, with the numbers multiplied by 10. The third
column is 102, so all numbers are multiplied by 100, etc. The leftmost column contains
the most significant digit (MSD). Following is an example:

MSD LSD

Power of 10 103 102 101 100

Digits 9 7 4 6

5
 Dec. Values 9000 + 700 + 40 + 6 = 9746

The sum of the values is equal to the real decimal number.

Computer-type equipment depends upon the electrical state of discrete bits of electrical
information. See Figure 13-1. A bit is the smallest increment of information that is
available. An electrical signal can have only two (2) states - ON or OFF. Consequently,
all other numbering systems must ultimately be derived and encoded from binary
information.

Figure 13-1
Binary bit pattem

Octal

Octal numbers are usually used for storing addresses. There is a total of 8 bit patterns
that can be derived from 3 bits of information: 0,1,2,3,4,5,6, and 7. If we count from 0
and 7, we use every possible combination available with a block of three (3) bits with
nothing left over. In other words, if we count using a base of 8, we will have the most
efficient use of our memory for storing addresses. Note that the binary values below, use
blocks of three digits.

Octal counting compared with decimal:

Octal = Decimal Binary Octal = Decimal Binary

0 = 0 000 10 = 8 001 000

1 = 1 001 11 = 9 001 001

2 = 2 010 12 = 10 001 010

3 = 3 011 13 = 11 001 011

4 = 4 100 14 = 12 001 100

5 = 5 101 15 = 13 001 101

6 = 6 110 16 = 14 001 110

7 = 7 111 17 = 15 001 111

6
The octal system is used extensively in identifying I/O points as well as memory
locations. See Figure 13-2.

Figure 13-2
Octal bit pattem

Binary Coded Decimal (BCD)

Binary coded decimal (BCD) numbers provide read-outs in the familiar decimal
format. In this case, four (4) bits of information are required for each digit. There are 16
patterns that can be derived from four bits, but only the first ten patterns are used,
giving us 0 through 9. While this is more convenient to read, it does waste some
resources.

BCD encoding (See Figure 13-3):

BCD Binary BCD Binary

0 0000 10 0001 0000

1 0001 11 0001 0001

2 0010 12 0001 0010

3 0011 13 0001 0011

4 0100 14 0001 0100

5 0101 15 0001 0101

6 0110 16 0001 0110

7 0111 17 0001 0111

8 1000 18 0001 1000

9 1001 19 0001 1001

7
 Figure 13-3
Binary Coded Decimal (BCD) bit pattem

Hexadecimal

Hexadecimal numbers have a base of 16. This is the total number of binary
combinations that one can get from a block of 4 bits of information. In this case single
digit numbers are not limited to a maximum of 0 through 9, but continue with letters of
the alphabet, utilizing all available resources. A comparison of hexadecimal and decimal
counting is shown below.

Hexadecimal count 0 1 2 3 4 5 6 7 8 9AB C D EF

Decimal count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Instead of counting 0 through 9 as in the decimal, each column counts 0 through F,

which is the equivalent of 0 through 15 decimal. As each 4-bit column is added, they
increase by a power of 16. See following example.

Hexadecimal
Decimal

Powers of 16 163 162 161 160

+ 256 + 16 + 1 =
1111 = 4096 4369

+ 3840 + 240 + 15 =
FFFF = 65535
61440

+ 256 + 0 + 10 =
F10A = 61440 61706

With four columns of hexadecimal numbers, any number from 0 to 65535 can be
represented. One word of 16 bits can provide 65536 different numbers. See Figure 13-4.
These numbers are used to map and address large blocks of memory.

8
 Figure 13-4
Hexadecimal bit pattem

These various number systems are a bit strange to deal with, and are sometimes hard to
understand, but this gives one a tool for interpreting them when they are encountered.
As we discuss memory mapping in the following chapter, one will see how some of
them are applied.

CHAPTER 14

PLC Memory Structure

The memory structures of different PLCs are quite similar in concept, but you will find
variations in addressing and the way they are displayed. The structure that we will use
for our examples relates to Allen-Bradley PLC-5 equipment. There is no attempt to fully
describe this product, as its capabilities go far beyond the examples we will use.
Memory structures are divided into the following increments.

Bit

A bit is the smallest increment of information that computer-type equipment can work
with. As mentioned in earlier discussions, a bit has only two states. When it is
energized, the state is true, or 1. When it is not energized, the state is false, or 0.

Byte

Eight (8) bits make up a byte. A byte is the smallest increment of information that can
transmit an ASCII character. ASCII is the abbreviation for American Standard Code for
Information Interchange, and is used to transmit data between computers and peripheral
equipment. Each letter, space, number, and character in this book requires a byte of
information so that it can be sent to a printer.

9
 Figure 14-1
Bit, Byte, Word, File relationships

Word

A word is made up of sixteen (16) bits or two (2) bytes. The byte with the lowest
address numbers is called a lower byte, and the one with the higher addresses is referred
to as an upper byte. See Figure 14-1.

The sixteen bits may have octal or decimal addressing. In our example, words related to
I/O have octal addressing, 0 through 7 and 10 through 17. Other words have decimal
addressing, 0 through 15.

File

A file contains any number of words. Files are separated by type, according to their
functions. Figure 14-2 shows the memory organization of a PLC-5 controller. The files
range from 32 to 1000 or more words per file. The Integer and Floating Point files allow
the PLC to make complex computations, and display data in Decimal, Binary, Octal,
and Hexadecimal formats. Since we will be comparing relay logic with a PLC program,
most of our discussion will be directed to Output Image, Input Image, Timer/Counter,
and Main (user logic) files.

10
 Figure 14-2
Memory organization for Allen-Bradley PLC-5

System Addressing

The key to getting comfortable with any PLC is to understand the total addressing
system. We have to connect our discrete inputs, push-buttons, limit-switches, etc., to our
controller, interface those points with our “electronic ladder diagram” (program), and
then bring the results out through another interface to operate our motor starters,
solenoids, lights, etc..

Inputs and outputs are wired to interface modules, installed in an I/O rack. Each rack
has a two-digit address, each slot has its own address, and each terminal point is
numbered. With this product, all of these addresses are octal. We combine the addresses
to form a number that identifies each input and output.

I/O Addresses

11
Figure 14-3 shows a very simple line of logic, where a push-button is used to turn on a
lamp. The push-button and lamp “hard-wiring” terminates at I/O terminals, and the
logic is carried out in software.

We have a push-button, wired to an input module (I), installed in rack 00, slot 0,
terminal 04. The address becomes I:000/04.

An indicating lamp is wired to an output module (O), installed in rack 00, slot 7,
terminal 15. The address becomes O:007/15.

Image table addresses

File 0 in the memory is reserved as an output image table. (See Figure 14-2). Every
word in file 0 has a three-digit octal address beginning with 0:, which can be interpreted
as the letter O for output. The word addresses start with octal 0:000 to 0:037 (or higher).
This number is followed with a slant (/) and the 2-digit bit number.

File 1 is reserved as an input image table. Every word in file 1 has a three-digit octal
address beginning with 1:, which can be interpreted as the letter I for input. The word
addresses start with octal 1:000 to 1:037 (or higher). This number is also followed by a
slant (/) and the 2-digit bit number.

Figure 14-3
Solution of one line of logic

12
Our input address, I:000/04, becomes memory address 1:000/04, and the output address
O:007/15 becomes memory address 0:007/15. In other words, type of module, rack
address, and slot position identify the word address in memory. The terminal number
identifies the bit number.

If you know the address of the input or output, you can immediately check the status of
its bit by calling up the equivalent address on the CRT screen.

Scanning

When running, the CPU scans the memory continuously from top to bottom, and left to
right, checking every input, output, and instruction in sequence. The scan time depends
upon the size and complexity of the program, and the number and type of I/O. The scan
may be as short as 15 milliseconds or less. 15 milliseconds per scan would produce 67
scans per second. This short time makes the operation appear as instantaneous, but one
must consider the scan sequence when handling critically timed operations and sealing
circuits. Complex systems may use interlocked multiple CPUs to minimize total scan
time.

As the scan reads the input image table, it notes the condition of every input, then scans
the logic diagram, updating all references to the inputs. After the logic is updated, the
scanner resets the output image table, to activate the required outputs.

In Figure 14-3, we have shown how one line of logic would perform. When the input at
I:000/04 is energized, it immediately sets input image table bit I:000/04 true (on). The
scanner senses this change of state, and makes the element 1:000/04 true in our logic
diagram. Bit 0:007/15 is turned on by the logic. The scanner sets 0:007/15 true in the
output image table, and then updates the output 0:007/15 to turn the lamp on. Figure 14-
4 shows some optional I/O arrangements and addressing.

Some manufacturers use decimal addresses, preceded by an X for inputs and Y for
output. Some older systems are based on 8-bit words, rather than 16. There are a
number of proprietary programmable controllers applied to special industries, such as
elevator controls, or energy management, that may not follow the expected pattern, but
they will use either 8 or 16 bit word structures. It is very important to identify the

13
 Figure 14-4
I/O addressing scheme

addressing system before you attempt to work on any system that uses a programmable
controller, because one must know the purpose of each I/O bit before manipulating them
in memory.

To illustrate the logical power of a PLC, the following chapter summarizes a typical
instruction set. It will be obvious that there is the capability of developing very complex
programs far beyond the scope of our discussions.

CHAPTER 15

PLC Instruction Set

Types of Instructions

There are several types of instructions that are available in a PLC. The instruction set
will very depending upon the brand and type of processor that is used. A. PLC-5 has
nine (9) types of instructions.

1. Bit level - Bit level instructions include examine on, examine off, output energize,
output latch, output unlatch and one shot. These are the most common instructions used
for simple ladder diagrams and are treated as relay logic. Combinations of examine on
and examine off instructions with branching, appear as NO and NC contacts
respectively. The output instructions appear as coils in the diagram.

14
2. Word level - There are over twenty (20) word level instructions that use sixteen (16)
bit words for calculations, comparisons, conversions, and masking. These instructions
appear as blocks, identifying the word addresses, and the desired function, activated by
one or more bit level instructions.

3. File level - These instructions allow the use of multiple word files to perform file
arithmetic and logic, file search and compare, sequencer output, sequencer input, and
sequencer load functions.

4. Timers and Counters - Timers and counters include timer on-delay, timer off-delay,
retentive timer, up-counter, down counter, and reset. These instructions reserve three (3)
sixteen bit words (total 48 bits) for their respective functions in a special file. They also
appear as block instructions that display time-base, preset values and accumulated
values as the instruction operates. These instructions are controlled by by bit level
instructions.

5. Program control - There are ten (10) program control instructions used for such
functions as sub-routines, label, jump, immediate inputs and outputs and related actions.
These appear as block instructions in the ladder diagram.

6. Communications - Three (3) instructions allow block transfer reads and writes, and
message handling. These allow the exchange of data between remote processors and I/O
racks.

7. Shifting - Five (5) instructions allow manipulation of bits within words. These
include the ability to perform FIFO (first-in, first-out) functions.

8. Diagnostic - Three (3) instructions include file bit compare, diagnostic detect, and
data transitional functions.

9. Miscellaneous - PID which provides a proportional, integral, derivative control that

can be tuned to match process requirements.

This is a very powerful instruction set that requires a lot of training to fully utilize its
total capabilities. Most simple operations utilize the bit level and timer/counter
instructions, and when printed out, appear very similar to a relay ladder diagram.

Most electricians, who are familiar with relay circuits, can usually trouble-shoot the
simpler PLC systems without formal programming experience. However, they must
learn the operating techniques required to manipulate the programming and monitoring
system without causing faults. As mentioned earlier, it is most important to understand
the addressing system so one can recognize the function of each symbol shown on the
PLC programming screen when trouble-shooting. Following are definitions of many of
the available instructions.

15
 Figure 15-1
Bit-level instruction logic

Bit Level Instructions

Let's look first at bit level instructions that are the most common instructions found in
the simpler PLC installations. These instructions follow the general pattern of the ladder
diagrams related to relay logic. See Figure 15-1.

Examine on is often abbreviated XIC, appears as a NO contact. If the element is not

energized, the contact appears on the CRT screen with normal intensity. When
energized, the contact will appear intensified, indicating that we have a conducting
element in our ladder diagram. The element can be an input, or be derived from an
output, or relay function within the program. The fact that this is an examine instruction
means that we can look at the status of any input or output element as often as
necessary, and add it to a new rung. If this were a relay ladder diagram, we would have
to add another isolated contact each time we needed to include the status of any relay.

Examine off, abbreviated XIO, appears as a NC contact. If the element is not energized,
the contact will appear as a conducting element, intensified on the screen. If it changes
to an energized state, the element will revert to lower intensity, appearing as a non-
conducting element in our ladder diagram. As above, we can examine any other input or
output as often as necessary to determine that it is not energized.

Output energize, (OTE) will be the last element on the right side of our ladder diagram,
and symbolize a coil. When all necessary conditions in the rung are “true” (conducting),
the output will appear intensified. This will turn on any load that this is connected to its
terminal in the I/O rack. We can add as many XIC and XIO instructions as we need in
our program, addressed from this output, to show its status.

Output addresses that are not assigned to an I/O rack can be used as internal relays
within the program. This is useful in cases where a complex set of conditions are
required in many rungs of logic. One can build one complex rung, terminating with a
relay address, then merely examine that relay's status with a single “contact” in each
rung that requires its logic, simplifying the program, and saving memory.

16
Output latch (OTL) and Output unlatch (OTU) instructions are always used in pairs
with the same address. When conditions are true in an OTL rung, the output will turn
on, and remain on after the conditions turn false (off). A separate rung must be used to
activate an OTU (unlatch), with the same address, to reset the original OTL to an
unlatched condition.

One shot (ONS) outputs only stay on for one scan after the rung is true. This provides a
pulse to control a following rung. The ring must go false before another pulse can be
repeated. This is a useful instruction, often used to provide a “triggering” signal when
an object first covers a limit switch, without holding a maintained signal that might
interfere with following logic. In other words you can have a single short pulse from an
input that may be held energized for a sustained time interval.

Word Level Instructions

Following are brief descriptions of word level instructions used principally to work
with numbers and shift registers. Analog input and output values are usually stored and
manipulated as words.

Compute (CPT) instruction performs copy, arithmetic, logical and conversion

operations. It is an output instruction that performs operations you define in an
expression, and writes the result into a destination address. It can copy data from one
address to another and convert the source data to the data type specified in the new
address (e.g. convert octal numbers to hexadecimal, etc.).

Add (ADD) instruction adds one value to another value, and places the result in a
destination address.

Subtract (SUB) instruction subtracts one value from another value, and places the result
in a destination address.

Multiply (MUL) instruction multiplies one value by another value, and places the result
in a destination address.

Divide (DIV) instruction divides one value by another value, and places the result in a
destination address.

Square Root (SQR) instruction takes the square root of a value, and place the result in a
destination address.

Negate (NEG) instruction is used to change the sign (+ or -) of a value.

BCD to Integer (FRD) instruction converts a BCD value to an integer value.

Integer to BCD (TOD) instruction converts an integer value to a BCD value.

Move (MOV) instruction copies a value from the source address to a destination every
scan. Often used to pick up a continuously changing input address and place it into a
continuous computation address.

17
Move with mask (MVM) instruction is similar to MOV except the move passes through
a mask to extract bit data from an element that may contain bit and word data.

Clear (CLR) instruction is used to reset all bits in a word to zero.

Bit inversion (NOT) instruction performs a NOT operation using the bits in a source
address. It inverts the status of bits, i.e., a (1) becomes a (0), and a (0) becomes a (1).
Figure 15-2 illustrates “truth tables” used to define several of these related instructions.

Figure 15-2
Logic truth tables

Bit-wise and (AND) instruction performs an AND operation using the bits in two source
addresses. The result is placed in a destination address. See Figure 15-2.

Bit-wise or (OR) instruction performs an OR operation using the bits in two source
addresses. The result is placed in a destination address. See Figure 15-2.

Bit-wise exclusive or (XOR) instruction performs an exclusive OR operation using bits

in two source addresses. The result is placed in a destination address. A (1) is placed in
the destination address if corresponding bits in source addresses are not equal. See
Figure 15-2.

18
Compare (CMP) is an input instruction that compares values and performs logical
comparisons. When comparison is true, the rung becomes true.

Equal to (EQU) is an input instruction that tests whether two values are equal, and
makes the rung true when the values are equal.

Not equal to (NEQ) is an input instruction that tests whether two values are not equal,
and makes the rung true when the values are not equal.

Less than (LES) is an input instruction that tests whether one value is less than a second
value, and makes the rung true when the conditions are true.

Less than or equal to (LEQ) is an input instruction that tests whether one value is equal
to or less than a second value, and makes the rung true when the conditions are true.

Greater than (GRT) is an input instruction that tests whether one value is greater than a
second value, and makes the rung true when the conditions are true.

Greater than or equal to (GEQ) is an input instruction that tests whether one value is
equal to, or greater than a second value, and makes the rung true when the conditions
are true.

Circular limit test (LIM) is an input instruction that tests whether one value is within
the limits of two other values. Rung is set true when condition is true.

Masked equal to (MEQ) is an input instruction that passes two values through a mask,
and test whether they are equal. Rung is set true when condition is true.

File Level Instructions

File arithmetic and logic (FAL) is an output instruction that performs copy, arithmetic,
logic, and function operations on the data stored in files. It performs the same operations
as CPT instruction, except FAL works with multiple words, rather than single words.

File search and compare (FSC) is an output instruction that performs search and
compare operations on multiple words. Performs same operations as CMP which is
limited to single words.

Sequencers

Sequencer instructions are used to control automatic assembly machines that have a
consistent and repeatable operation using 16 bit data.

Sequencer output (SQO) is an output instruction that steps through a sequencer file of
16-bit output words whose bits have been set to control various output devices. When
the rung goes from false to true, the instruction increments to the next (step) word in the
sequencer file.

19
Sequencer input (SQI) is an input instruction used to monitor machine operating
conditions for diagnostic purposes by comparing 16-bit image data, through a mask,
with data in a reference file.

Sequencer load (SQL) is an output instruction used to capture reference conditions by

manually stepping the machine through its operating sequences and loading I/O or
storage data into destination files. (A machine “teaching” tool).

Timer and Counter Instructions

Timers and counters are shown in the position of outputs in the PLC print-outs. As
mentioned earlier, they appear as block instructions, and are controlled by XIO, XIC, or
other contacts in their respective rung of logic. The done (DN) bits of the timers and
counters are energized when timing or counting values match the preset values, and are
used as contacts in other rungs as required - as often as necessary.

Timers also have a Timer timing (TT) bit that is energized whenever timing is in
progress. Energized bit (EN) is true (on) whenever the rung is true. See Figure 15-3.

Timer on-delay (TON) will have a selectable time base (e.g. 0.01, 0.1, 1.0 seconds), a
selectable preset showing the number of increments of the time base to be used for the
time delay, and the accumulated value while the timer is running. When the
accumulated value equals the preset, the DN bit will turn on.

Timer off-delay (TOF) will have the same functions, but will turn on when its rung is
true, and hold its DN bit energized for the preset time after its rung turns false (off).

Figure 15-3
On-delay timer ladder diagram

20
Retentive timer (RTO) operates similar to a TON, but accumulates time whenever its
rung is true, holds that value when the rung becomes false, and then resumes timing
where it left off each time the rung is true. When the accumulated value equals the
preset, the DN bit is energized and held on. A separate rung must be provided to control
a Reset instruction (RES) having the same address as the RTO. When the RES
instruction is true, it resets the RTO accumulated value to zero.

Count up (CTU) and Count down (CTD) instructions count up or down one increment
each time their respective rung is energized. A DN bit is set when the accumulated value
is equal to the preset. CTU and CTD instructions can be used in pairs, having the same
address. A RES instruction with the same address is used to reset the accumulated value
to zero, similar to the RTO instruction. An Overflow bit (OV) is turned on if the count
exceeds the preset of the counter. All these bits can be used where needed, anywhere in
the program, and as often as necessary.

Program Control

Immediate input (IIN) is an output instruction used to update a word of input image
bits before the next normal update, by interrupting program scan momentarily.

Immediate output (IOT) is an output instruction used to update an I/O group of outputs
before the next normal update, by interrupting program scan momentarily.

Master control reset (MCR) instructions are used in pairs to create program zones that
turn off all non-retentive outputs in the zone. Allows one to enable or inhibit segments
of the program as might be needed in recipe applications.

Jump (JMP) is an output instruction that allows one to skip portions of the ladder logic.
It is used with LBL which designates the destination of the jump.

Label (LBL) is an input instruction that identifies the destination of a JMP instruction.

Jump to subroutine (JSR)

Subroutine (SBR)

Return from subroutine (RET)

JSR, SBR, and RET instructions direct the processor to go to a separate subroutine file
within the ladder processor, scan that subroutine file once, and return to the point of
departure.

Temporary end (TND) is an output instruction that returns the scan to the beginning of
the program. Often inserted progressively through the program for debugging and
trouble-shooting a program.

Always false instruction (AFI) is an input instruction that can be temporarily used to
disable a rung during testing and trouble-shooting.

21
Communications Instructions

Block transfer read (BTR) is an output instruction that can transfer up to 64 words at a
time from an I/O chassis or supervisory processor.

Block transfer write (BTW) is an output instruction that can transfer up to 64 words at a
time to an I/O chassis or supervisory processor.

Message (MSG) is an output instruction used to send “packets” of up to 1000 elements

of data between processors on a data highway network.

Shifting Instructions

Bit shift left (BSL) used to move bits one address left.

Bit shift right (BSR) used to move bits one address right.

Bit field distributor (BTD) used to move bits within a word.

Fifo load (FFL) used to load a first in, first out file, storing words in a “stack”. Used
with FFU.

Fifo unload (FFU) used to provide first in, first out operation, removing words from an
FFL “stack”.

Lifo load (LFO) used to load a last in, first out file, storing words in a “stack”. Used
with LFU.

Lifo unload (LFU) used to provide last in, first out operation, removing words from an
LFO “stack”.

The above instructions are output instructions used to move bits in various modes for
shift register operations. Can be used to track product as it moves down a processing
line.

Diagnostic Instructions

File bit compare (FBC) is used to compare I/O data against a known, good reference,
and record mismatches.

Diagnostic detect (DDT) is used to compare I/O data against a known, good reference,
record mismatches, and update the reference file to match the source file.

Data transitional (DTR) is used to pass source data through a mask and compare to
reference data, then write the source word into the reference address of the next
comparison.

Miscellaneous Instructions

22
Proportional, integral, derivative (PID) is a complex instruction used for process control
for such quantities as pressure, temperature, flow rate, and fluid levels. Inputs are
brought in through A/D converters, and processed as integer numbers. After
comparative calculations are made, the integer numbers are sent out as outputs to D/A
converters for corrective control.

Summary

The instruction set listed in this chapter is not all inclusive nor have we tried to
document all the ways these instructions can be applied. Bit level, relay instructions and
timer/counter instructions are the most common elements that will be found in single
machine operations. As production lines become more complex, with inter-dependent
operations between machines, you will find more and more of the complex instructions
used. This list will help one identify the type of logic being processed, if some of the
more complex instructions are encountered.

Since we are comparing simple PLC programs to ladder logic, we will limit our
applications to the more common instruction sets described above. You will find similar
instructions in most brands of PLCs. The configuration of timers and counters may
appear differently, but the same functions will usually be present.

One can visualize a simple PLC program as a relay schematic whose relays have a
limitless number of contracts. The logic, however, examines the state of each relay, not
actual hardware, and we just add another contact to the schematic wherever required.

CHAPTER 16

How Do PLCs Compare to Relay Logic?

In early chapters, we discussed ways we apply logic to design and trouble-shoot

electrical ladder diagrams. We also discussed the principal characteristics of
programmable logic controllers and the available instructions sets. In this chapter, we
will illustrate how this logic can be compared with a PLC program.

In Chapter 3, the schematic of a motor control circuit with a run/jog option was
illustrated in Figure 3-1. We will use this simple circuit to illustrate a conversion to PLC
control with some enhancements.

PLC installations require “hard-wired” components, terminating at input and output

terminals, where they interface with the software program. This means that we have to
provide documentation for both the hard-wiring and the software logic.

The most difficult hurdle we face in trouble-shooting a PLC installation is interpreting

the designer's interface addressing. A high percentage of industry's documentation
requires switching back and forth between multiple drawings, print-outs, and instruction
books to identify which component (or function) is represented at each input. On the
other hand, we have the same problem identifying what happens as each output is
energized.

23
Some vendors provide drawings of the hard-wired components, using only their
abbreviated identification, terminating at input address- es with no explanation of the
functions. The software is provided as a computer print-out which often has no
annotation to identify function of each rung. This requires one to look up a table that
may be buried in the instruction book, or on an obscure drawing to learn what each
abbreviation means. It is so cumbersome that the logic might as well be considered
proprietary, as only the manufacturer can decipher it with any expedience.
Annotation and element indexing are available from most PLC manufacturers, and
should be supplied to the customer. If a consistent pattern of properly labeled hard-
wired components and program elements is followed, a comparison of the schematic
with a separate annotated program print-out can be considered an acceptable
documentation for trouble-shooting.

Figure 16-1 illustrates a documentation system that is often incorporated in industrial

machine controls. The inputs are shown as hard-wired components connected to the
high side of the control circuit, and terminating at PLC input addresses. Each input
appears as close as possible to the related ladder rung in the program running down the
center of the drawing. Each rung is annotated to identify its purpose.

Outputs are shown, picking up their power from their respective output addresses, and
terminating at the low side of the control circuit.

Rungs can be numbered similar to relay logic ladder diagrams, and the locations where
each input and output is examined are noted at each terminal point on the drawing.

Analyze the Sample Program

Some unique conditions that must be considered when using a PLC are illustrated in
Figure 16-1. As we trace through the logic, one will note that we are “examining” the
status of each input and output terminal, not looking at the discrete hardware
component.

On the left of our drawing, we have shown a NC Stop push-button, a NO Start push-
button, a NO Run/Jog selector (run position), and a NC motor overload contact. Each of
these connect to an input address, corresponding to their I/O rack terminal location.

Rung #1 starts with an apparently NO XIC contact element, addressed to the NC Stop
push-button, followed by another XIC

24
 Figure 16-1
Motor contactor circuit, using PLC logic

addressed to the NC motor overload contact. One might ask, “Why are we showing NC
inputs as NO elements in our program?” You will recall that an XIC element becomes
true (conducting) when its input address is true. If the NC Stop push-button does not
change state, the input I:012/01 will be energized and make the XIC true in the ladder
diagram. If the push-button is opened, the address becomes false, and de-energizes the
rung to shut down the motor.

The same logic applies to the motor overload contact input I:012/04. If an overload
occurs, this address will be de-energized, and its XIC will de-energize the rung, and shut
down the motor.

With the first two elements true, the next bit of logic is examining the Start push-button
input at I:012/02. If we press this NO push-button, we make all of the elements true that
are required to energize the output O:013/06. This will activate the XIC element with
the same output address in the lower branch of this rung, and if I:012/03 is not true, the
output will remain energized when the Start push-button is released.

If the Run/Jog selector switch is turned on, to select the jog function, I:012/03 XIO will
stop conducting, and the output can only be true when the Start push-button is held in a
true condition. It cannot seal in.

If we did not bring the motor overload contact in as an input, the motor contactor M
could drop out on overload, even though the output logic showed it to be energized. We
added another rung at line 3 that will turn on an output, addressed to activate a warning
light at O:013/07, when input I:012/04 goes false from a tripped overload.

25
With this rung, we can tell why the motor contactor shut-down. If an overload occurs,
O:013/06 will turn off, and O:013/07 will be turned on.

Many levels of “branching” can be included in a single rung of logic. Very complex
multi-path input structures can be assembled, controlling a single output, or sometimes
multiple outputs. In lengthy programs, an expert programmer may save programming
memory, and optimize scan time by using this capability. However, this complexity does
not lend itself to easy trouble-shooting by someone who is unfamiliar with the program
logic. If memory is adequate, and scan time is not critical, it is adviseable to break
simple programs into more rungs of simple logic that can be adequately annotated, and
understood by more people.

Large applications, requiring multiple interlocked PLCs, require personnel who have
PLC communicating skills. It is unlikely that a maintenance person who has not had
extensive training would be expected to take the responsibility those complex systems.
Most electricians can pick up the needed knowledge to work on systems that emulate
relay logic, and those are the people this material is directed to.

CHAPTER 17

Convert Relay Logic to PLC

In Chapter 6, we developed the relay schematic diagram for the conveyor control
system. We will use the same application to illustrate how it can be represented in a
PLC system. Compare Figure 6-4 (or Figure 9-1) with Figures 17-1, 17-2, and 17-3 as
the discussion continues.

Power Considerations

In an earlier chapter, we mentioned the fact that most inputs provide a “voltage present”
signal to the input modules. Current is really not a problem in most instances, but
voltage quality is important. The CPU requires a power source that is as free as possible
of line disturbances. Since there are minimum disturbances created by input signals, it is
common practice to use a common power source for the CPU and inputs.

However, outputs must switch loads with varying currents. Often a large contactor or
solenoid will not only draw a high in-rush current, but also create a high-voltage
inductive voltage spike when de-energized. If the CPU is subjected to these
disturbances, its low-level logic components may be damaged, followed by erratic
operations or premature failure. On large installations, a separate load transformer is
recommended for the outputs, isolating the inputs and CPU from load-created line
disturbances.

When working with solid state devices, we must remember that there are “leakage
currents” present even during apparent OFF condi- tions. If an element fails, the
leakage currents may increase to a point where it may fault in the ON mode. This failure
may turn ON other logic, causing dangerous, unpredictable operations. For this reason,
a “hard-wired” emergency stop circuit should always be installed to shutdown the
output power supply in the event of an electronic fault.

26
Figure 17-1 illustrates one way the above requirements can be shown. Comparing this
schematic to Figure 6-4, you will see that we have a control transformer CX, and a
separate load transformer LX. Each transformer has its own output control switch. The
control circuit has “pull-on, push-off” push-button controlling the system's only relay
ES, whose contacts control the power to the input circuits and output modules. This
allows de-energizing all inputs and outputs, while maintaining power to the CPU for
check-out and trouble-shooting. Logic Considerations

The input and output modules have been shown as simple blocks to show power wiring.
The input terminal addresses shown on the left side of the schematic represent terminals
on the input modules. The outputs on the right side of the schematic receive their power
from output terminal addresses on the output modules.

The programmed logic is shown in the center of the drawing, and represents the lines of
logic that you observe on your CRT screen. An effort is made to show inputs and
outputs as close as possible to their first occurrence in the logic diagram. This
arrangement helps a trouble-shooter, not familiar with the circuit, to quickly see an
obvious pattern of logic.

Indexing

All hard-wired circuits have been assigned wire numbers. Each line of logic is indexed
on the left margin. Inputs and outputs are indexed to show the lines of logic where their
elements are used. Each line of logic is annotated to identify its function, either on its
line, or adjacent to it.

Programming Considerations

On line 13, the three overload contacts are connected in series and connected to input
address 1:000/00. When all contacts are in their nor-

27
 Figure 17-1
PLC conveyor control

mally closed condition input 1:000/00 is true (ON). The first line of logic examines this
address for a false (OFF) condition which turns on the output 0:001/00 to energize the
OL (overload) indicating lamp. Since the input is normally energized (true), the lamp
will not be lit until the input circuit is broken and voltage is not present on wire #8.

Indexing shows that 1:000/00 is also examined on lines 14, and 15, for a true (ON)
condition. These three lines must see a true 1:000/00, indicating no overload condition,
before any other logic can proceed. We can examine any address as often as necessary
in any line of logic.

On line 14, address 1:000/01 is true when our selector switch is set on Auto. If 1:000/00
and 1:000/01 are both true, output 0:100/00 will be true. This output is being used as an
internal relay to store this information. Unused output addresses can be used for internal
relays. Note that actual inputs and outputs are addressed to rack 00. The relay output in
this rung is addressed to rack 10 which is not being used for real outputs, but is
available in the output image table. Note that this “relay” is examined in eight (8) other
rungs of logic.

28
Line 15 has the same logic to store the information that Hand has been selected. It is
examined in three (3) other rungs of logic.

Line 16 is the first rung that is initiated in the Auto mode and starts the on-delay timer
controlling the start of conveyor 3. It requires that Auto is selected, the Auto-start PB
pressed, and Auto-stop true, to start the timer T4:0. The “energized” bit, T4:0/EN, is
used to seal this rung ON until Auto-stop is de-energized. If you look ahead to Figure
17-2, you will see that T4:0/EN is also used as a holding contact for the warning circuit
on line 19.

Here is an instance where the rung sequence is important. Bits 0:100/01, 1:000/03, and
1:000/04 are used in rungs 16 and 18 as start/stop control for both rungs. If the
“warning” rung were programmed in a sequence ahead of the T4:0 timer, that rung
would not seal in, because the scan would leave the warning rung before the timer is
activated to supply the sealing contact T4:0/EN.

Continuing with Figure 17-2, we find the rest of the logic required to provide automatic
starting and stopping sequence. Bit 0:100/00 appears in every rung, identifying them as
automatic rungs. Off-delay timers T4:3, T4:4 and T4:5 have identical logic including a
T4:0/EN bit

Figure 17-2
PLC conveyor control, continued

and a 1:000/04 auto/stop bit that keeps them energized during the entire Auto-run
operating time. The T4:0/DN bit in rung 20 starts T4:1 timer after 15 seconds, and

29
T4:1/EN bit turns on C3 in rung 45, starting conveyor 3. (See Figure 17-3). A T4:1/EN
bit provides a sealing path parallel to T4:0, keeping it energized when T4:0 is cancelled
during Auto/stop cycle.

After another 15 seconds, T4:1/DN energizes T4:2 whose EN bit turns on C2 in rung
43, starting conveyor 2.

After another 15 seconds, T4:2/DN energizes (relay) 0:100/02 to turn on C1 in rung 41,
starting conveyor 1. 0:100/02, NC element in rung 18 goes false and shuts down the
warning signal.

Pressing the Auto-stop PB makes 1:000/04 false, de-energizing rungs 16, 19, 25, 27, and
29. The off-delay timers are de-energized, but C1, C2, and C3 hold in. As each timer
times out, conveyor 1 drops out after 15 seconds, conveyor 2 drops out after 30 seconds,
and conveyor 3 drops out after 45 seconds.

Rungs 31, 33, and 35, are constructed similar to Figure 6-3, with a manual mode bit
0:100/01 leading each rung. Jog functions are controlled by bits related to 1:000/13
input from the Run/Jog selector switch.

Interlock contacts for C1, C2, C3 have been brought in as inputs. When the respective
contactor is energized and pulled in, these inputs will turn on the respective indicating
lamp outputs to “prove” contactor action.

Each output, controlling C1, C2, C3, has parallel automatic and manual control bits
derived from the preceding logic, so either system can control the conveyors.

Comparisons

If you compare the PLC logic with the relay logic shown in Figure 6-4, you can trace
patterns that are almost identical. In many cases, the Logic will be provided as a
separate print-out. The inputs and outputs are often annotated where used on the print-
out to identify their functions. Most software will also print-out a cross-reference table
identifying every I/O and internal relay address, and the rungs where they will be found.

In this case there should be a separate wiring diagram showing the schematic layout of
hard-wired components, terminating at respective I/O

30
 Figure 17-3
PLC conveyor control, continued

addresses. Experience has proven that there are varying degrees of clarity in these
interface drawings, depending upon the draftsman's style.

There should always be a chart listing all components, their function, and location in the
documentation.

There are a lot of options for the hard-wire layout. As an example, we might have
eliminated two (2) inputs if we had used wire #9 from the selector switch as the source
of power for Auto-start and Auto-stop in Figure 17-1, and wire #10 as the source for all
“hand” functions in Figure 17-3. Internal relays 0:100/00 and 0:100/01 would not be
used, but we would have had to provide additional logic to latch-in Auto and Hand
operations in the rungs that follow. The use of the selector switch inputs in our example,
simplifies the programming requirements, because the modes of operation are
effectively latched-in at the input terminals.

An experienced programmer could also use short-cuts to pick multiple time intervals
from a single timers, by monitoring the “running” bits in the “accumulator” word of the
respective timer. While this might save some resources, it would make it more difficult
for an “outsider” to decipher his logic.

31
These examples of programming options emphasize the diversity of logic that one
might find for any given application. Patterns of logic are only limited by the
imagination of the circuit designer.

CHAPTER 18

PLC Start-up and Trouble-shooting

Start-up or commissioning of a PLC installation is carried out much like our previous
discussion in Chapter 9. The same precautions must be taken to prevent accidental start-
up of equipment in the event of a fault. One should lock-out power to motor contractors,
and other power devices while testing the logic in a systematic sequence.

The principal difference lies in the use of the Programmer CRT to verify operating tests.
Point to point voltage tests can be made with a multi-meter to verify proper hard-wire
connections through wires #1 through #4A, Figure 17-1. The PLC can be tested per
manufacturer's recommendations for proper set-up, and connections to the programming
terminal. The first tests will be made with the output control switch in the Off position
so that all outputs are disabled. Consider Figures 17-1 through 17-3 in Chapter 17 as
one continuous schematic and program as we continue.

With the PLC in I/O monitor and control mode, we bring up each rung of the program
in sequence, and operate each input device. This mode may vary from one processor to
the next so you must determine how to bring up this screen on your CRT. The indicating
lamp should turn ON at each respective input terminal on the I/O rack when the its input
is true.

The first rung on line 13 should show no intensified elements if the input from wire #8
at I:000/00 is energized. If wire #8 is momentarily disconnected, input element 1:000/00
and output element 0:001/00 should intensify, indicating a break in the motor overload
circuit. The 1:000/00 elements on lines 14 and 15 should be intensified at all times,
unless wire #8 is disconnected.

If we turn our selector switch to Auto, 1:000/01 should intensify on line 14, and since
all elements are true, relay element 0:100/00 should be energized. All automatic rungs
from line 16 through 29 should show an intensified element 0:100/00 when Auto is
selected.

In like manner, if we select Hand, 1:000/02 should intensify on line 15, and if 1:000/00
is true, relay element 0:100/01 should intensify. All manual references to this element
should also be intensified where used on lines 31 through 35 when Hand is selected.

Pressing the Auto Start push-button when 0:100/00 is energized should turn on the rung
at line 16, to start the timer T4:0, and energize the warning output 0:001/01 on line 18.
As T4:0 times out, the other on-delay timers will cycle in sequence. As each element
becomes true, it will intensify on the screen, and turn on the output for each rung as its
required elements become true. The outputs on lines 41 to 45 should come on in their
timed sequence. The outputs at lines 38 to 40 will not turn on until output modules are
enabled, allowing the contractors to actually pull-in.

32
The Auto-stop cycle can be monitored in the same way. Then test the manual mode
inputs.

Most PLC systems also give you the capability to force inputs or outputs on or off to
check operations without going to the operator consoles. If someone is monitoring the
contractors, with output power on, you can determine if the proper device is connected
to each address. The big advantage is that you can prove most of your installation
quickly, without running around to watch relays cycle. Since there are fewer hard-wired
devices, there are not so many opportunities to have faulty wiring. A copy of the
program should be saved on tape or disc, so that it can be quickly restored if a CPU
must be replaced.

Histograms

Most modern systems give you the capability of developing and printing histograms. In
this case, you select any bit address, and literally watch and record the true and false
conditions in real time. This is particularly useful if you find intermittent false
operations, and have to locate the “culprit” that is causing the problem. It may be a case
of an intermittent limit-switch, that is either failing to operate every time, or possibly it
is bouncing and providing extra unwanted pulses. It can also help you locate
programming errors where a rung is not in its proper sequence so that it misses a sealing
or resetting function. This is most likely to happen if more than one programmer is
involved in creating the logic.

One illustration of the importance of logic sequence is a replication of the shift-register

circuits illustrated in Chapter 11. In the relay logic, zone B is used to reset zone A.
There is no scanning sequence, so it does not matter what order the ladder rungs are
drawn. However, to accomplish this with a programmable controller, all zones have to
be programmed in reverse order because zone B must be scanned first to see if it is reset
before zone A can send it a new code. This pattern is required for the entire code and
decode zone structure, otherwise a complete scan would have to be completed before a
reset could be made. In the time for one scan, the code might be overwritten in a
following rung before the scan returned to reset the zone. This could totally confuse the
logic.

One should think the logic through, one element at a time in “slow motion”, always
remembering the scanning sequence. A “contact” cannot change state until its line of
logic tells it to. If its reference is needed “up-stream” during a single scan, its rung will
have to be moved ahead of the required action.

While we have not tried to teach one how to program, it is important to realized that if
you modify the program to insert a new rung of logic, its sequence in the program must
be considered. You can't arbitrarily “tack it on” at the end of the program. Many
program flaws can be attributed to improper scan sequences. It is interesting to note that
several manufacturers call their CPU a “Sequencer”.

It is obvious that the materials covered in the past seven (7) chapters will not make the
reader an experienced PLC programmer. If one can grasp the concept of how the PLC
relates to the relay ladder diagram, it should help him cope with almost any
programmable controller that might be thrust upon him. Addressing and scan sequence

33
are probably the two most importance concepts that one should understand.
Programming techniques can be learned through exposure, but we would certainly
advise the technician to seek, as a minimum, a first level factory or distributor-
sponsored school where he will be taught how to work with the hardware, as well as the
instruction set.

A well-planned PLC installation can save thousands of dollars in materials and

installation costs. Maintenance is easier than fighting banks of electro-mechanical
relays, and reliability is excellent. It also gives a plant a communication link to its
processes that can provide statistical and production information that would not be
available with relays. However, the investment in a PLC installation could be in
jeopardy if the plant does not also invest in basic training for their maintenance
personnel so they can maintain the system intelligently.

CHAPTER 19

Logic Comparisons

Digital

The logic we have been discussing in our previous chapters has used discrete on and off
conditions for each element in a line of logic. In other words the logic depends upon the
true or false status of each element. There are only two (2) states that an element can
have, and no other variables. This is called digital logic. By combining a binary notation
with digital logic, we can represent discrete numbers that can be used for encoding,
decoding, counting, and various mathematical functions. Within a PLC or computer, we
can also store ASCII characters to represent alpha-numeric characters that can be
interpreted by a printer.

Analog

Another type of logic refers to continuous signals that represent a variable quantity over
a continuous range. This is refered to as analog logic. Analog means “analogous to” or
“equivalent to” another reference. Following are a few examples; a tachometer
generates an analogous voltage signal in proportion to a shaft (mechanical) rpm, a
thermistor controls current by changing resistance in proportion to changes in
temperature; a pressure device controls a voltage or current in proportion to changes in
pressure; a generator produces voltage in proportion to its excitation and speed, etc.
Note that these are proportional values. The devices that change energy from one form
to another are called transducers.

Analog signals, as a rule, are not linear over a very wide range, i.e., the ratio of input to
output will not be constant due to changes in heat, resistance, magnetic saturation, etc.
Therefore an analog system will tend to “drift” from its commanded performance over
time.

There is also a condition known as hysteresis which is a tendency for a device or system
to have two outputs for a given input. The output will tend to be low when the input
rises, and remain high as the input drops. The range is selected over a relatively short

34
spread of input changes so that it can be plotted as a relatively straight line and provide
minimum hysteresis and distortion.

Variable processes are considered analog applications, and all variable outputs provide
analog signals. Systems that have only analog controls are difficult to control with
precision because of the drift and hysteresis. This is especially true when trying to
synchronize multiple systems.

Converters

If we can combine the precision of digital logic with the variable analog logic, we can
greatly improve process control. This requires interface devices to convert analog
signals to and from digital formats.

A/D converter - This is the abbreviation for an analog to digital converter. This is a
device or circuit that converts an analog signal to a digital signal. The digital signal is
often represented as binary number that may provide a thousand (1000) or more discrete
values across a range of perhaps 0 to 10 vdc.

D/A converter - This is the abbreviation for a digital to analog converter. The device or
circuit converts digital signals to proportional analog signals. Again, the preciseness of
the output depends upon how many discrete values the binary number has available. If
the D/A converter has a number 0–1000 representing 0–10 vdc, a value of 500 would
provide an output of 5 vdc. In other words this could produce a precise output with the
accuracy of 0.01 vdc.

Signal Manipulation

Multiple A/D converter signals, sensing various conditions, can be brought into our
digital logic, probably by a PLC, and manipulated as necessary. For instance input
temperature reference and feed-back sig- nals might be sent to a comparator device or
circuit which would in turn produce an error signal that could be used to correct any
variance in system performance.

The various signals can be manipulated mathematically for internal scaling of values,
adding, subtracting, multiplying, dividing, and displaying as digital read-outs to an
operator's station. The final corrected calculations can then be sent out through a D/A
converter as a precise reference voltage.

The advantage of this arrangement is that the continuous calculations and corrections
minimize drift in the process. The digital signals always have discrete values that do not
change until modified by a change in their bit pattern. In an all-analog system, we
would likely be using resistors for voltage dividers and signal scaling. A pair of
opposing generator fields might serve as our comparator to provide the appropriate error
signals. This leaves the system susceptible to variable loading, resistance changes, and
electro-magnetic hysteresis that would allow it to drift above and below the selected
performance level.

Many industrial products have programmable digital parameters that can be used to
adjust range limits and change signal scaling. This allows one to fine-tune variable logic

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for optimum performance. In some AC variable speed drive products there are as many
as 2000 accessible parameters for adjustments and performance monitoring. Many
power products have their own CPU on-board as well as A/D converters to accept
different reference signals. They can also be linked to a PLC for digital remote control
and process monitoring.

CHAPTER 20

Applied Analog Logic

In our previous chapter, we introduced the concept of analog logic. If you have to work
with any process that has variables, you will likely have some analog logic to contend
with. To provide an example of analog logic, we are going to look at an analog control
system that was popular prior to the 1970's. It will illustrate ways the signals could be
manipulated, and you will also see the many components that contributed to drift and
hysteresis. This chapter will consider the analog logic required to control a DC motor.

DC Drive Logic

Industrial DC motors require a “drive system” to provide the necessary DC voltages to

the motor. The drive system may use a solid state Silicon Controlled Rectifier (SCR)
control, energized from an AC power source for the DC power, or a rotating DC
generator that is driven by an AC motor. There are thousands of older installations in
industry that still use a motor-generator set (M-G) for their power source. The common
control system is often referred to as a “Ward-Leonard” control. This system connects
the motor and generator armatures back to back so that the motor follows the voltage
and polarity of the generator to establish its speed and direction of rotation. Additional
auxiliary exciters (generators) are usually required to provide amplification and
controlled excitation for the generator and motor fields. We will use a Ward-Leonard
circuit to illustrate the DC motor logic because it allows us to follow the schematic
without getting lost in the electronics of an SCR drive. The minimum logic we will
discuss must be provided in all controls, electronic or otherwise.

How Does a DC Motor Work?

Before we attempt to define the logic required to control a DC motor, we need to review
the way the DC motor is constructed, and how its operation is controlled. The
mechanical/electrical construction of the DC motor is a lot more complex than an AC
motor and requires special control considerations. Figure 20-1 illustrates a cutaway of a
typical industrial DC motor.

There are two major parts to consider. One is the stator, or stationary “shell” of motor
which holds the magnetic field poles. While some motors use permanent magnets, the
vast majority are wound with a “shunt winding” to establish alternately North and South
poles. This winding is separately excited to provide precise control of the field current.
The available motor torque is determined by the flux density of this magnetic field as
defined by the ampere-turns (amperes times coil turns) available. The stator will also
have auxiliary poles between the shunt fields, called interpoles or commutating poles
that carry armature current. Their purpose is to correct magnetic distortion, caused by

36
the armature current and maintain a stable neutral zone for the brushes, to prevent
sparking.

The rotating member, called the armature, has many coils wound in slots in the
laminated iron core, and terminating at a current collector system called a commutator.
The commutator consists of many insulated copper segments which collect current from
the brush assembly, mounted in the end-bell of the motor.

When current is fed to the armature, magnetic poles are produced because of the unique
position of the coils and brushes at any given time. The interaction between the field
and armature magnetic fields produces torque as like poles repel, and opposite poles
attract. As the armature rotates, the commutator continuously switches armature coils to
maintain a constant magnetic relationship between the rotor and stator. The total
available torque is a summation of the field and armature magnetic field strengths.

Figure 20-1
DC motor structure

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Speed Regulation

DC motor armatures always generate a voltage which opposes the applied voltage. This
opposing voltage is called a counter-electromotive force, abbreviated Cemf. The Cemf
is dependent upon the field strength and the speed of rotation. The motor stabilizes its
speed when the Cemf is theoretically equal to the armature source voltage. With
constant field current, the armature speed varies directly with the applied voltage. When
the armature and field both have full voltage applied, the motor will run at its base
speed.

If the field strength is reduced while holding the armature voltage constant, the motor
must run faster to generate enough Cemf to balance the input voltage. This is a useful
characteristic that is used to drive the motor faster than the base speed. When operating
in this mode, the motor has constant horsepower characteristics because torque (field
strength) is falling off at the same rate as the speed is increasing. (Hp = Torque ×
Rpm/5252)

If the field loses excitation while the motor is running, the armature will accelerate until
the residual magnetic field can produce the required Cemf before the speed can
stabilize. The typical result is that the motor literally runs away, and ultimately explodes
from centrifugal forces. For this reason, it is imperative that the field has controlled
excitation at all times. A current-sensitive Field Loss relay or equivalent sensor should
always be provided to take the system off line if the field current drops below a
minimum level.

The Cemf is often used as a voltage feed-back in the control system to indicate that the
motor has reached the commanded speed. The operator gives a reference command, and
when Cemf matches it, the speed stabilizes at that point.

Cemf is also used to reverse current and provide counter-torque for controlled
regenerative braking of high-inertia machines when generator voltage is reduced.

Power Sources

Since there are two (2) separately controlled elements in a DC motor, we must supply
two power sources. It is also imperative that field exci- tation is applied first, and kept at
a safe operating level at all times. Armature voltage must be applied in a controlled
manner, starting from zero, because current is only limited by resistance or Cemf.
Armature resistances are very low - often less than 0.02 ohms. If high voltage is applied
while at rest, the in-rush currents will cause extensive damage to the brush and
commutator assemblies.

DC Schematic

We have established the “ground rules” for controlling the DC motor, and will now look
at a relatively simple schematic showing a generator-driven DC motor and minimum
control logic. See Figure 20-2.

As you scan down the center of the drawing, you can identify the power components
that are being used. At the top on line 1, we show a single-phase, full-wave, bridge

38
rectifier. We have not specified voltages, as they must be matched to the equipment you
are working with. This rectifier is often referred to as the constant potential source. In
many installations, a constant-potential exciter (generator) may be installed. Many older
installations now have rectifiers that have replaced a failed exciter.

The motor field exciter MFX, is shown as a generator having two control windings,
AF1–AF2, and AF3–AF4, with its output connected directly across the motor field
terminals MF1–MF2, through a current-sensing “field-loss” relay. The exciter could be
a small generator called an amplidyne, once manufactured by General Electric Co. A
few milliamperes of current on a control field can produce up to 250 vdc and 6 amperes
output for the motor field excitation. This amplification allows use of small, low current
devices to control very large power circuits.

The generator and motor armatures are shown connected back-to-back to form the
“power loop”. This circuit has an instantaneous over-load relay to protect against
sudden stalling loads, and an isolating loop contactor M. The contactor must be rated to
carry the expected DC current, and will require DC arc blow-out features. The logic is
designed to prevent opening this contactor under load, but it should be able to handle
any emergency service at rated current.

At line 11, we have the generator field exciter GFX, which is identical in construction to
MFX. If the generator field required a totally different current capacity, a different type
of exciter could be used.

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 Figure 20-2
Generator, DC drive logic

Control Components

Our relay logic is shown at the bottom of the schematic. All relays could be DC, or the
DC MF and M could have special AC coils. We have shown both AC and DC to identify
components that usually have DC rated contacts. When amplidynes are used, the
excitation currents are so low that AC relays that can break the low energy DC currents,
are sometimes applied as GF and MF relays.

The placement of the M and MF in the DC control circuit is a carry-over from the time
when a rotating constant potential exciter was used instead of the bridge rectifier. In that
case, if AC power was lost, the inertia of the rotating components could provide DC
control power to hold in M and MF long enough to bring the motor to a controlled
regenerative stop.

The master switch (controller) is constructed as a reversible “throttle” assembly. When

at neutral position (off), brushes #48 and #49 are both contacting the negative side of
the constant potential power - with no difference in potential. The potentiometer is
constructed in such a way that #48 picks up increasing positive voltage and #49 stays on

40
the negative bus in the forward direction. When operating in reverse, #49 picks up
increasing positive voltage while #48 stays on the negative bus. The master switch also
has a pair of cam-operated switches shown of lines 17 and 19 in the neutral, off
position.

The high side AC control voltage will require a control On/Off switch (not-shown)
ahead of wire #1.

Operating Sequence

We start with all control power on, including the bridge rectifier. The motor field
exciter MFX will receive a minimum excitation on its field AF1–AF2 through resistor
tap #32 on resistor R1. The resistor tap should be adjusted so that the output will
provide minimum rated motor field current and pull-in the field failure relay (FL).

If the Master Switch is in the off position, RS will now be energized and seal-in. If there
is an overload, or a field loss, RS will drop out immediately. RS closes an enabling
contact on line #19 as long as it remains energized. If an instantaneous overload trips
RS off, returning the master switch to OFF will reset it. This insures that the system
must return to zero speed, after any fault, before it can restart.

As the operator moves his master switch in either direction, the cam at #1-#2 closes to
instantly energize the off-delay timer TD. TD immediately picks up the motor field relay
MF which switches the motor field excitation to maximum on R1, line 2. This applies
full field on the motor for maximum torque.

MF on line 16 closes and energizes M to close the power loop between the armatures.
M on line 19 then enables GF to connect the reference field of the generator field exciter
GFX to the master switch circuits #48–#49. GFX amplifies this signal and energizes the
generator field at GF1-GF2. As the generator excitation builds up, current flows in the
power loop and the motor accelerates as it follows the voltage. Instantaneous polarities
are shown on the schematic for this condition.

Voltage Regulation

Generator output voltage is reflected across resistor R3, wires #38 and GA1. Tap #44
senses a percentage of generator voltage across the resistor to wire #38 with #44 having
the most positive voltage. We can use this adjustable voltage as a feed-back signal to
our reference. You will see that the reference signal to the generator field exciter passes
through resistor R7 and at this time #46 is more positive than #53. The excitation
current creates a voltage drop across the resistor. If we can run another current in the
same direction through the same resistor, we can increase its voltage drop, (increase
apparent resistance) and reduce the current that is flowing through the field AF1–AF2.
By adding a positive tap #44 on R7 nearest to #46, and a negative tap #38 nearer to #53,
we can provide an adjustable potential that is proportional to the generator voltage, and
use it as a feed-back to stabilize the voltage (speed) when the feed-back approximates
the original reference Current Regulation

41
Resistor R2 is connected across the motor and generator interpole coils using interpole
taps #36 and #38. A current surge will create an inductive voltage boost across the
interpoles which appears across R7. This is often found to be about 7 volts on many
installations with about 200% of rated loop current. We can calibrate this signal by
adjusting tap #37 with reference to #38. At this instant, #37 will be most positive.

R4 and R5 are called bias resistors, and are connected across the constant potential bus.
When #30 is positive, the current will pass through the diode at #40, through the resistor
to #43, and then through the GFX field AF4-AF3 to #38. #30 is the positive end of R4,
and #40 is more positive than #43, so we again can have two currents passing in the
same direction through a resistor. If we adjust the standing difference in potential
between #40 and #43 to 5 volts, no control current will flow until the potential across
#37 and #38 exceeds 5 volts. If the signal reaches 7 volts, then the bias circuit would
allow the equivalence of 2 volts to pass across R4 and through the field AF4-AF3.
Excitation is in opposite polarity to the reference, so this field will subtract from the
reference signals command. Thus when there is a surge of current, this serves as a
current limit, and over-rides the command reference to protect our system. We can
adjust the intensity of the signal on R2 and set its threshold on R4 for the point where it
is to become effective. The adjustment between #41 and #43 sets the bias voltage for
operation in the opposite direction.

Field Crossover

A wood veneer lathe drive often operates in the constant horsepower range because it
must speed up to maintain veneer sheet speed as the log gets smaller in diameter.
Reverse is used to back out of a jam, so does not require the field weakening control.
The circuit shown is quite primitive for 1995, but the concept is valid. In this case we
are using the MFX field AF4-AF3 to subtract from the reference field, and in turn
weaken the motor field for higher speeds. The voltage signal is derived from tap #34 on
R3, and wire #38. #34 is most positive and we use taps #38 and #39 on R5 to set the
“spill over” armature voltage that we want to reach before we start field weakening.
Note that #39 must be set more positive than #38. Tap #34 on R3 determines the
maximum signal that we need to pick off.

Regenerative Braking

If we suddenly return our “throttle” to zero, GF will immediately drop out, and transfer
the reference field of GFX to the voltage appearing across #38 and #34. Note that this
voltage always has a polarity that is opposite to the reference voltage. TD will hold MF
and M energized for a preset interval, usually about 3 seconds.

While the motor is still turning, with full field excitation, it is generating considerable
voltage. Since this voltage opposes the generator output, the current in the power loop
reverses, but if you look closely the voltage across #38-GA1, it does not change
polarity. This voltage is applied through GF to the GFX in reverse polarity and drives
the Generator output to zero. This is often called a “suicide circuit”. The motor comes to
a stop at a rate controlled by the current limit circuit, whose polarity has also reversed to
cushion the stop. If there is no command to restart within about 3 seconds, MF will be

42
released by TD, reducing the motor field to a stand-by condition and then deenergize M
to open the power loop.

When the master switch is operated in opposite direction, all polarities reverse, and
action is the same, except in this instance, field weakening will not be available.

Comments

There has been no attempt in this discussion to “engineer” a drive system because it
would be necessary to calculate all resistor values and wattages to match the
requirements of all the control fields. We would need to know the resistance of all
machine fields, their current and voltage ratings and the amplification ratios of the
exciters. Some additional resistors might be required to provide proper scaling of the
feed-back signals.

Figure 20-2 is a generic “demonstration” circuit to show how the logic might be
applied. A system, using this circuit, would be susceptible to considerable “drift”
attributable to temperature changes.

In a modern system, most of the feed-back signals would be scaled and passed directly
through A/D converters, processed digitally, then returned as reference signals through a
D/A converter. The digital numbers could be manipulated mathematically so that none
of the bias resis-tors would be required. The motor and generator field exciters could be
replaced with silicone controlled rectifier (SCR) power supplies, and controlled directly
from the digital logic.

If the generator is replaced by a “power SCR” module, it would be controlled directly,

eliminating the generator field exciter. When using digital control on all solid-state
components, very few analog devices will be required so very precise control of the DC
motor can be accomplished. The essential requirements for controlling the motor can be
provided by either analog or digital logic — or a combination of both. The arrival of
solid-state components has provided a means of doing it most efficiently.

CHAPTER 21

Unusual Trouble-shooting Case Histories

Since our stated purpose in this book is to help electricians and technicians become
better trouble-shooters, it is appropriate to include some interesting real-life experiences
that illustrate a few challenges we have experienced. Often the apparent problem could
be quickly identified, but the real fault was hard to “pin down.”

Relay Systems

Many elevator and marine control panels have been constructed in the past as live-front
boards. This construction uses an asbestos-composition or “Glasstex” insulating board
for its principal structure. Contractors and relays are assembled directly on this board
which might be 3/4'' to 1-1/4'' thick. Most wiring is installed on the back of board and
connected to brass or copper bolts that secure various parts of the respective
components. Stationary contacts are bolted directly to the board. Movable contacts will

43
have a flexible, braided shunt fastened to a through-bolt. Power and control voltages are
usually DC.

With a good schematic, the circuitry is usually fairly easy to follow. Wire numbers and
component identifications are frequently stamped on the front and back of the board.
Since the panel is usually not enclosed, it is subject to any contamination that might be
in the area, such as salt air, diesel fumes, oil-mist, carbon dust from brushes, etc. Board
Cracks

With aging, some boards tend to “craze” or form hair-line cracks between mounting
bolts. This fault may collect conductive contaminates over time. The resistance of the
contaminates may be high enough that you might not detect it with an ohmmeter, but
when voltage is applied, there is enough leakage current to cause a fault. Correction of
this problem depends upon whether or not the crack can be routered-out enough to clear
the conducting material and replace it with an insulating compound. It may be necessary
to bore a hole in another area and move the wiring away from the defect. Components
must be isolated and tested with a “megger” (high-voltage resistance tester) to prove
adequate insulation. Ohmmeters usually operate on relatively low-voltage (1.5–9 vdc)
while a megger uses about 500 vdc.

Shunts

The flexible shunt strands will crack from fatigue over time. If they are carrying much
current, they will develop hot spots, and may even char the board. In time they will
break. Since the shape has become conformed to the terminal locations, it may not be
visually apparent that it is broken.

44