Birla Institute of Technology & Science, Pilani

Work Integrated Learning Programmes Division

M.S. Software Engineering at Wipro Technologies (WASE)

Third Semester 2012 - 2013 (September to February 2014)

Comprehensive Exam (Makeup)

Course Number : SEWP ZC413

Course Title : Computer Organization & Architecture

Type of Exam : Open Book

No. of Pages : 5
Weightage : 60%
No. of Questions : 14
Duration : 3 hours

Date of Exam : 07/03/2014 SessionNo.

: of Questions
FN : 24

Note:

1. Please read and follow all the instructions given on the cover page of the answer script.
2. Start each answer from a fresh page. All parts of a question should be answered consecutively.
3. Appropriate assumptions can be made and explicitly mentioned .

Section A

1. A DMA module is transferring characters to memory using cycle stealing from a device transmitting
at 19200bps. The processor is fetching instructions at the rate of 2 MIPS. By how much will the
processor be slowed down due to the DMA activity. 3 Marks

2. A bench mark program is run on an 1 Ghz processor. The machine code consists of 200,000
instructions with the following instruction mix and CPI.

Instruction Type Instruction Count CPI

Arithmetic 50000 2
Register Transfer 80000 1
 Control 30000 2
Load Store Memory 40000 3

Determine the Effective CPI, MIPS rate and execution time of the program. 4 Marks

3. An address field in an instruction contains value 12h. find the corresponding operand located
for
a. Immediate addressing.
b. Direct addressing.
c. Indirect addressing.
d. Register indirect addressing. 4 Marks

Section B

4. A microprocessor scans the status of the output I/O device every 10ms. This is accomplished
by means of a timer alerting the processor every 10ms. The interface of the device includes
two ports : one for status and one for data output. How long does it take to scan and service
the device given a clock rate of 16 MHz. Assume for simplicity all the relevant instructions takes
12 clock cycles. 4 Marks

5. Consider a program snippet

i=0;
Do {
F[i]= x[i] + y[i]- z[i] ;
i=i+1;
} while (i<=1023);

is executed in memory with a page size of 1 K words. Using a processor that employs index
addressing mode to access memory operands write an generic ALP to implement the snippet
and show the sequence of page references and also total pages accessed during the execution
of the program. 4 Marks

6. Consider a general purpose Processor in which it was observed that the Dram memory fall short of
providing read data by X ns.
a. How many wait states in clock cycles needs to be inserted for proper system operation if the bus
clocking rate is F Mhz.
b. To enforce the wait states ,a Ready status line is employed. After the read command is issued by
the processor it must wait until the ready line is asserted before attempting to read data.
At what time interval must we keep the ready line low in order to force the processor to insert
 the required number of wait states if clk= 8Mhz and read latency is 180ns. 4 Marks

7. The following numbers use the IEEE 32 bit floating point format. What is the equivalent decimal
value.
a. 1 10000011 11000000000000000000000
b. 0 01111110 10100000000000000000000 4 Marks

Section C

8. Perform Binary division for the following operands.

Dividend : -27, Divisor 13 ( shown are the decimal equivalents of the numbers).
Explain clearly the partial result of each iteration . 5 Marks

9. A computer uses a small direct-mapped cache between the main memory and the
processor. The cache has four 16-bit words, and each word has an associated 13-bit tag.
When a miss occurs during a read operation, the requested
word is read from the main memory and sent to the processor. At the same time, it is
copied into the cache, and its block number is stored in the associated tag. Consider the
following loop in a program where all instructions and operands are 16bits long

TAG DATA

Cache Memory

054E A03C
05D9
10D7

Main Memory

Program Snippet

Loop: Add [R1]+, R0

Dec R2
Jnz Loop
 Assume that, before this loop is entered, registers RO, Rl, andR2 contain 0, 054E,
and 3, respectively. Also assume that the main memory contains the data shown in
previous figure where all entries are given in hexadecimal notation. The loop starts at
location Loop =02EC.
(a) Show the contents of the cache at the end of each pass through the loop.
(b) Assume that the access time of the main memory is 10τ and that of the cache is 1τ.
Calculate the execution time for each pass. Ignore the time taken by the processor
between memory cycles. 6 Marks

10. An important advantage of interrupts over polling is the ability of the processor to perform
other tasks while waiting for communication from an I/O device. Suppose that a 1GHz
processor needs to read 1000 bytes of data from a particular I/O device. The I/O device
supplies 1 byte every 0.02ms.The code to process the data and store it in a buffer takes
1000cycles.

a. If the processor detects that a byte of data is ready through polling and a polling iteration
takes 60 cycles, how many cycles does the entire operation take?
b. If instead, the processor is interrupted when a byte is ready and the processor spends the
time between interrupts on another task, how many cycles of this other task can the
processor complete while the I/O communication is taking place? The overhead for handling
an interrupt is 200 cycles. 4 Marks

11. A pipelined processor uses the delayed branch technique. You are asked to recommend
one of two possibilities for the design of this processor. In the first possibility, the
processor has a 4-stage pipeline and one delay slot, and in the second possibility, it
has a 6-stage pipeline with two delay slots. Compare the performance of these two
alternatives, taking only the branch penalty into account. Assume that 20 percent of the
instructions are branch instructions and that an optimizing compiler has an 80 percent
success rate in filling the single delay slot. For the second alternative, the compiler is able to
fill the second slot 25 percent of the time. 5 Marks

12. The average seek time and rotational delay in a disk system are 6 ms and 3 ms, respectively.
The rate of data transfer to or from the disk is 30Mbytes/sec and all disk
accesses are for8 Kbytes of data. Disk DMA controllers, the processor, and the main
memory are all attached to a single bus. The bus data width is 32bits, and a bus transfer
to or from the main memory takes 10nanoseconds.
 a. What is the maximum number of disk units that can be simultaneously transferring
data to or from the main memory?

b. What percentage of main memory cycles are stolen by a disk unit, on average, over
a long period of time during which a sequence of independent 8K-byte transfers
takes place? 4 Marks

13. Consider a 16-bit, floating- point number with a 6-bit exponent and a 9-bit normalized fractional
mantissa. The exponent is represented in excess 31 format.

a. Add the number A and B represented as follows, and represent the result in normalized form.
A 0 100011 010010100
B 1 011100 110100111

b. Determine the largest and smallest floating point number which can be represented in this
format. 4 Marks

14. Write a program to evaluate the following statement 5 Marks

X= (A - B + C * (D*E – F))/ (G+ H*K).

Using

1. Using a processor which support three operand address instructions.

2. Using a processor which support two operand address instructions.
3. Using a zero address stack organized processor.