Chapter 1

Module 1 Operational Amplifier

Fundamentals:

• Basic Op-amp circuit

• Op-Amp parameters

– Input and output voltage

– CMRR and PSRR
– offset voltages and currents
– Input and output impedances
– Slew rate
– Frequency limitations

• OP-Amps as DC Amplifiers

– Biasing OP-amps
– Direct coupled voltage followers
– Non-inverting amplifiers
– inverting amplifiers
– Summing amplifiers
– Difference amplifiers

• Interpretation of OP-amp LM741 & TL081 data sheet

(Text1) (L1, L2,L3)

1
1.1. BASIC OP-AMP CIRCUIT Chapter 1. Module 1 Operational Amplifier Fundamentals:

1.1 Basic Op-amp Circuit

The basic circuit of an operational amplifier is as shown in Figure 1.1. It has a differential amplifier input
stage and an emitter follower output. The supply voltages +Vcc and -Vcc are provided. Transistors Q1
and Q2 with resistors RE and RC constitute a differential amplifier, which produces a voltage change
at the collector of Q2. Transistor Q3 acts as a emitter follower. The Q2 collector voltage is applied to
the base of the transistor Q3.
Applying KVL to the base emitter for Q2

−VBE − VRE + VEE = 0

−VBE − (IE1 + IE2 )RE + VEE = 0

VEE − VBE
IE1 + IE2 =
RE
IE1 = IE2 = IE Then
VEE − VBE
IE =
2RE
Applying KVL for the loop VCC , RC , VBE3 and Vo

VCC − IC RC − VBE3 − Vo = 0

Vo = VCC − IC RC − VBE3

+ Vcc
7
+
VRC RC
-
IC2 Q3

3 2 Output
NonInverting Q1 Q2
Inverting 6
Input + +
Input
VBE IE1 IE2 VBE
VO=VCC-VRC-VBE3
- IE1+IE2 -
+
VRE RE
- 4
- VEE

Figure 1.1: Basic Op-amp Circuit

To demonstrate the circuit operation, Assume that VCC = 10V, VEE = −10V, RE = 4.7kΩ, RC =
6.8kΩ, andVBE = 0.7V
VEE − VBE 10 − 0.7
IE = = ' 1mA
2RE 2 × 4.7kΩ
IE2 = IC2 = IE = 1mA Then
Vo = VCC − IC RC − VBE3

Vo = VCC − IC RC − VBE3
= 10 − 1 × 10−3 × 6.8103 − 0.7
' 2.5V

If a positive voltage is applied to the non-inverting input terminal, Q1 base is pulled up by the
input voltage and its emitter terminal tends to follow the input signal. Since Q1 and Q2 emitters are

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1.2. OP-AMP PARAMETERS Chapter 1. Module 1 Operational Amplifier Fundamentals:

connected together, the emitter of Q2 is also pulled up by the positive going signal at the non-inverting
input terminal.
The base voltage of Q2 is fixed at ground level, so the positive going movement at its emitter causes
a reduction in its base-emitter voltage (VBE2). The result of the reduction in VBE2 is that its emitter
current is reduced and consequently its collector current is reduced
Assume that Positive going input at the base of Q1 reduces Ic2 by 0.2 mA (from 1mA to 0.8mA)
then

Vo = 10 − 0.8 × 10−3 × 6.8103 − 0.7 = 3.9V

This voltage is changed from +2.5 V to 3.9 V which is 1.4 V higher in this case.

1.2 OP-AMP Parameters

1.2.1 Input Voltage Range Configuration”. When both input terminals
are at the same potential, so ideally the output
Op-amp has a cascade of differential amplifiers.
should be zero (VO = V1 − V2 ). Because the base
When the input voltage is increased beyond
voltages of Q1 and Q2 are biased to 1 V above
the limit, it may cause the transistor to reach
ground, the voltage drop across emitter resistor RE
saturation stage. Or when the input voltage
is increased by 1 V and consequently, IC1 and IC2
is decreased beyond the limit it may cause the
are increased. The increased level of IC2 produces
transistor in cutoff region.
an increased voltage drop across RC which results
Input voltage range is defined as the in a change in the output voltage at the emitter of
maximum positive going and negative going Q3.
input voltage that may be applied to an op-
amp for proper functioning of an op-amp. + Vcc
7
For the 741 op-amp with a supply of ±15 V,
+
the data sheet lists the input voltage range of ±13 VRC RC
V. - Ra
IC1
NonInverting IC2 Q3
Input
3 2 Output
1.2.2 Output Voltage Range Q1 Q2
Inverting 6
+ + +
Input
The maximum voltage swing is limited by the input 1 V VBE IE1 IE2 VBE
VO
- - I +I -
voltage range. The output voltage can swing in + E1 E2
VRE Rb
a positive or negative direction depends on the RE
- 4
supply voltage and the op-amp output circuitry. A
- VEE
rough approximation for most op-amps is that the
maximum output voltage swing is approximately Figure 1.2: Common Mode Configuration
equal to 1 V less than the supply voltage.
For the 741 op-amp with a supply of 15 V, the The common mode gain is the ratio of
data sheet lists the output voltage swings in the output voltage to the common mode input
range of 14 V. voltage applied to the input terminals.

V0(cm)
1.2.3 Common Mode Rejection Acm =
Vi(cm)
When the same voltage is applied to
inverting and non inverting terminals of The success of the op-amp rejecting common
op-amp, the voltage is called ”Common mode inputs is defined in the common mode
Mode Voltage Vin”, and the op-amp is rejection ratio (CMRR). CMRR is the ratio of
said to be operating in the ”Common Mode the open loop gain M to the common mode

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1.2. OP-AMP PARAMETERS Chapter 1. Module 1 Operational Amplifier Fundamentals:

gain Acm. Which is given by. This unwanted output is known as Output
Offset Voltage. To get zero voltage at the
M output then the input should be raised to + 0.1V.
CM RR =
Acm This voltage is known as Input Offset Voltage.
Usually transistors in integrated circuits are very
In terms of decibel,
well matched and there is always some input offset

M
 voltage. The typical offset voltage 741 is 1 mV.
CM RRdB = 20log dB
Acm
Input Offset Current
1.2.4 Power Supply Voltage Rejec- If the input transistors of an op-amp not being
tion perfectly matched, as well as the transistor base-
emitter voltages being unequal, the current gain
If there is any variation in −VEE , then it will hf e of one transistor may not be exactly equal to
changes in the voltage drop across RE . This will that of the other. When both transistors have
change the currents IE1 , IE2 , IC2 . The change in equal levels of collector current, the base current
IC2 will change VRC and this will change the dc may not be equal. The difference in these two
output voltage. The variations in VCC or/and VEE input currents is known as Input Offset Current
will produce some changes at the output. (IOS).
The Power Supply Rejection Ratio The Input Offset Current for 741 op-amps is 20
(PSRR) is a measure of how effective the nA.
op-amp is in dealing with variations in
supply voltage. Offset Nulling
For example if a variation of 1V in VCC or VEE
causes the output to change by 1V, then the supply To correct the input offset voltage and current
voltage rejection ratio is 1V/V. is as shown in Figure. A 10 k potentiometer is
Similarly if output changes by 10mV when connected to offset nulling terminals 1 and 5 and its
one of the supply voltages changes by 1V, then moving contact is connected to the negative supply
Supply voltage Rejection Ratio is 10mV/V. For line. The details of the circuit for offset nulling is
741 operational amplifier it is 30 µV /V . as shown in Figure 1.3
+ Vcc
7
3
1.2.5 Offset Voltage and Currents + 6
μA741
Input Offset Voltage 2 _1 5 Vout
10 kΩ
For a voltage follower circuit, the output of 4
OPAMP is fed back to the inverting terminal and
the input voltage is given non-inverting terminal.
- VEE
For the output voltage to be exactly equal to
the input voltage, transistors Q1 and Q2 must be Figure 1.3: Offset nulling
perfectly matched.
The output voltage for the voltage follower
circuit is, 1.2.6 Input and Output Impedance
VO = Vi − VBE1 + VBE2 Input Impedance
The input impedance offered by any op-amp is
With VBE1 = VBE2 and Vi = 0 , then substantially modified by its application. From
negative feedback theory, the impedance at the op-
VO = Vi = 0 amp input terminal is
If the transistors are not perfectly matched and
Zin = (1 + M β)Zi
that VBE1 = 0.7 V and VBE1 = 0.6 V with Vi = 0,
where Zi = the op-amp input impedance without
VO = 0 − 0.7 + 0.6 = −0.1 negative feedback. M = op-amp open loop gain, β

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1.2. OP-AMP PARAMETERS Chapter 1. Module 1 Operational Amplifier Fundamentals:

= Feed back factor 1 for voltage follower Vin 3 + Vcc

+ 7 Vout
Typical value of input impedance of an opamp 6
μA741
is 1M Ω 2 _ 4
- Vcc

Output Impedance

The output impedance offered by any op-amp is

Figure 1.5: Slew Rate

ZO ∆V ∆VO
Zout = t= =
1 + Mβ ∆t S
The typical slew rate of the 741 op-amp is 0.5 V
where ZO = the op-amp output impedance without per microsecond. This means that 1 microsecond
negative feedback. M = op-amp open loop gain, β is required for output to change by 0.5 V
= feed back factor.
The typical output resistance specified for the Frequency limitations
741 op-amp is 75Ω.
The plot of frequency (f) versus gain (A) of an
741 op-amp is as shown in Figure 1.6.The open
R1 + V CC loop gain (A) falls by 20 dB when the frequency
3
Zi increases from 100 Hz to 1 KHz. The ten times
Zo 6
'
Zin Z in increase in frequency is termed a decade. So, the
2 Zout rate of the gain is said to be 20 dB per decade.
IB Where internal gain equals to or greater than 80
R2
- VEE dB is required for a particular application, it is
Zo
Z out = available with a 741 only for signal frequencies up
1 + M / Av
I2 to 100 Hz. A greater than 20 dB is possible for
Zin = (1 + M / Av )Zi signal frequencies up to 90 kHz. Other op-amp
R3
maintains much higher frequencies than the 741.

Figure 1.4: Input and Output Impedance

Slew Rate

The slew rate (S) of an op-amp is the maximum

rate at which the output voltage can change. When
the slew rate is too slow for the input, distortion
results. This is illustrated as shown in the Figure,
which shows a sine wave input to a voltage follower
producing a triangular output waveform. The
triangular wave results because the op-amp output
cannot fast enough to follow the sine wave input. Figure 1.6: Frequency response

——————————————————–

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1.3. OP-AMPS AS DC AMPLIFIERS Chapter 1. Module 1 Operational Amplifier Fundamentals:

1.3 OP-Amps as DC Amplifiers

1.3.1 Biasing Operational Ampli- Virtual Ground

fier Ideal differential amplifier amplifies the difference
of the two input voltages. Consider two input
Bias Current Paths voltages V1 and V2 and its output voltage is VO
with open loop gain of Aol .
Operational amplifier must be properly biased to
function properly. The inputs of op-amps are the VO ∝ (V1 − V2 )
base terminals of the transistors in a differential VO = Aol (V1 − V2 )
amplifier. Base currents must flow into these VO = Aol × Ad
terminals for the transistors to be operational.
If the open loop gain is very high i.e., ∞ then
One of the two input terminals is usually
connected to the op-amp output to provide VO = Aol (V1 − V2 )
negative feedback. The other input is biased VO VO
directly to ground via a signal source. The current (V1 − V2 ) = = =0
Aol ∞
IB1 flows into the op-amp via the signal source
Then
while IB2 flows from the output terminal which is
V1 = V2
as shown in Figure 1.7.

I B1 + VCC V1 +
3 Ideal
+ 7 6 Differential
VS
2 _μA741 4
+
V2 _Amplifier
Vo
Vout
I B2 _
- VEE

Figure 1.7: Directly coupled voltage follower Figure 1.9: Voltage follower with resistor
Biasing method using resistor is as shown in
Figure 1.9 in which resistor R1 is added in series Direct Coupled Voltage Followers
with inverting terminal to match signal source As shown in the figure 1.9 the resistor R1 is
resistance RS in series with the non-inverting included in series with the inverting terminal to
terminal. Op-amp input currents produce voltage match the source resistance RS in series with the
drops IB1 × RS and IB2 × R1 across the resistors. non-inverting terminal. The input and output
RS and R1 should be selected as equal resistors so impedances of the voltage follower are
that the resistor voltage drops are approximately
equal. Any difference in these voltage drops will Zin = (1 + M )Zi
have the same effect as an input offset voltage. Zo
Zout =
(1 + M )
I B1 + VCC
3 The voltage follower has very high input impedance
-
+ 76 and very low output impedance. Therefore, it is
VRs R 2 _μA741 4
+ normally used to convert a high impedance source
to low output impedance. It is used as a buffer
s Vout
+ I B2 _ between the high impedance source and the low
- VEE
impedance amplifier. It is also termed as a buffer
Vs R1 amplifier .
When the voltage follower is connected to the
+ -
load the circuit diagram is as shown in Figure
VR1
1.10. From the figure it appears that a signal
voltage is potentially divided across Rs and RL
Figure 1.8: Voltage follower with resistor
when connected directly to a load. But when the

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1.3. OP-AMPS AS DC AMPLIFIERS Chapter 1. Module 1 Operational Amplifier Fundamentals:

load and source are joined by the voltage follower, impedance and higher output impedance with the
it presents its very high impedance to the signal emitter follower.
source. Because Zin is normally very much larger + Vcc I B1 + VCC
3
than Rs , there is virtually no loss for signal and + 7 6
effectively all the input appears at the op-amp Q Zin _μA741
+ 3 Vi 2
Vi 4
input. VBE - I VO =Vi
B2
- VEE
I B1 + VCC RL VL =Vi − VBE R1
3
7 6 Vs
+
+ -
vZ Zin _μA741 VR1
Vi = s in 2 4 Voltage follower
Rs + Z in Emitter follower
I B2 VO =Vi
- VEE Figure 1.11
Vs R1

+ - Direct coupled non-inverting amplifiers

VR1
The circuit diagram of direct coupled inverting
Rs RL vs RL amplifier is as shown in Figure 1.12
Vo = In this circuit it is design such that the potential
Rs + RL
divider current (I2 ) is very much larger than the
Vs
maximum input bias current IB(max) . The drop
across R1 is negligible.
From the concept of virtual ground Vi = Vin =
Figure 1.10 VA . The current I from the output VO is
The voltage follower output is IB + VCC
R1 3
Vi -
+ 7 6
Vd = + μA741
M VRs Vin 2 _ I
Vi 4 VO
Vi + - IB
VO = Vi − Vd = Vi − - VEE R2
M
  Vs VA
1 I2
VO = Vi 1 −
M
R3
The output voltage can be thought of as being
divided across RL and the voltage follower output
impedance Zout . But Zout is much smaller than any
load resistance that might be connected. So, there
Figure 1.12: Non-Inverting amplifier
is effectively no signal loss and all Vi appears as Vo
at the circuit output. VO − VA
I=
R2
Voltage Follower compared to an Emitter Vin = VA
Follower VO − Vin
I=
R2
Both voltage follower and the emitter follower
are buffer amplifiers. The voltage follower has At the inverting terminal I2 is very much larger
a much higher input impedance and much lower than IB(max) then (I2 ) = I
output impedance than the emitter follower. The Vin − 0
disadvantage of the emitter follower is the dc I=
R3
voltage loss due to the transistor base-emitter
voltage drop. But the voltage follower dc loss of VO − Vin Vin
=
Vi/A is insignificant. There can also be a greater R2 R3
loss of ac signal voltage in the emitter follower than VO Vin Vin
in the voltage follower because of the lower input = +
R2 R3 R2

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1.3. OP-AMPS AS DC AMPLIFIERS Chapter 1. Module 1 Operational Amplifier Fundamentals:

 
VO R3 + R2 R2 + R3 VA = 0
= R2 =
Vin R2 R3 R3 Vin VO
+ =0
The voltage gain of a non-inverting amplifier, R1 R2
R2 + R3
Av = VO R2
R3 =−
Vin R1
Performance The voltage gain of a non-inverting amplifier,
The input impedance of the op-amp circuit is as
shown in Figure R2
Av = −
R1
R1 + VCC
3
Zi
Zo 6 R2
Z ' Zin
in 2 Virtual
Zout ground + -
IB I1 Vo
R2 + VCC
- VEE R1
Z out =
Zo 3 _ 7
6
1 + M / Av + + - VA
I2 Rs 2
Zin = (1 + M / Av )Zi Vin + 4 Vo
R3 - IB
- VEE
R3
Vs

Figure 1.13
Figure 1.14: Inverting amplifiers
Zin = (1 + M β)Zi Resistor R3 is connected at the non-inverting
terminal to equalize the dc voltage drops due to
where β is the feedback factor for noninverting
the input bias currents. Usually equal resistance
amplifier which is given by
should be used for the input terminals of the op-
R3 1 amp.
β= =
R2 + R3 Av R3 = R1 kR2
Therefore   If R1 is smaller than the source resistance RS , then
M
Zin = 1+ Zi
Av
R3 ' (RS + R1 )kR2
The impedance seen is, from the signal source
0
Zin = R1 + Zin As with other bipolar op-amp circuits, the resistor
current (I1 ) is first selected very much larger than
Since Zin is always much larger than R1 in a non- the maximum input bias current (I(Bmax) .
inverting amplifier, the inclusion of R1 normally
makes insignificant. Vi
The output impedance of the op-amp circuit R 1 =
I1
Zo M Zo M
Zout = == and
1 + Mβ 1 + M/Av
VO
R2 =
I1
Direct coupled inverting amplifiers
The circuit diagram of direct coupled inverting
amplifier is as shown in Figure 1.14 Performance

VA − Vin VA − VO The input impedance of the op-amp circuit is as

+ =0 shown in Figure 1.15
R1 R2

Dr. Manjunatha P Professor Dept of ECE, JNN College of Engineering, Shivamogga 8

1.3. OP-AMPS AS DC AMPLIFIERS Chapter 1. Module 1 Operational Amplifier Fundamentals:

R2 If R1 = R2
R3
Vo = − (V1 + V2 )
R1
R1 + VCC = Av (V1 + V2 )
-
Zo 6 Also when R1 = R2 = R3
Zo
Zin = R1 Zout = Vo = −(V1 + V2 )
+ 1 + M / Av
Virtual
ground R3 - VEE I f = I1 + I 2 R
3
V2 R2

I2 Vo

Figure 1.15 V1 R1 + Vcc

2 -
The input impedance Zin is 76
I1
3 Vo
4
Zin = R1 +
- VEE
R4
The output impedance of the op-amp circuit

Zo
Zout = Figure 1.16: Inverting Summing Amplifier
1 + Mβ
The circuit diagram of a three inputs summer is as
where β is the feedback factor for inverting shown in Figure. The currents I1 I2 , and I3 are
amplifier which is given by
V1 V2 V3
I1 = , I2 = and I3 =
R1 1 R1 R2 R3
β= =
R1 + R2 Av 
V1 V2 V3

Vo = −(I1 + I2 + I3 )R4 = − + + R4
Zo R1 R2 R3
Zout = If R1 = R2 = R3 then
[1 + M R1 /(R1 + R2 )
when R2  R1 R4
Vo = − (V1 + V2 + V3 )
R1
Zo R1
Zout = R4 =
(1 + M/Av ) 3
1
Vo = − (V1 + V2 + V3 )
3
1.3.2 Summing Amplifiers The output is the average of three inputs,
Inverting Summing Circuit hence the summing amplifier acts as a averaging
circuit.
The circuit diagram of an inverting summing I 4 = I1 + I 2 + I 3
circuit is as shown in Figure 1.16. In this circuit R3
amplifies the sum of two or more inputs and R4
V3 I3
inputs are applied to the inverting input terminal, Vo
hence the amplifier is called Inverting Summing R2
Amplifier . The inverting input terminal of the V2
I2
op-amp behaves as a virtual ground.
The currents I1 and I2 are expressed as R1 + Vcc
2 -
V1 76
V1 V2 I1 3
I1 = and I2 = + 4 Vo
R1 R2 - VEE
R3
These two currents are flowing in a resistor R3
 
V1 V2
Vo = −(I1 + I2 )R3 = − + R3 Figure 1.17: Averaging circuit
R1 R2

Dr. Manjunatha P Professor Dept of ECE, JNN College of Engineering, Shivamogga 9

1.3. OP-AMPS AS DC AMPLIFIERS Chapter 1. Module 1 Operational Amplifier Fundamentals:

Noninverting Summing Circuit R3

A noninverting summing circuit is as shown in V3 +

Figure 1.18. This circuit gives the sum of of the - R2 + Vcc
3
inputs instead of inverted sum.To determine the +
V2 + 76
input voltage given to the circuit is determined 2
- 4 Vo
using superposition theorem. -
R1 - VEE R4
With V2 = 0 and R1 = R2 = R
V1 + +
V1 R V1 - Vi
Vi1 = = +
R+R 2 - Vi R5
With V1 = 0 -
V2
Vi2 = Figure 1.19: 3 Input Noninverting Summing
2
Circuit
V1 V2 V1 + V2
Vi = + =
2 2 2 Difference Amplifier
A differential amplifier amplifies the difference
R2
between two input signals. It has a two inputs, one
V2 at inverting terminal and the other at noninverting
terminal. The circuit diagram of a differential
R1 + Vcc amplifier is as shown in Figure 1.20.
Vout
V1 + 76 R2
Vi
- 4
- VEE
R3
R1 + Vcc
2 - 76
Vi R4 V1 R3
3
4 Vo
+ +
V2 - VEE
Figure 1.18: Noninverting Summing Circuit VR4
R4
-
R3 + R4
Av =
R4 Figure 1.20
The differential amplifier is a combination of
R3 + R4 v1 + v2 inverting and non-inverting amplifier.
vo = Av × Vi = ×
R4 2 When V2 = 0, it is an inverting amplifier and
with R3 = R4 its output is

vo = v1 + v2 R2
VO1 = − × V1
R1
The three input noninverting summing circuit is When V = 0, it is an noninverting amplifier.
1
as shown in Figure 1.19. When all the three input
resistors are equal the input at the noninverting R4
VR4 = × V2
terminal is R3 + R4
V1 + V2 + V3 Inverting amplifier and its output is
Vi =
3
R1 + R2
R4 +R5 VO2 = × VR4
The gain Av = R5 = 3 then R1
R1 + R2 R4
Vo = V1 + V2 + V3 VO2 = × × V2
R1 R3 + R4

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1.3. OP-AMPS AS DC AMPLIFIERS Chapter 1. Module 1 Operational Amplifier Fundamentals:

When R3 = R1 and R4 = R2 R2
VO = (V2 − V1 )
R1
R2
VO2 = × V2
R1 When R2 = R1 the output is the direct difference of
When both signals present the two inputs. When R2 > R1 the output can be
R2 R2 made an amplified version of the input difference.
VO = VO1 + VO2 = × V2 − × V1 ———————————————————–
R1 R1

Dr. Manjunatha P Professor Dept of ECE, JNN College of Engineering, Shivamogga 11

1.3. OP-AMPS AS DC AMPLIFIERS Chapter 1. Module 1 Operational Amplifier Fundamentals:

Q1. Using a 741 op-amp design non-inverting R1 = R2 kR3 = 1 M Ωk15 kΩ

amplifier to have a voltage gain of approximately 1 M Ω + 15 kΩ
66. The signal amplitude is to be 15 mV. = ' 15 kΩ
1 M Ω × 15 kΩ
Solution: Q3. A noninverting amplifier is to amplify a 100
mV signal to a level of 3V. Using a 741 op-amp
From the data sheet for 741 IB(max) = 500nA
design a suitable circuit.
Choose I2 = 100 × IB(max) = 50µA
Solution:
VO = Av × Vi = 66 × 15mV = 990mV
From the data sheet for 741 IB(max) = 500nA
R1 + VCC Choose I2 = 100 × IB(max) = 50µA
3 7
+ 6
μA741
Vin 2 _ Vi = I2 × R3
Vi 4
- VEE R2 Vi 100mV
R3 = = = 2 kΩ
I2 50µA
I2 VO
VO = I2 × (R2 + R3 )
R3
3V
R2 + R3 = = 60 kΩ
50µA

Figure 1.21
R2 = (R2 + R3 ) − R3
= 60 kΩ − 2 kΩ = 58 kΩ
Vi = I2 × R3
Vi 15mV
R3 = = = 300 Ω
I2 50µA R1 = R2 kR3 = 58 kΩk2 kΩ
VO = I2 × (R2 + R3 ) 58 kΩ + 2 kΩ
= ' 1.93 kΩ ' 2.2kΩ
58 kΩ × 2 kΩ
990mV
R2 + R3 = = 19.8 kΩ
50µA + VCC
R1 3 7
+ 6
R2 = (R2 + R3 ) − R3 μA741
Vin 2 _
= 19.8 kΩ − 300 Ω = 19.5 kΩ Vi 4
- VEE R2

R1 = R2 kR3 = 19.8 kΩk300 Ω I2 VO

19.8 kΩ + 300 Ω R3
= = 295 Ω
19.8 kΩ × 300 Ω
Q2. Using a LF-353 op-amp design non-inverting
amplifier to have a voltage gain of approximately Figure 1.22
66. The signal amplitude is to be 15 mV.
Q4. Design a direct coupled noninverting amplifier
Solution: to amplify a 100 mV signal using a 741 op-amp to
a level of 4V.
From the data sheet for 741 IB(max) = 200pA
Using this current requires very large resistor Solution:
values select R2 = 1 M Ω
From the data sheet for 741 IB(max) = 500nA
R2 + R3 R2 Choose I2 = 100 × IB(max) = 50µA
Av = =1+
R3 R3
Vi = I2 × R3
R2
= Av − 1 Vi 100mV
R3 R3 = = = 2 kΩ
I2 50µA
R2 1 MΩ
R3 = = ' 15 kΩ VO = I2 × (R2 + R3 )
Av − 1 66 − 1

Dr. Manjunatha P Professor Dept of ECE, JNN College of Engineering, Shivamogga 12

1.3. OP-AMPS AS DC AMPLIFIERS Chapter 1. Module 1 Operational Amplifier Fundamentals:

4V Q6. Design an inverting amplifier using a LF-3531

R2 + R3 = = 80 kΩ
50µA op-amp. The voltage gain is to be 50 and the
output voltage amplitude is to be 2.5 V.
R2 = (R2 + R3 ) − R3
Solution:
= 80 kΩ − 2 kΩ = 78 kΩ
Select the largest feedback resistor R2 = 1 M Ω
R1 = R2 kR3 = 78 kΩk2 kΩ The gain Av of an inverting amplifier is
78 kΩ + 2 kΩ R2
= ' 1.93 kΩ ' 1.95kΩ Av =
78 kΩ × 2 kΩ R1

R1 + VCC R2 1 MΩ
3 7 R1 = = = 20 kΩ
+ 6 Av 50
μA741
Vin 2 _
Vi 4
- VEE R2 R3 = R1 kR2 = 20 kΩk1 M Ω
20 kΩ + 1 M Ω
I2 VO = = 19.6 kΩ
20 kΩ × 1 M Ω
R3
Q7. Design an inverting amplifier using a 741 op-
amp with a voltage gain of 66 and the output
voltage required is 3 V.
Figure 1.23
Q5. Design an inverting amplifier using a 741 op- Solution:
amp. The voltage gain is to be 50 and the output From the data sheet for 741 IB(max) = 500nA
voltage amplitude is to be 2.5 V. Choose I2 = 100 × IB(max) = 50µA
Solution: VO 3
Vi = = = 45.45mV
From the data sheet for 741 IB(max) = 500nA Av 66
Choose I2 = 100 × IB(max) = 50µA Vi 45.45mV
R1 = = ' 1 kΩ
VO 2.5 I1 50µA
Vi = = = 50mV VO 3
Av 50 R2 = = = 60 kΩ
I1 50µA
I1 R2 47 kΩ

- + R3 = R1 kR2 = 1 kΩk60 kΩ
VO
I1 + VCC 1 kΩ + 60 kΩ
R1 1 kΩ - = ' 1 kΩ
1 kΩ × 60 kΩ
+ - 6
Vi V1
VO Q8. Design a bias current compensated inverting
+ amplifier to amplify a dc input of 150 mV by factor
R3 - VEE
of 40¿ Use a 741 op-amp with a voltage gain of 66
1 kΩ
and the output voltage required is 3 V.
Solution:
Figure 1.24
From the data sheet for 741 IB(max) = 500nA
Vi 50mV Choose I2 = 100 × IB(max) = 50µA
R1 == = 1 kΩ
I1 50µA VO 3
VO 2.5 Vi = = = 45.45mV
R2 = = = 50 kΩ Av 66
I1 50µA
Vi 45.45mV
R1 = = ' 1 kΩ
R3 = R1 kR2 = 1 kΩk50 kΩ I1 50µA
1 kΩ + 50 kΩ VO 3
= ' 1 kΩ R2 = = = 60 kΩ
1 kΩ × 50 kΩ I1 50µA

Dr. Manjunatha P Professor Dept of ECE, JNN College of Engineering, Shivamogga 13

1.3. OP-AMPS AS DC AMPLIFIERS Chapter 1. Module 1 Operational Amplifier Fundamentals:

R3 = R1 kR2 = 1 kΩk60 kΩ
1 kΩ + 60 kΩ
= ' 1 kΩ
1 kΩ × 60 kΩ
Q9. Design a summing amplifier as shown in
Figure 1.25to give the direct sum of two inputs
which each range from 0.1V to 1 V. Us1 a 741 op-
amp.
I f = I1 + I 2 R
3
V2 R2

I2 Vo

V1 R1 + Vcc
2 - 76
I1
3 Vo
4
+
- VEE
R4

Figure 1.25

Solution:
From the data sheet for 741 IB(max) = 500nA
Choose I2 = 100 × IB(max) = 50µA

Vi = I2 × R3
Vi(min) 0.1V
R1 = = = 2 kΩ
I1(min) 50µA
Use 1.8 kΩ R1 = R2 = 1.8 kΩ
For Av = 1 R3 = R1 = 1.8 kΩ

R4 = R1 kR2 kR3 = 1.8 kΩk1.8 kΩk1.8 kΩ

1 1 1
= + + =' 600Ω
1.8 kΩ 1.8 kΩ 1.8 kΩ

Dr. Manjunatha P Professor Dept of ECE, JNN College of Engineering, Shivamogga 14

1.3. OP-AMPS AS DC AMPLIFIERS Chapter 1. Module 1 Operational Amplifier Fundamentals:

JAN-2019-CBCS 1a)List the ideal characteristics iv) output voltage swing: The output voltage
of operational amplifier and mention the practical swing is the maximum peak to peak output
values of each. voltage that an OPAMP can produce at its
Solution: output. For 741 IC it is ±13V
Opamp has the following ideal characteristics
v) CMRR: is the ratio of the open loop gain
• Infinite input impedance 1 MΩ M to the common mode gain Acm. Which
is given by.
• Zero output impedance 75Ω.
M
• Zero common-mode gain CM RR =
Acm
• Infinite common-mode rejection
For 741 IC it is 90 dB
• Infinite bandwidth.
vi) PSRR. The Power Supply Rejection
• Infinite Voltage Gain Ratio (PSRR) is a measure of how effective
the op-amp is in dealing with variations in
supply voltage.
1b) Explain the operation of direct coupled non- ±13V
inverting summing amplifier and show that output b) Discuss the ideal voltage transfer curve of op-
voltage Vo = V1 + V2 amp and also draw the equivalent circuit of op-amp
and discuss its significance.
1c) Design an direct coupled inverting amplifier
using op-amp 741 with voltage gain 100 and output c) Sketch the direct coupled difference amplifier
voltage required is 5V circuit. Derive an equation for output voltage
Vo = RR2
2
(V2 − V1 )
2 a)Explain the following terms: i) input offset
voltage ii) slew rate iii) output voltage swing iv) 10EC46 JAN 2019
CMRR V) PSRR. Mention the typical values of
each terms for 741 op-amp. 1 a) Explain the operation of a basic op-amp circuit
Solution:
i) input offset voltage: For an ideal op-amp 1 b)Define the following op-amp parameters and
if both the inputs are at the same voltage with mention the typical values for 741 op-amp: i)
respect to ground then the output voltage should CMRR ii) slew rate
be zero. Due to manufacturing process if there is
a difference in a transistors characteristics, output 1 c) Using a 741 op-amp design a non inverting
may not be zero. To make the output to be zero amplifier to have a voltage gain of approximately
one of the input should be adjusted to get zero 66. The input signal amplitude is 15 mV
output. This voltage is called of the input offset
voltage. The typical offset voltage of 741 is 1 mV. 15EC46 JAN 2018

ii) slew rate: The slew rate (S) of an op-amp 1 a)Define the following terms with respect to op-
is the maximum rate at which the output amp and mention the typical values for 741 op-
voltage can change. amp: i)PSRR. ii)CMRR iii)slew rate iv) input
∆V voltage range and output voltage range.
Slewrate =
∆t
1 b) Compare the emitter follower with voltage
The typical slew rate of the 741 op-amp is 0.5 V follower.
per microsecond.
iii) Input Voltage Range: Input voltage 1 c) A voltage follower using a 741 op-amp is
range is the range of a common mode input connected to signal source with resistance Rs =
signal for which a differential amplifier 47kΩ. Calculate suitable value of resistance R1 and
remains linear. For 741 IC it is ±13V also maximum voltage drop across each resistor

Dr. Manjunatha P Professor Dept of ECE, JNN College of Engineering, Shivamogga 15

1.3. OP-AMPS AS DC AMPLIFIERS Chapter 1. Module 1 Operational Amplifier Fundamentals:

and maximum input offset voltage produced by 1 a) With a neat circuit diagram explain the
input offset current. working a basic circuit of operational amplifier

1 a) Derive output voltage equation of 3 input non 1 b) A direct coupled noninverting amplifier is to
inverting summing circuit and show how it can be amplify a 100 mV signal to a level of 3 V. Using
converted into averaging circuit. 741 desing suitable circuit. Assume IB(max) 500nA.
2b ) An operational amplifier circuit with closed
loop gain is 100 and common mode output voltage
is 5 mV and common mode input is 5 mV, 1 c) Write the circuit diagram of 3 input non
determine common mode rejection ratio. inverting summing circuit and prove that Vo =
V1 + V2 + V3
2 c) Explain the operation of a basic op-amp
circuit. 15EC46 July 2017
1 a) With a neat circuit diagram explain the basic
10EC46 JAN 2018 operational amplifier circuit.
1 a) Explain the basic circuit of operational
amplifier
1 b) Define CMRR of an operational amplifier. 741
1b) Draw a neat circuit diagram of a direct coupled op-amp is used in a non inverting amplifier with a
non-inverting op-amp and explain the design steps voltage gain of 50. Calculate the typical output
voltage that would result from a common mode
1 c) op-amp Design an inverting amplifier using a input with a peak level of 100 mV
741 op-amp for the voltage gain to be 50 and the
output voltage amplitude to be 2.5 volts. 1 c) Design an averaging circuit to give the average
of two inputs which range from 0.1 V to 1 V. Use
10EC46 July 2018 74 op-amp

Dr. Manjunatha P Professor Dept of ECE, JNN College of Engineering, Shivamogga 16