148 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO.

1, JANUARY 2005

Power Factor Correction Using a Series Active Filter

Zhiguo Pan, Student Member, IEEE, Fang Z. Peng, Fellow, IEEE, and Suilin Wang

Abstract—This paper presents a low-cost approach to power

factor correction (PFC) of single-phase diode rectifiers using a
series active filter. Comparing with the traditional PFC, the pro-
posed PFC has lower requirements of power device ratings, which
leads to lower cost, higher efficiency, and lower electromagnetic
interference. It also can eliminate the bulky inductor needed
in the traditional PFC. The topology, operation principle, and
application issues of the proposed PFC are analyzed in this paper.
Fig. 1. Traditional power factor correction.
The control strategy is discussed in detail and simulation results
are provided. A 1-kW prototype is built up and the experimental
results are presented to verify the analysis. simple and easy to implement, is presented to eliminate line har-
Index Terms—Adjustable-speed drive, heating, ventilating, and monics. Simulation and experimental results are given to verify
air conditioning (HVAC), power factor correction (PFC), series ac- the analysis and demonstrate the control performance.
tive filter.
II. TOPOLOGY AND OPERATION PRINCIPLE
I. INTRODUCTION The diode rectifier with proposed PFC for typical residen-
tial HVAC is shown in Fig. 2. Because the ac line is 100 V and
I N the recent years, more and more variable speed motor
drives fed by single-phase utility power are used in residen-
tial heating, ventilating, and air-conditioning (HVAC) systems.
low, a voltage doubler is used for rectification, i.e., two capaci-
tors are charged alternatively over one cycle. The output voltage
is doubled, resulting in an approximate 250 V dc link voltage
Most of them are using diode rectifiers with smoothing dc ca-
( V). The PFC circuit, implemented by a full bridge
pacitors as the front-end. The diode rectifier draws pulsed cur-
inverter with an optional inductor, connected in series with the
rent from the utility line, which leads to low power factor, low
diode rectifier. Since the diode rectifier and the full bridge in-
efficiency, and high rating requirements to the switching de-
verter behave like voltage sources, the line current is determined
vices. As a result, some standards such as IEC 1000-3-2 have
by the difference among these three voltage sources and the loop
been brought forward to limit the harmonic current of the utility
inductance, which includes the line impedances and
line. To comply with these standards, power factor correction
the inductance of the optional inductor .
(PFC) is needed. So far, a variety of passive and active PFC tech-
Although four switching devices are used in this topology,
niques have been proposed [1]–[5]. While the passive PFC may
each power device only needs to sustain a low capacitor voltage,
be the simplest way in the low power applications, the active
, which is limited below 50 V. Thus low-cost, high-effi-
PFC are used in the majority of applications for their high per-
ciency 60-V metal-oxide semiconductor field effect transistors
formance, compact size, and light weight.
(MOSFETs) can be employed. The voltage rating of each
Fig. 1 shows the most common approach to signal-phase ac-
device is only 20% of the voltage rating of the switching device
tive PFC, where a boost circuit with an additional filter inductor
that are used in the boost stage of the traditional PFC. There-
is used to shape the line current. The boost stage forces the dc
fore, even though four MOSFETs are used in the proposed
bus current to follow the line voltage, which results in a nearly
topology, its total cost of switching devices is still less than
sinusoidal line current without phase difference. However, it
the cost of the high voltage device in the traditional topology.
brings in high dc bus stress, high switching device ratings, high
In addition, the gate drive circuit of the proposed topology
switching losses, and high electromagnetic interference (EMI).
can draw power directly from the dc capacitor of the inverter
In this paper, a new compact, low-weight, low-cost PFC using
without isolation. A simple charge-pump gate drive circuit
a series active filter is proposed. Comparing with the traditional
powered by the inverter dc capacitor can be easily implemented
PFC, it has lower device ratings, lower cost, lower EMI, and
for each MOSFET. Compared with the high transfer ratio and
higher efficiency. The inductor needed in the proposed series
isolated power supply needed in the gate drive circuit of the
PFC is also much smaller than those in the traditional PFC, and
traditional boost PFC, the proposed topology can also reduce
in the most cases, the line impedance of the utility line is enough
the complexity and cost of the gate drive signal tremendously.
for its normal operation. A hysteresis control strategy, which is
The EMI problem due to the while switching is also a
big concern of the PFC system. In the proposed PFC, the voltage
Manuscript received August 19, 2003; revised April 28, 2004. Recommended stress on the switching devices is only , which is less than
by Associate Editor H. du T. Mouton. 50 V, while the switching device in the traditional boost PFC
The authors are with the Department of Electrical and Computer En- needs to switch on and off the whole dc bus voltage, 250 V.
gineering, Michigan State University, East Lansing, MI 48824-1226 USA
(e-mail: zpan@egr.msu.edu). Therefore, the EMI interference during switching will be re-
Digital Object Identifier 10.1109/TPEL.2004.839819 duced significantly. The voltage distortion brought into the ac
0885-8993/$20.00 © 2005 IEEE
PAN et al.: POWER FACTOR CORRECTION 149

Fig. 2. Proposed PFC.

grid by the proposed circuit also can be neglected because 1)

the inverter dc voltage is relatively low ( V) and 2) the line
impedance, with the inductance of the optional inductor,
are normally far greater than the source impedance, .
The simplified equivalent circuit is shown in Fig. 3, where
is the total line impedance, . The relationship Fig. 3. Equivalent ciruit of proposed PFC.
between the output voltage of the inverter and the state of each
switch can be summarized by

(1)

where is defined as
for is ON and is OFF
for both are ON or OFF simultaneously
for is OFF and is ON
(2)
Note that and are complimentary pairs, re-
spectively.
From the equivalent circuit shown in Fig. 3, the line current
satisfies

(3)

where
for or Fig. 4. Hysteresis control.
for or (4)
for and filter, and fed into a hysteresis comparator. The output of the in-
and is the rectifier capacitor voltage. verter will switch between and to limit the harmonic
Assume that and are constant. The line current, current within the hysteresis band. In this control strategy, the
can be controlled when , or zero voltage of the inverter is not utilized, which results in higher
is satisfied. Thus, the series inverter with enough dc voltage is switching frequency and higher switching ripples. In order to
able to make the line current follow the desired reference. reduce the switching frequency and the voltage ripple, the zero
voltage has to be utilized.
III. CONTROL STRATEGY Fig. 4(b) shows the proposed double hysteresis control, which
utilizes the zero voltage output of the inverter. In this control
A. Hysteresis Control strategy, two hysteresis comparators with different hysteresis
The easiest way to control the proposed topology is to use the widths, and , are used. Since the two phase legs of the
hysteresis control, as shown in Fig. 4(a). In this control, the har- full-bridge inverter are symmetrical, we can assume that is
monic component of the line current, is extracted by a notch greater than . Fig. 5 illustrates the comparator and inverter
150 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 1, JANUARY 2005

Fig. 6. Block diagram of hysteresis control with dc voltage control.

to be zero. However, it cannot be automatically guaranteed in

the actual circuit. So a voltage feedback control shown in Fig. 6
is added to regulate the dc voltage of the inverter.
In this circuit, the actual dc capacitor voltage is detected and
compared with the reference value, and the error is fed into a
PI controller. A sinusoidal signal in phase with the line voltage
Fig. 5. Operation principle of the double hysteresis control. is added to the harmonic currents extracted by the notch filter.
The amplitude of the sinusoidal signal is controlled by the PI
controller. By adding the sinusoidal offset to the input of the
waveforms, where and are 3 A and 2 A, respectively.
When the line voltage, satisfies , hysteresis comparator, active power flowing into the capacitor
the output of comparator 1 is always high, i.e., switch is will be changed, thus the dc capacitor voltage can be controlled.
turned on. Then the output of the inverter switches between 0
C. Switching Frequency and Voltage Ripple
and , according the output of comparator 2, to force the
line current to follow the sinusoidal reference. Considering at Since the hysteresis control is used to control the switching
reaches the upper limit of comparator 2 and the devices, the switching frequency is not constant. However, it is
output of comparator 2 flips to high, then the output of the in- desirable to estimate the average switching frequency for design
verter becomes 0. According to (3), the derivative of the har- purposes.
monic current, becomes negative, and starts to de- Fig. 7 illustrates the switching pattern of the hysteresis control
crease. At reaches the lower limit of comparator 2, when the line voltage satisfies , and the
then the output of the inverter changes to and stops de- output of the inverter switches between 0 and .
creasing and begins to increase again. Therefore, for During period , the inverter voltage and the line current
is limited within the hysteresis band of com- satisfy
parator 2. Since does not reach either limit of comparator 1,
the output of comparator 1 will always remain high during this (5)
period. At changes to negative, keeps de- (6)
creasing slowly as the line voltage, approaches . When
surpasses at becomes positive according to (3). Similarly, during period , we have
Then starts to increase and reaches the upper limit (2 A) of
comparator 2 again. Since the output of comparator 2 is already (7)
high, will keep increasing until reaches the lower limit (8)
( A) of comparator 1 at , when the output of comparator 1
flips to low. After , the output of the inverter switches between Assume that the switching frequency is much higher than the
0 and to control the harmonic current within the hysteresis fundamental frequency, thus can be assumed as a constant
band of comparator 2. Similarly, we can analyze the operation value during one switching cycle, then and can be given
for and . by
In this control strategy, switches and only switch
three times per fundamental cycle. The switching frequency and (9)
of switches and is approximately half that of the single
hysteresis control with the same hysteresis width. Therefore, (10)
the double hysteresis control strategy tremendously reduces the
switching frequency.
The duty cycle and switching frequency can be written as
B. Voltage Control of DC Capacitor
and (11)
In the former discussion, we assume that the dc capacitor
voltage of the inverter is constant, which requires the net av-
erage active power flowing into the capacitor during one cycle (12)
PAN et al.: POWER FACTOR CORRECTION 151

Fig. 7. Switching pattern of the hysteresis control.

Similarly, for , the duty cycle and

switching frequency are given by

and (13)

(14)

Since the line voltage, varies over time in magnitude, the duty
cycle and frequency are also changing in corresponding to the
line voltage. Assuming that the hysteresis width is small enough,
the line current will follow the sinusoidal waveform when the
line voltage satisfies , and stay at zero when
satisfies . It can be seen that the line current
Fig. 8. Waveform of line current i in the ideal case, duty cycle D and
is closer to a sinusoidal waveform when is higher. Fig. 8 f
switching frequency .
shows the waveforms of the line current in the ideal case, the
duty cycle, and the switching frequency, where during this period because the polarity of is positive, same as
the polarity of . also keeps discharging when satisfies
(15)
because is negative and is either 0 or
(16) during this period. Similarly, keeps charging when is
greater than . Thus, the maximum and minimum value of
and is the peak value of the line voltage.
occurs at and , respectively. The voltage ripple on the
The actual switching frequency, which is the average fre-
capacitor can be determined by integrating the current flowed
quency over one line cycle, can be calculated as
into the capacitor over time , which is

(17)
(19)
From (17), it can be seen that the optional inductor can fur-
where is the peak value of the line current. The required
ther reduce the switching frequency and the switching losses.
capacitance of the inverter for an acceptable voltage ripple can
However, the line impedance will be enough to get good perfor-
be obtained from (19).
mance for most cases.
The line current, charges, discharges, or bypasses the dc D. Switching Frequency Balancing
capacitor depending on the switching state . The dc capacitor
voltage can be expressed as In the double hysteresis control, the switching frequency of
the phase leg is only three times the fundamental fre-
(18) quency, while the phase leg has much higher frequency
as expressed in (17). The unbalance of the switching frequen-
where switching state is defined in (2). From the above anal- cies of two phase legs results in the unbalance of stress and
ysis of the hysteresis control, is either 0 or 1 when sat- power losses. Fortunately, a switching frequency balancing cir-
isfies . The dc capacitor keeps discharging cuit can be easily implemented by a simple digital logic circuit
152 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 1, JANUARY 2005

Fig. 9. Schematic of the switching frequency balancing circuit.

Fig. 12. Experimental result of proposed control strategy. V = 100 V, V =

40 V, V = 114 V, I = 20 A, H = 2 A.

Fig. 10. Result of swiching frequency balancing circuit.

Fig. 11. Simulation result of proposed control strategy.

Fig. 13. Experimental result of proposed control strategy. V = 100 V, V =

by utilizing the switching states redundancy of the zero voltage 53 V, V = 100 V, I = 17 A, H = 2 A.
output.
Fig. 9 shows the schematic of the switching frequency bal-
ancing circuit. It alternates the zero output between two states: From the simulation results, it can be seen that the line cur-
and both ON and and both ON. The result of the rent is improved and becomes nearly sinusoidal. Also it is shown
balancing circuit is shown in Fig. 10, where and are unbal- that the voltage of the capacitor is well balanced with an average
anced gate drive signals and and are balanced gate drive value of 50.2 V. The maximum and the minimum of the are
signals. From Fig. 10, it can be seen that the switching frequen- 52.2 and 47.0 V, respectively, and the ripple voltage is 5.2 V,
cies of the two phase legs are well balanced and become half of or 10%, which agrees well with the analytical calculation. The
the original frequency of while generating the same output switching frequencies of and are 180 Hz and 27 kHz, re-
voltage. spectively, which are also consistent with our previous analysis.
A series PFC prototype with the proposed control strategy
has been implemented. Experimental waveforms are shown in
IV. SIMULATION AND EXPERIMENTAL RESULTS
Figs. 12 and 13. Fig. 12 is the result when the reference value
According to the analysis above, a PFC circuit has been de- of was 40 V, where the current THD dropped to 24% after
signed. The parameters of the load and power source are: output correction, and the current displacement was 1.2 , resulting in
power kW, V (rms), 60 Hz. The reference a power factor of 0.97. Fig. 13 is the result when the reference
value of was set to 50 V and to 2 A. Letting the ripple value of was 50 V. According to our previous analysis, the
voltage of the dc capacitor be less than 10%, the minimum ca- line current should be closer to a sinusoidal waveform in this
pacitance should be 4 mF according to (19). Assume that the case, which was verified by the experimental waveform. The
line inductance is 0.2% p.u., which is 53 H. Simulation results current THD dropped to 11% after correction, and the current
are shown in Fig. 11. displacement was 0.8 , resulting a power factor of 0.99.
PAN et al.: POWER FACTOR CORRECTION 153

V. CONCLUSION Fang Z. Peng (M’92–SM’96–F’05) received the B.S.

degree in electrical engineering from Wuhan Univer-
In this paper, a new PFC with double hysteresis control has sity, Wuhan, China, in 1983 and the M.S. and Ph.D.
been presented. The operation principle has been discussed in degrees in electrical engineering from Nagaoka Uni-
versity of Technology, Niigata, Japan, in 1987 and
detail. A 1-kW prototype has been built to verify the analysis 1990, respectively.
and simulation results. It shows that a high power factor has been He joined Toyo Electric Manufacturing Company,
obtained. Compared with the traditional PFC, the proposed PFC Ltd., from 1990 to 1992 as a Research Scientist, was
engaged in research and development of active power
has the following advantages: 1) lower devices rating, which re- filters, flexible ac transmission systems (FACTS) ap-
duces cost, EMI, and switching losses, 2) no additional inductor plications, and motor drives. From 1992 to 1994, he
is required, the line impedance is enough for most cases, and worked with Tokyo Institute of Technology, Tokyo, Japan, as a Research As-
sistant Professor, and initiated a multilevel inverter program for FACTS ap-
3) the proposed double hysteresis control reduces the switching plications and a speed-sensorless vector control project. From 1994 to 2000,
frequency significantly, which leads to higher efficiency. he was a Research Assistant Professor with Oak Ridge National Laboratory
(ORNL), University of Tennessee, Knoxville, from 1994 to 1997, and was a
Staff Member, Lead (Principal) Scientist of the Power Electronics and Electric
REFERENCES Machinery Research Center, ORNL, from 1997 to 2000. Since 2000, he has been
[1] O. Garcia, J. A. Cobos, R. Prieto, P. Alou, and J. Uceda, “Power factor an Associate Professor with the Department of Electrical and Computer Engi-
correction: A survey,” in Proc. IEEE Annu. Power Electronics Special- neering, Michigan State University, East Lansing. He is also currently a Spe-
ists Conf. (PESC’01), 2001, pp. 8–13. cially Invited Adjunct Professor with Zhejiang University, Hangzhou, China.
[2] J. Itoh and K. Fujita, “Novel unity power factor circuits using zero-vector He holds over 10 patents.
control for single phase input system,” in Proc. IEEE Applied Power Dr. Peng received the 1996 First Prize Paper Award and the 1995 Second
Electronics Conf. (APEC’99), 1999, pp. 1039–1045. Prize Paper Award of Industrial Power Converter Committee in IEEE/IAS An-
[3] F. Z. Peng, “Application issues and characteristics of active power fil- nual Meeting, the 1996 Advanced Technology Award of the Inventors Clubs of
ters,” IEEE Ind. Applicat. Mag., vol. 4, pp. 21–30, Sep./Oct. 1998. America, Inc., the International Hall of Fame; the 1991 First Prize Paper Award
[4] C. Qiao and K. M. Smedley, “A topology survey of single-stage power in the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, the 1990 Best Paper
factor corrector with a boost type input-current-shaper,” in Proc. IEEE Award in the Transactions of the IEE of Japan, and the Promotion Award of the
Applied Power Electronics Conf. (APEC’00), 2000, pp. 460–467. Electrical Academy. He has been an Associate Editor for IEEE TRANSACTIONS
[5] F. Z. Peng, H. Akagi, and A. Nabae, “A new approach to harmonic ON POWER ELECTRONICS since 1997 and Chair of Technical Committee for Rec-
compensation in power systems—A combined system of shunt passive tifiers and Inverters of IEEE Power Electronics Society.
and series active filters,” IEEE Trans. Ind. Applicat., vol. 26, no. 6, pp.
983–990, Nov./Dec. 1990.

Suilin Wang received the B.S. and M.S. degrees in

Zhiguo Pan (S’02) received the B.E degree in elec- electrical engineering from Huazhong University of
trical engineering from Xi’an Jiaotong University, Science and Technology, Wuhan, China, in 1987 and
Xian, China, in 1997, the M.E. degree in electrical 1990, respectively.
engineering from Tsinghua University, Beijing, From 1990 to 2001, he was a Development
China, in 2001, and is currently pursuing the Ph.D. Engineer with Huazhong CNC System Co., Ltd.
degree at Michigan State University, East Lansing. (a company affiliated to Huazhong University of
His research interests include power factor cor- Science and Technology). Since 2002, he has been
rection techniques, multilevel converters, and dc–dc a Research Scholar with Michigan State University,
converters. East Lansing. His major research interest is real-time
control in power electronic applications.