test & measurement

ATM18 Logic Analyzer

for deft data acquisition
By Wolfgang Rudolph and Burkhard Kainka (Germany)

The oscilloscope is a fine tool for showing the evolution of a signal in time, but when it comes to digital
signals it soon shows its limitations. Few oscilloscopes can clearly show more than four signals at once, and
setting up complex trigger conditions can be messy. If it is logic levels rather than pulse shapes that matter, a
software-based logic analyzer like the one described here can offer a very powerful alternative solution.

A logic analyzer is an instrument for moni- inputs: even the simplest units have six- and forwards through a series of events: a
toring how signals in a digital circuit change teen inputs and top-end models aimed at kind of time machine for digital signals.
with time. This can of course also be done analyzing complex digital circuits have up to Unfortunately, as you might expect, these
using an analog or a digital oscilloscope, 512 inputs. The y-axis of the analyzer’s dis- instruments are not cheap.
but these devices tend to be limited in the play is only capable of displaying logic lev-
number of channels that they can simulta- els, ‘0’, ‘1’, or ‘undefined’. There is no provi-
neously process and display, and it can be sion for direct measurement of the voltage Analysis using an oscilloscope
difficult to set up the wanted triggering con- on an input as on an oscilloscope. However, Suppose you want to examine the signals
ditions. However, they are useful for mea- the unit can store a very complex series of on a serial port, a job which is actually more
suring certain properties of signals, such as events for each of its digital inputs. With the complicated than it first appears. An ordi-
pulse width, rise and fall times and signal right add-on module, a good analyzer can nary analog oscilloscope will clearly show
period. Glitches, however, can generally follow the execution of a computer program you the signal levels and the duration of
only be observed if they happen to occur in real time, disassembling and displaying each bit, but the data actually being sent are
at the right time and have sufficiently long instructions as it goes, by simply connect- still shrouded in mystery: what is being sent
duration. ing it to the address and data buses of the in the reverse direction, and what is hap-
microprocessor under test. pening on the handshake and other control
The earliest logic analyzers appeared on the lines? What should we use as a trigger sig-
market in the 1970s, and rapidly became Even though many modern microcontrollers nal? As soon as a signal has been detected,
valuable tools for engineers working in the feature diagnostic interfaces and built-in it disappears again. Although analysis
then rapidly-growing field of digital elec- hardware support for software debugging, using an oscilloscope may be practical at
tronics. These early examples featured a the logic analyzer is still a valuable trouble- 300 baud, at higher speeds it becomes very
maximum of eight input channels and were shooting weapon in the engineer’s arsenal difficult indeed.
relatively hard to use. of test equipment, allowing a rapid overview A storage oscilloscope is a better proposi-
In comparison to oscilloscopes, modern of what is happening on all input channels tion in these circumstances, since it allows
logic analyzers have considerably more and the ability to scroll rapidly backwards you to examine a portion of a signal at your

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leisure. However, you will need several chan-

nels as well as independent triggering for
each channel. And, of course, more chan-
nels translates into higher cost.

Figure 1. Acquisition of six digital inputs. Figure 2. Triggered acquisition.

ATM18 as logic analyzer
Previous articles have shown that our ATM18
processor board is a very flexible piece of
hardware. As we shall see below, with the is based on that used in the oscilloscope is programming an ATmega8 device. To
right software it can even be pressed into project, with the timebase and triggering observe the process it is best to set the ISP
service as a logic analyzer. There are six free code, for example, being very similar. clock rate to its lowest value of 1.2 kHz.
input ports that we can use as inputs, and Listing 1 shows an excerpt from the BAS- From top to bottom the signals are SCK,
the processing required is well within the COM program Logic1.bas. The data acqui- MISO, MOSI and Reset. As can be seen,
capability of the processor. All we need to sition itself is done using a timer interrupt. Reset is held low during the programming
do is monitor whether the voltage at each Taking one sample per interrupt gives a process. The programmer generates the
input is above or below a set threshold: maximum sample rate of 10 kHz and a dis-
played timebase of 1 ms per division. To
• if the voltage is above the threshold, a obtain faster sampling (up to 50 kHz, or
logic ‘high’ is displayed; 0.2 ms per division) we have to avoid paying Listing 1
the penalty of interrupt latency. If the high-
Storing digital data (BASCOM program
• if the voltage is below the threshold, a est sample rates are selected, therefore, the Logic1.bas)
logic ‘low’ is displayed. processor will acquire all 501 samples in a
single loop, without leaving the interrupt Tim1_isr:
The resulting stored values are then trans- service routine. If Timebase > -30 Then
ferred to a host PC, where they are displayed All six digital inputs have a pull-up resistor For Adr = 0 To 501
as greatly simplified oscilloscope traces with enabled. This means that in the quiescent D = Pinc
a vertical resolution of just one bit. state they will all read as ‘high’ (see Fig- Ram(adr) = D
The ATM18 thus offers a cheap and cheer- ure 1). The traces only change when signals Next Adr
ful solution. The project as described here are applied to one or more channels. Else
offers simultaneous acquisition over the six Timer1 = Timebase
input channels, and there are two versions Portb.0 = 1
of the firmware to choose from, offering dif- Triggering D = Pinc
ferent features. The trigger function implemented in the If Saveram = 1 Then
software allows acquisition to start at a Ram(adr) = D
defined point in time. It is necessary to Adr = Adr + 1
Digital inputs specify what levels are required on which Else
The essence of the operation of a logic channels to initiate the process. The levels Put #1 , D
analyzer is simple: values are read from an on inputs PC0 to PC5 are combined into a End If
entire port in rapid succession and then single binary value for this purpose. Fig- End If
stored to memory. Then the values are ure 2 shows the result of an acquisition
transferred to a program running on a PC, triggered by a rising edge on input PC2. If Adr > 501 Then
where they are separated out into individ- The other inputs are not connected in this For Adr = 1 To 501
ual bits. The process is highly reminiscent example and therefore are read as high: this D = Ram(adr)
of the storage oscilloscope article ‘Scop- must also be reflected in the bits of the trig- Put #1 , D
ing with the ATM18’ that we published in ger value corresponding to PC3 to PC5. The Next Adr
the April 2009 issue of Elektor [1]. The case resulting value in this case is binary 111100 Adr = 1
here is somewhat simpler as we simply need (decimal 60). The unit will begin acquisition If Oneshot = 1 Then
to read a value directly from a port rather when this value is first seen on the input Stop Timer1
than from a multi-channel analog-to-digi- port. End If
tal converter. The six digital inputs used are End If
pins PC0 to PC5 of port C, the only external Figure 3 shows an example acquisition Portb.0 = 0
circuitry required being a set of series 4k7 using four channels, in this case connected Return
resistors to protect the inputs. The software to an Atmel STK500 programmer while it

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test & measurement

tion of whether they have been correctly

received by the target processor.
This example demonstrates the benefit
of having multiple digital channels avail-
able, but also a weakness of the software: it
would be highly desirable to have a longer
Figure 3. A four-channel acquisition. Figure 4. An acquisition lasting 200 ms. data buffer to allow acquisition over a lon-
ger time period, but retaining the ability to
zoom in to details of the signal behavior. If
clock signal and outputs the data to be After a delay of exactly eight clocks the data we slow the timebase down to, for exam-
programmed one byte at a time on MOSI. values reappear on MISO, giving an indica- ple, 20 ms per division (Figure 4) then it is

Listing 2 Picture1.Line (X1, Y1)-(X2, Y1), &H0&

Display of six bits (Visual Basic program ATM18Logic1.vbp) Picture1.Line (X2, Y1)-(X2, Y2), &H0&
For n = 1 To 498 Y1 = 120 - 4 * (Ch1(n) And 8)
X1 = n Y2 = 120 - 4 * (Ch1(n + 1) And 8)
X2 = n + 1 Picture1.Line (X1, Y1)-(X2, Y1), &H0&
Y1 = 240 - 32 * (Ch1(n) And 1) Picture1.Line (X2, Y1)-(X2, Y2), &H0&
Y2 = 240 - 32 * (Ch1(n + 1) And 1) Y1 = 80 - 2 * (Ch1(n) And 16)
Picture1.Line (X1, Y1)-(X2, Y1), &H0& Y2 = 80 - 2 * (Ch1(n + 1) And 16)
Picture1.Line (X2, Y1)-(X2, Y2), &H0& Picture1.Line (X1, Y1)-(X2, Y1), &H0&
Y1 = 200 - 16 * (Ch1(n) And 2) Picture1.Line (X2, Y1)-(X2, Y2), &H0&
Y2 = 200 - 16 * (Ch1(n + 1) And 2) Y1 = 40 - 1 * (Ch1(n) And 32)
Picture1.Line (X1, Y1)-(X2, Y1), &H0& Y2 = 40 - 1 * (Ch1(n + 1) And 32)
Picture1.Line (X2, Y1)-(X2, Y2), &H0& Picture1.Line (X1, Y1)-(X2, Y1), &H0&
Y1 = 160 - 8 * (Ch1(n) And 4) Picture1.Line (X2, Y1)-(X2, Y2), &H0&
Y2 = 160 - 8 * (Ch1(n + 1) And 4) Next n

Listing 3 End If
If Timestamp > 60000 Then
Use of timestamps (BASCOM program Logic2.bas)
Do
Sub Logger Ram(adr) = D
Timer1 = 0 Adr = Adr + 1
Adr = 1 A = High(timestamp)
Dold = 255 Ram(adr) = A
Do Adr = Adr + 1
Timestamp = Timer1 A = Timestamp
D = Pinc Ram(adr) = A
Portb.0 = 1 Adr = Adr + 1
If D <> Dold Then
Ram(adr) = D Loop Until Adr > 500
Adr = Adr + 1 End If
A = High(timestamp) Portb.0 = 0
Ram(adr) = A Loop Until Adr > 500
Adr = Adr + 1 For Adr = 1 To 501
A = Timestamp D = Ram(adr)
Ram(adr) = A Put #1 , D
Adr = Adr + 1 Next Adr
Dold = D End Sub

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possible to see a longer record covering the

programming of around ten bytes, but the
details of the clock signal and its time rela-
tionship to the data signal are lost. A record
length of 500 samples is not enough to give
a full overview of the process.
Figure 5. Signals on an I2C bus. Figure 6. I2C bus signals under the
magnifying glass.
Timestamps
The underlying problem is that digital sig- filled, the last state will be repeated until In conclusion
nals can include both very brief and very long the buffer is full. This gets around the prob- This project has again demonstrated the
pulses. We would like to have a much larger lem that if fewer than 167 state changes potential of modern microcontrollers and
memory buffer (and, ideally, a correspond- occur the system would wait for ever with- the versatility of the ATM18 board, which
ingly larger monitor on which to view the out displaying any results to the user, the has been turned into a logic analyzer with
results). Both, unfortunately, are expensive. timeout ensuring that even constant sig- very little effort. By converting the soft-
nals are displayed. The total acquisition ware [2] into C or assembler it would be pos-
There is, however, a solution. In the exam- time now depends on the signal being sible to achieve higher time resolution, and
ples we have looked at there have been long observed: with constant or very slowly the PC program that displays the results
periods where the state of a signal does not changing input the total time will reach its also has plenty of scope for expansion. One
change, which is rather wasteful of memory. maximum of 240 ms, while the shortest possibility would be to automatically anal-
If, instead of storing values at regular inter- possible total acquisition time is just 2 ms, yse the bit patterns that have been acquired
vals of time, we store values only when they a ratio of 120 to 1. The maximum sample from a serial port and convert them into
change, we can save on memory. The cost is rate is approximately 200 kHz. ASCII characters to be displayed alongside
that each sample now needs to be accompa- the waveforms. Although our little logic
nied by a timestamp. The timestamp might The decisive advantage of this technique is analyzer lacks the performance and some of
take the form of a 16-bit quantity, mea- that it is possible to display the results from the features of its professional cousins, the
sured to a resolution of 4 µs using Timer 1 a single acquisition and analyse them at basic principles are much the same: we have
(see Listing 3). A total of three bytes are various timebases at your leisure. You can learned a lot more and spent a lot less!
now required for each sample, and we can scroll through the data to look for signifi- (080949-I)
fit 167 state changes in the memory buffer. cant events. For example, you can set the
This is fewer than before, but we can now timebase to 10 ms per division to get an
mix short and long pulses at will. Listing 4 overview of the situation and then zoom
shows how the timestamps are converted in for a closer look. Figure 5 shows some
into x-coordinates in the Visual Basic pro- activity on an I 2C bus: you can see that
gram running on the PC. there is a gap of around 30 ms between the
individual data packets. Figure 6 shows a Internet Links
The implementation includes a further close-up displaying a part of the transac-
compromise, in that if 60000 time units tion in greater detail. [1] www.elektor.com/080944
(240 ms) pass and the buffer has not been [2] www.elektor.com/080949

Listing 4 Y2 = 240 - 32 * (Ch1(n + 3) And 1)

Picture1.Line (X1, Y1)-(X2, Y1), &H0&
Converting timestamps into x-coordinates
(Visual Basic program ATM18Logic2.vbp) Picture1.Line (X2, Y1)-(X2, Y2), &H0&
Y1 = 200 - 16 * (Ch1(n) And 2)
X1 = 0 Y2 = 200 - 16 * (Ch1(n + 3) And 2)
For n = 0 To 497 Step 3 Picture1.Line (X1, Y1)-(X2, Y1), &H0&
X2 = (Ch1(n + 5) + 256 * Ch1(n + 4)) Picture1.Line (X2, Y1)-(X2, Y2), &H0&
X2 = X2 - Pos * 80 …
X2 = X2 / zoom …
If X2 < 0 Then X2 = 0 X1 = X2
If X2 > 500 Then Pos2 = 500 Next n
Y1 = 240 - 32 * (Ch1(n) And 1) End Sub

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