06-05-2019

Chapter 8

Digital Design and Computer Architecture, 2nd Edition

David Money Harris and Sarah L. Harris

Chapter 8 <1>

Chapter 8 :: Topics

• Introduction
• Memory System Performance
Analysis
• Caches
• Virtual Memory
• Memory-Mapped I/O
• Summary

Chapter 8 <2>

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Introduction
• Computer performance depends on:
– Processor performance
– Memory system performance
Memory Interface
CLK CLK

MemWrite WE
Address ReadData
Processor Memory
WriteData

Chapter 8 <3>

Processor-Memory Gap
In prior chapters, assumed access memory in 1 clock
cycle – but hasn’t been true since the 1980’s

Chapter 8 <4>

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Memory System Challenge

• Make memory system appear as fast as
processor
• Use hierarchy of memories
• Ideal memory:
– Fast
– Cheap (inexpensive)
– Large (capacity)

But can only choose two!

Chapter 8 <5>

Memory Hierarchy

Access Bandwidth
Technology Price / GB
Time (ns) (GB/s)

SRAM $10,000 1 25+

Cache

DRAM $10 10 - 50 10
Speed

Main Memory

SSD $1 100,000 0.5

HDD $0.1 10,000,000 0.1
Virtual Memory
Capacity

Chapter 8 <6>

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Locality
Exploit locality to make memory accesses fast
• Temporal Locality:
– Locality in time
– If data used recently, likely to use it again soon
– How to exploit: keep recently accessed data in higher
levels of memory hierarchy
• Spatial Locality:
– Locality in space
– If data used recently, likely to use nearby data soon
– How to exploit: when access data, bring nearby data
into higher levels of memory hierarchy too
Chapter 8 <7>

Memory Performance
• Hit: data found in that level of memory hierarchy
• Miss: data not found (must go to next level)

• Average memory access time (AMAT): average time

for processor to access data
AMAT = tcache + MRcache[tMM + MRMM(tVM)]
is the average time a processor must wait for memory per load or store
instruction
Chapter 8 <8>

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Memory Performance Example 1

• A program has 2,000 loads and stores
• 1,250 of these data values in cache
• Rest supplied by other levels of memory
hierarchy
• What are the hit and miss rates for the cache?

Chapter 8 <9>

Memory Performance Example 1

• A program has 2,000 loads and stores
• 1,250 of these data values in cache
• Rest supplied by other levels of memory
hierarchy
• What are the hit and miss rates for the cache?

Hit Rate = 1250/2000 = 0.625

Miss Rate = 750/2000 = 0.375 = 1 – Hit Rate

Chapter 8 <10>

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Memory Performance Example 2

• Suppose processor has 2 levels of hierarchy:
cache and main memory
• tcache = 1 cycle, tMM = 100 cycles
• What is the AMAT of the program from
Example 1?

Chapter 8 <11>

Memory Performance Example 2

• Suppose processor has 2 levels of hierarchy:
cache and main memory
• tcache = 1 cycle, tMM = 100 cycles
• What is the AMAT of the program from
Example 1?

AMAT = tcache + MRcache(tMM)

= [1 + 0.375(100)] cycles
= 38.5 cycles

Chapter 8 <12>

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Gene Amdahl, 1922-

• Amdahl’s Law: the

effort spent increasing the
performance of a
subsystem is wasted
unless the subsystem
affects a large percentage
of overall performance
• Co-founded 3 companies,
including one called
Amdahl Corporation in
1970
Chapter 8 <13>

Cache
• Highest level in memory hierarchy
• Fast (typically ~ 1 cycle access time)
• Ideally supplies most data to processor
• Usually holds most recently accessed data

Chapter 8 <14>

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Cache Design Questions

• What data is held in the cache?
• How is data found?
• What data is replaced?

Focus on data loads, but stores follow same principles

Chapter 8 <15>

What data is held in the cache?

• Ideally, cache anticipates needed data and
puts it in cache
• But impossible to predict future
• Use past to predict future – temporal and
spatial locality:
– Temporal locality: copy newly accessed data
into cache
– Spatial locality: copy neighboring data into
cache too

Chapter 8 <16>

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Cache Terminology
• Capacity (C):
– number of data bytes in cache
• Block size (b):
– bytes of data brought into cache at once
• Number of blocks (B = C/b):
– number of blocks in cache: B = C/b
• Degree of associativity (N):
– number of blocks in a set
• Number of sets (S = B/N):
– each memory address maps to exactly one cache set

Chapter 8 <17>

How is data found?

• Cache organized into S sets
• Each memory address maps to exactly one set
• Caches categorized by # of blocks in a set:
– Direct mapped: 1 block per set
– N-way set associative: N blocks per set
– Fully associative: all cache blocks in 1 set
• Examine each organization for a cache with:
– Capacity (C = 8 words)
– Block size (b = 1 word)
– So, number of blocks (B = 8) Chapter 8 <18>

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Example Cache Parameters

• C = 8 words (capacity)
• b = 1 word (block size)
• So, B = 8 (# of blocks)

Ridiculously small, but will illustrate organizations

Chapter 8 <19>

Direct Mapped Cache

Address
11...11111100 mem[0xFF...FC]
11...11111000 mem[0xFF...F8]
11...11110100 mem[0xFF...F4]
11...11110000 mem[0xFF...F0]
11...11101100 mem[0xFF...EC]
11...11101000 mem[0xFF...E8]
11...11100100 mem[0xFF...E4]
11...11100000 mem[0xFF...E0]

00...00100100 mem[0x00...24]
00...00100000 mem[0x00..20] Set Number
00...00011100 mem[0x00..1C] 7 (111)
00...00011000 mem[0x00...18] 6 (110)
00...00010100 mem[0x00...14] 5 (101)
00...00010000 mem[0x00...10] 4 (100)
00...00001100 mem[0x00...0C] 3 (011)
00...00001000 mem[0x00...08] 2 (010)
00...00000100 mem[0x00...04] 1 (001)
00...00000000 mem[0x00...00] 0 (000)

230 Word Main Memory 23 Word Cache

Chapter 8 <20>

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Direct Mapped Cache Hardware

Byte
Tag Set Offset
Memory
00
Address
27 3
V Tag Data

8-entry x
(1+27+32)-bit
SRAM

27 32

Hit Data

Chapter 8 <21>

Direct Mapped Cache Performance

Byte
Tag Set Offset
Memory
00...00 001 00
Address 3
V Tag Data
0 Set 7 (111)
# MIPS assembly code 0 Set 6 (110)
0 Set 5 (101)
addi $t0, $0, 5 0 Set 4 (100)
1 00...00 mem[0x00...0C] Set 3 (011)
loop: beq $t0, $0, done
1 00...00 mem[0x00...08] Set 2 (010)
lw $t1, 0x4($0) 1 00...00 mem[0x00...04] Set 1 (001)
lw $t2, 0xC($0) 0 Set 0 (000)
lw $t3, 0x8($0)
addi $t0, $t0, -1 Miss Rate = ?
j loop
done:

Chapter 8 <22>

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Direct Mapped Cache Performance

Byte
Tag Set Offset
Memory
00...00 001 00
Address 3
V Tag Data
0 Set 7 (111)
# MIPS assembly code 0 Set 6 (110)
0 Set 5 (101)
addi $t0, $0, 5 0 Set 4 (100)
1 00...00 mem[0x00...0C] Set 3 (011)
loop: beq $t0, $0, done
1 00...00 mem[0x00...08] Set 2 (010)
lw $t1, 0x4($0) 1 00...00 mem[0x00...04] Set 1 (001)
lw $t2, 0xC($0) 0 Set 0 (000)
lw $t3, 0x8($0)
addi $t0, $t0, -1 Miss Rate = 3/15
j loop = 20%
done:
Temporal Locality
Compulsory Misses
Chapter 8 <23>

Direct Mapped Cache: Conflict

Byte
Tag Set Offset
Memory
00...01 001 00
Address 3
V Tag Data
# MIPS assembly code 0 Set 7 (111)
0 Set 6 (110)
0 Set 5 (101)
addi $t0, $0, 5 0 Set 4 (100)
loop: beq $t0, $0, done 0 Set 3 (011)
lw $t1, 0x4($0) 0 Set 2 (010)
mem[0x00...04] Set 1 (001)
1 00...00 mem[0x00...24]
lw $t2, 0x24($0)
0 Set 0 (000)
addi $t0, $t0, -1
j loop
done:
Miss Rate = ?

Chapter 8 <24>

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Direct Mapped Cache: Conflict

Byte
Tag Set Offset
Memory
00...01 001 00
Address 3
V Tag Data
# MIPS assembly code 0 Set 7 (111)
0 Set 6 (110)
0 Set 5 (101)
addi $t0, $0, 5 0 Set 4 (100)
loop: beq $t0, $0, done 0 Set 3 (011)
lw $t1, 0x4($0) 0 Set 2 (010)
mem[0x00...04] Set 1 (001)
1 00...00 mem[0x00...24]
lw $t2, 0x24($0)
0 Set 0 (000)
addi $t0, $t0, -1
j loop
done:
Miss Rate = 10/10
= 100%
Conflict Misses
Chapter 8 <25>

N-Way Set Associative Cache

Byte
Tag Set Offset
Memory
00
Address Way 1 Way 0
28 2
V Tag Data V Tag Data

28 32 28 32

= =
1

Hit1 Hit 0 Hit1

32

Hit Data

Chapter 8 <26>

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N-Way Set Associative Performance

# MIPS assembly code

addi $t0, $0, 5

loop: beq $t0, $0, done Miss Rate = ?
lw $t1, 0x4($0)
lw $t2, 0x24($0)
addi $t0, $t0, -1
j loop
done:
Way 1 Way 0
V Tag Data V Tag Data
0 0 Set 3
0 0 Set 2
0 0 Set 1
0 0 Set 0

Chapter 8 <27>

N-Way Set Associative Performance

# MIPS assembly code

addi $t0, $0, 5

loop: beq $t0, $0, done Miss Rate = 2/10
lw $t1, 0x4($0) = 20%
lw $t2, 0x24($0)
addi $t0, $t0, -1 Associativity reduces
j loop conflict misses
done:
Way 1 Way 0
V Tag Data V Tag Data
0 0 Set 3
0 0 Set 2
1 00...10 mem[0x00...24] 1 00...00 mem[0x00...04] Set 1
0 0 Set 0

Chapter 8 <28>

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Fully Associative Cache

V Tag Data V Tag Data V Tag Data V Tag Data V Tag Data V Tag Data V Tag Data V Tag Data

Reduces conflict misses

Expensive to build

Chapter 8 <29>

Spatial Locality?
• Increase block size:
– Block size, b = 4 words
– C = 8 words
– Direct mapped (1 block per set)
– Number of blocks, B = 2 (C/b = 8/4 = 2)
Block Byte
Tag Set Offset Offset
Memory
00
Address
27 2
V Tag Data
Set 1
Set 0
27 32 32 32 32
11

10

01

00

32
=

Hit Data
Chapter 8 <30>

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Cache with Larger Block Size

Block Byte
Tag Set Offset Offset
Memory
00
Address
27 2
V Tag Data
Set 1
Set 0
27 32 32 32 32

11

10

01

00
32
=

Hit Data

Chapter 8 <31>

Direct Mapped Cache Performance

addi $t0, $0, 5
loop: beq $t0, $0, done Miss Rate = ?
lw $t1, 0x4($0)
lw $t2, 0xC($0)
lw $t3, 0x8($0)
addi $t0, $t0, -1
j loop
done:

Chapter 8 <32>

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Direct Mapped Cache Performance

addi $t0, $0, 5
loop: beq $t0, $0, done Miss Rate = 1/15
lw $t1, 0x4($0)
lw $t2, 0xC($0)
= 6.67%
lw $t3, 0x8($0)
addi $t0, $t0, -1
Larger blocks
j loop reduce compulsory misses
done:
Block Byte
through spatial locality
Memory Tag Set Offset Offset
00...00 0 11 00
Address
27 2
V Tag Data
0 Set 1
1 00...00 mem[0x00...0C] mem[0x00...08] mem[0x00...04] mem[0x00...00] Set 0
27 32 32 32 32
11

10

01

00
32
=

Hit Data
Chapter 8 <33>

Cache Organization Recap

• Capacity: C
• Block size: b
• Number of blocks in cache: B = C/b
• Number of blocks in a set: N
• Number of sets: S = B/N
Number of Ways Number of Sets
Organization (N) (S = B/N)
Direct Mapped 1 B
N-Way Set Associative 1 < N < B B/N
Fully Associative B 1

Chapter 8 <34>

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Capacity Misses
• Cache is too small to hold all data of interest at once
• If cache full: program accesses data X & evicts data Y
• Capacity miss when access Y again
• How to choose Y to minimize chance of needing it again?
• Least recently used (LRU) replacement: the least recently
used block in a set evicted

Chapter 8 <35>

Types of Misses
• Compulsory: first time data accessed
• Capacity: cache too small to hold all data of
interest
• Conflict: data of interest maps to same
location in cache

Miss penalty: time it takes to retrieve a block from

lower level of hierarchy

Chapter 8 <36>

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LRU Replacement
# MIPS assembly
lw $t0, 0x04($0)
lw $t1, 0x24($0)
lw $t2, 0x54($0)
Way 1 Way 0

V U Tag Data V Tag Data

0 0 0 Set 3 (11)
0 0 0 Set 2 (10)
0 0 0 Set 1 (01)
0 0 0 Set 0 (00)

Chapter 8 <37>

LRU Replacement
# MIPS assembly
lw $t0, 0x04($0)
lw $t1, 0x24($0)
lw $t2, 0x54($0)
Way 1 Way 0

V U Tag Data V Tag Data

0 0 0 Set 3 (11)
0 0 0 Set 2 (10)
1 0 00...010 mem[0x00...24] 1 00...000 mem[0x00...04] Set 1 (01)
0 0 0 Set 0 (00)
(a)
Way 1 Way 0

V U Tag Data V Tag Data

0 0 0 Set 3 (11)
0 0 0 Set 2 (10)
1 1 00...010 mem[0x00...24] 1 00...101 mem[0x00...54] Set 1 (01)
0 0 0 Set 0 (00)
(b)
Chapter 8 <38>

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Cache Summary
• What data is held in the cache?
– Recently used data (temporal locality)
– Nearby data (spatial locality)
• How is data found?
– Set is determined by address of data
– Word within block also determined by address
– In associative caches, data could be in one of several
ways
• What data is replaced?
– Least-recently used way in the set
Chapter 8 <39>

Miss Rate Trends

• Bigger caches reduce capacity misses
• Greater associativity reduces conflict misses

Adapted from Patterson & Hennessy, Computer Architecture: A Quantitative Approach, 2011
Chapter 8 <40>

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Miss Rate Trends

• Bigger blocks reduce compulsory misses

• Bigger blocks increase conflict misses
Chapter 8 <41>

Multilevel Caches
• Larger caches have lower miss rates, longer
access times
• Expand memory hierarchy to multiple levels of
caches
• Level 1: small and fast (e.g. 16 KB, 1 cycle)
• Level 2: larger and slower (e.g. 256 KB, 2-6
cycles)
• Most modern PCs have L1, L2, and L3 cache

Chapter 8 <42>

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Intel Pentium III Die

Chapter 8 <43>

Virtual Memory
• Gives the illusion of bigger memory
• Main memory (DRAM) acts as cache for hard
disk

Chapter 8 <44>

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Memory Hierarchy

Access Bandwidth
Technology Price / GB
Time (ns) (GB/s)

SRAM $10,000 1 25+

Cache

DRAM $10 10 - 50 10
Speed

Main Memory

SSD $1 100,000 0.5

HDD $0.1 10,000,000 0.1
Virtual Memory
Capacity

• Physical Memory: DRAM (Main Memory)

• Virtual Memory: Hard drive
– Slow, Large, Cheap
Chapter 8 <45>

Hard Disk

Magnetic
Disks

Read/Write
Head

Takes milliseconds to seek correct location on disk

Chapter 8 <46>

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Virtual Memory
• Virtual addresses
– Programs use virtual addresses
– Entire virtual address space stored on a hard drive
– Subset of virtual address data in DRAM
– CPU translates virtual addresses into physical addresses
(DRAM addresses)
– Data not in DRAM fetched from hard drive
• Memory Protection
– Each program has own virtual to physical mapping
– Two programs can use same virtual address for different data
– Programs don’t need to be aware others are running
– One program (or virus) can’t corrupt memory used by
another
Chapter 8 <47>

Cache/Virtual Memory Analogues

Cache Virtual Memory
Block Page
Block Size Page Size
Block Offset Page Offset
Miss Page Fault
Tag Virtual Page Number

Physical memory acts as cache for virtual memory

Chapter 8 <48>

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Virtual Memory Definitions

• Page size: amount of memory transferred
from hard disk to DRAM at once
• Address translation: determining physical
address from virtual address
• Page table: lookup table used to translate
virtual addresses to physical addresses

Chapter 8 <49>

Virtual & Physical Addresses

Most accesses hit in physical memory

But programs have the large capacity of virtual memory

Chapter 8 <50>

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Address Translation

Chapter 8 <51>

Virtual Memory Example

• System:
– Virtual memory size: 2 GB = 231 bytes
– Physical memory size: 128 MB = 227 bytes
– Page size: 4 KB = 212 bytes

Chapter 8 <52>

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Virtual Memory Example

• System:
– Virtual memory size: 2 GB = 231 bytes
– Physical memory size: 128 MB = 227 bytes
– Page size: 4 KB = 212 bytes
• Organization:
– Virtual address: 31 bits
– Physical address: 27 bits
– Page offset: 12 bits
– # Virtual pages = 231/212 = 219 (VPN = 19 bits)
– # Physical pages = 227/212 = 215 (PPN = 15 bits)

Chapter 8 <53>

Virtual Memory Example

• 19-bit virtual page numbers
• 15-bit physical page numbers

Chapter 8 <54>

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Virtual Memory Example

What is the physical address

of virtual address 0x247C?

Chapter 8 <55>

Virtual Memory Example

What is the physical address
of virtual address 0x247C?
– VPN = 0x2
– VPN 0x2 maps to PPN 0x7FFF
– 12-bit page offset: 0x47C
– Physical address = 0x7FFF47C

Chapter 8 <56>

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How to perform translation?

• Page table
– Entry for each virtual page
– Entry fields:
• Valid bit: 1 if page in physical memory
• Physical page number: where the page is located

Chapter 8 <57>

Page Table Example

Virtual Page
Page Number Offset
Virtual
0x00002 47C
Address
19 12

Physical
V Page Number
0
0
1 0x0000
VPN is index 1 0x7FFE
0
into page table
Page Table

0
0
1 0x0001
0
0
1 0x7FFF
0
0
15 12
Hit
Physical
0x7FFF 47C
Address
Chapter 8 <58>

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Page Table Example 1

What is the physical V

Physical
Page Number

address of virtual 0
0
1 0x0000
address 0x5F20? 1
0
0x7FFE

Page Table
0

0
0
1 0x0001
0
0
1 0x7FFF
0
0

Chapter 8 <59>

Page Table Example 1

Virtual Page
Page Number Offset
Virtual
0x00005 F20
Address
19 12

What is the physical V

Physical
Page Number

address of virtual 0
0
1 0x0000
address 0x5F20? 1
0
0x7FFE
Page Table

0
– VPN = 5
– Entry 5 in page table 0
0
VPN 5 => physical 1 0x0001
0
page 1 0
1 0x7FFF
– Physical address: 0
0
0x1F20 Hit
15 12

Physical
0x0001 F20
Address

Chapter 8 <60>

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Page Table Example 2

Virtual Page
Page Number Offset
Virtual
0x00007 3E0
Address
19

What is the physical Physical

address of virtual V
0
Page Number

0
address 0x73E0? 1 0x0000
1 0x7FFE
0

Page Table
0

0
0
1 0x0001
0
0
1 0x7FFF
0
0
15
Hit

Chapter 8 <61>

Page Table Example 2

Virtual Page
Page Number Offset
Virtual
0x00007 3E0
Address
19

What is the physical Physical

address of virtual V
0
Page Number

0
address 0x73E0? 1 0x0000
1 0x7FFE
– VPN = 7 0
Page Table

0
– Entry 7 is invalid
– Virtual page must be 0
0
paged into physical 1 0x0001
0
memory from disk 0
1 0x7FFF
0
0
15
Hit

Chapter 8 <62>

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Page Table Challenges

• Page table is large
– usually located in physical memory
• Load/store requires 2 main memory accesses:
– one for translation (page table read)
– one to access data (after translation)
• Cuts memory performance in half
– Unless we get clever…

Chapter 8 <63>

Translation Lookaside Buffer (TLB)

• Small cache of most recent translations
• Reduces # of memory accesses for most
loads/stores from 2 to 1

Chapter 8 <64>

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TLB
• Page table accesses: high temporal locality
– Large page size, so consecutive loads/stores likely to
access same page
• TLB
– Small: accessed in < 1 cycle
– Typically 16 - 512 entries
– Fully associative
– > 99 % hit rates typical
– Reduces # of memory accesses for most loads/stores
from 2 to 1

Chapter 8 <65>

Example 2-Entry TLB

Virtual Page
Page Number Offset
Virtual
0x00002 47C
Address
19 12

Entry 1 Entry 0

Virtual Physical Virtual Physical

V Page Number Page Number V Page Number Page Number
1 0x7FFFD 0x0000 1 0x00002 0x7FFF TLB
19 15 19 15

= =
1

Hit1 Hit0 Hit1

15 12
Physical
Hit Address 0x7FFF 47C

Chapter 8 <66>

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Memory Protection
• Multiple processes (programs) run at once
• Each process has its own page table
• Each process can use entire virtual address
space
• A process can only access physical pages
mapped in its own page table

Chapter 8 <67>

Virtual Memory Summary

• Virtual memory increases capacity
• A subset of virtual pages in physical memory
• Page table maps virtual pages to physical
pages – address translation
• A TLB speeds up address translation
• Different page tables for different programs
provides memory protection

Chapter 8 <68>

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Memory-Mapped I/O
• Processor accesses I/O devices just like
memory (like keyboards, monitors, printers)
• Each I/O device assigned one or more
address
• When that address is detected, data
read/written to I/O device instead of
memory
• A portion of the address space dedicated to
I/O devices

Chapter 8 <69>

Memory-Mapped I/O Hardware

• Address Decoder:
– Looks at address to determine which
device/memory communicates with the
processor
• I/O Registers:
– Hold values written to the I/O devices
• ReadData Multiplexer:
– Selects between memory and I/O devices as
source of data sent to the processor

Chapter 8 <70>

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The Memory Interface

CLK

MemWrite WE
Address ReadData
Processor Memory
W riteData

Chapter 8 <71>

Memory-Mapped I/O Hardware

Address Decoder
WE2
WE1

WEM

RDsel1:0

CLK CLK

MemWrite WE
Address
Processor Memory
WriteData

CLK
00
I/O ReadData
01
EN Device 1 10

I/O
EN Device 2

Chapter 8 <72>

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Input/Output (I/O) Systems

• Embedded I/O Systems

– Toasters, LEDs, etc.
• PC I/O Systems

Chapter 8 <73>

Embedded I/O Systems

• Example microcontroller: PIC32

– microcontroller
– 32-bit MIPS processor
– low-level peripherals include:
• serial ports
• timers
• A/D converters

Chapter 8 <74>

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Digital I/O
// C Code
#include <p3xxxx.h>

int main(void) {
int switches;
TRISD = 0xFF00; // RD[7:0] outputs
// RD[11:8] inputs
while (1) {
// read & mask switches, RD[11:8]
switches = (PORTD >> 8) & 0xF;
PORTD = switches; // display on LEDs
}
}

Chapter 8 <75>

Serial I/O

• Example serial protocols

– SPI: Serial Peripheral Interface
– UART: Universal Asynchronous
Receiver/Transmitter
– Also: I2C, USB, Ethernet, etc.

Chapter 8 <76>

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Personal Computer (PC) I/O Systems

• USB: Universal Serial Bus

– USB 1.0 released in 1996
– standardized cables/software for peripherals
• PCI/PCIe: Peripheral Component
Interconnect/PCI Express
– developed by Intel, widespread around 1994
– 32-bit parallel bus
– used for expansion cards (i.e., sound cards, video
cards, etc.)
• DDR: double-data rate memory
Chapter 8 <77>

Personal Computer (PC) I/O Systems

• TCP/IP: Transmission Control Protocol and

Internet Protocol
– physical connection: Ethernet cable or Wi-Fi
• SATA: hard drive interface
• Input/Output (sensors, actuators,
microcontrollers, etc.)
– Data Acquisition Systems (DAQs)
– USB Links

Chapter 8 <78>

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I/O Bus Examples

Firewire USB 2.0 PCI Express Serial ATA Serial
Attached
SCSI
Intended use External External Internal Internal External
Devices per 63 127 1 1 4
channel

Data width 4 2 2 per lane 4 4

Peak 50MB/s or 0.2MB/s, 250MB/s/lane 300MB/s 300MB/s
bandwidth 100MB/s 1.5MB/s, or 1×, 2×, 4×,
60MB/s 8×, 16×, 32×
Hot Yes Yes Depends Yes Yes
pluggable

Max length 4.5m 5m 0.5m 1m 8m

Standard IEEE 1394 USB PCI-SIG SATA-IO INCITS TC
Implementers T10
Forum

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