X-Propagation

An Alternative to Gate Level Simulation?

Adrian Evans
Craig Forward
Julius Yam

Cisco Systems
Outline

• Introduction We are here !

• Background
– Sources of X in RTL
– Ambiguous RTL Constructs
– Existing Solutions

• X-Propagation Technology
– Introduction
– T-Merge/X-Merge
– Results

• Conclusions

2
X-Propagation
Introduction

• Gate Simulations are a pain!

• Why do we bother?

Reason to run
Gate Simulations
Synthesis Errors
Questionable RTL Style
Timing Verification
Power Analysis
RTL X-Optimism

3
X-Propagation
Introduction

• Gate Simulations are a pain!

• Why do we bother?

Reason to run Alternative

Gate Simulations Approach
Synthesis Errors Equivalence Checking
Questionable RTL Style
Timing Verification
Power Analysis
RTL X-Optimism

4
X-Propagation
Introduction

• Gate Simulations are a pain!

• Why do we bother?

Reason to run Alternative

Gate Simulations Approach
Synthesis Errors Equivalence Checking
Questionable RTL Style Lint Tools
Timing Verification
Power Analysis
RTL X-Optimism

5
X-Propagation
Introduction

• Gate Simulations are a pain!

• Why do we bother?

Reason to run Alternative

Gate Simulations Approach
Synthesis Errors Equivalence Checking
Questionable RTL Style Lint Tools
Timing Verification Static Timing Tools
Power Analysis
RTL X-Optimism

6
X-Propagation
Introduction

• Gate Simulations are a pain!

• Why do we bother?

Reason to run Alternative

Gate Simulations Approach
Synthesis Errors Equivalence Checking
Questionable RTL Style Lint Tools
Timing Verification Static Timing Tools
Power Analysis RTL Power Analysis
RTL X-Optimism

7
X-Propagation
Introduction

• Gate Simulations are a pain!

• Why do we bother?

Reason to run Alternative

Gate Simulations Approach
Synthesis Errors Equivalence Checking
Questionable RTL Style Lint Tools
Timing Verification Static Timing Tools
Power Analysis RTL Power Analysis
RTL X-Optimism

8
X-Propagation
Introduction

• Gate Simulations are a pain!

• Why do we bother?

Reason to run Alternative

Gate Simulations Approach
Synthesis Errors Equivalence Checking
Questionable RTL Style Lint Tools
Timing Verification Static Timing Tools
Power Analysis RTL Power Analysis
RTL X-Optimism
X-Propagation
Technology

9
X-Propagation
Outline

• Introduction
• Background
– Sources of X in RTL We are here !
– Ambiguous RTL Constructs
– Existing Solutions

• X-Propagation Technology
– Introduction
– T-Merge/X-Merge
– Results

• Conclusions

10
X-Propagation
Where do Xs Come From?
1. Uninitialized state
• Initially all DUT state is X Simulator

DUT
DUT
X X X
X
XXXXX
XXXXX XXXXXXX
X XX
XXXXXXX

Testbench

11
X-Propagation
Where do Xs Come From?
1. Uninitialized state
• Initially all DUT state is X Simulator
– Testbench applies RESET
DUT
DUT
X X X
X
XXXXX
XXXXX XXXXXXX
X XX
XXXXXXX

RESET

Testbench

12
X-Propagation
Where do Xs Come From?
1. Uninitialized state
• Initially all DUT state is X Simulator

– Asserting RESET clears critical DUT

DUT
state (state machines, control 0 0 1 1
logic) 00000
XXXXX XXXXXXX
– But X‟s remain (memories, XX
0
data-path) …. 0000000

– Circuit cost of exhaustive reset

is usually too high!
Testbench

13
X-Propagation
Where do Xs Come From?
2. Testbench drives X
• Good DV practice is to assign Simulator
X to input signals that
should not be consumed: DUT
DUT

IDLE

Test-bench

14
X-Propagation
Where do Xs Come From?
2. Testbench drives X
• Good DV practice is to assign Simulator
X to input signals that
should not be consumed: DUT
DUT
task pkt_driver::drive_idle();
pkt_bus.valid <= ‘b0; VALID = ‘b0
pkt_bus.sop <= ‘bx; SOP, EOP = ‘bX
DATA = ‘bX
pkt_bus.eop <= ‘bx;
pkt_bus.data <= ‘bx;
endtask IDLE

• Design should work fine Test-bench

regardless of actual values

15
X-Propagation
Where do Xs Come From?
3. RTL Drives Xs
• Designers express : Simulator

Output Don’t Care Condition DUT

DUT

DC_OUTPUT <= ‘bx

• Allows synthesis tool freedom
to optimize logic

Test-bench

16
X-Propagation
Where do Xs Come From?
4. Models Drive X on Errors
• A simulation model can drive Simulator
X as the response to an
invalid transaction DUT
DUT
• Real system behaviour is
unknown
‘bXXXXX

Protocol Error
Violation Response

Simulation
Model

17
X-Propagation
Where do Xs Come From?
Summary
Source Timeline
Uninitialized State Start of simulation
Testbench Any time
RTL Output Don‟t Care Any time
Simulation Model Any time

Note : Xs are not only an issue at start of simulation!

18
X-Propagation
Outline

• Introduction
• Background
– Sources of X in RTL
– Ambiguous RTL Constructs We are here !
– Existing Solutions

• X-Propagation Technology
– Introduction
– T-Merge/X-Merge
– Results

• Conclusions

19
X-Propagation
Normal RTL X Semantics

• X represents a „0‟ OR „1‟

• Normal RTL simulation can only explore one of these

possibilities

RTL X-Optimism

Circuit appears to work in RTL simulation.

Actual circuit does not work !! -> RESPIN!!

20
X-Propagation
Ambiguous RTL Constructs (1)
IF/ELSE
reg state;

#define INIT_STATE 0 Designer forgot

#define RUN_STATE 1 a reset

always @( posedge clock )

if ( state == `RUN_STATE ) begin
. . .
else
state <= `INIT_STATE; Predicate
evaluates to X

IN SIMULATION
ELSE branch executes
and flushes X

21
X-Propagation
Ambiguous RTL Constructs (1)
IF/ELSE

IEEE 1800-2009
If the cond_predicate expression evaluates to
true (that is, has a nonzero known value), the
first statement shall be executed. If it
evaluates to false (that is, has a zero value
or the value is x or z), the first statement
shall not execute. If there is an else
statement and the cond_predicate
expression is false, the else statement
shall be executed.

22
X-Propagation
Ambiguous RTL Constructs (2)
CASE Statements
• The issue of optimistic X propagation through CASE
statements in RTL is very similar to IF/ELSE
statements

23
X-Propagation
 Ambiguous RTL Constructs (3)
AMBIGUOUS EDGES

Actual clock could be a flat-line! Believe it or not

this is a valid
posedge !!

24
X-Propagation
Ambiguous RTL Constructs (3)
AMBIGUOUS EDGES

IEEE 1800-2009
A negedge shall be detected on the transition
from 1 to x, z, or 0, and
from x or z to 0.

A posedge shall be detected on the transition

from 0 to x, z, or 1, and
from x or z to 1.

25
X-Propagation
Ambiguous RTL Constructs (4)
BIT SELECTS
reg [3:0] index;

always @( posedge clock )

vector[index] <= 1’b0;

IN SIMULATION
If index is X, no
assignment takes place

26
X-Propagation
Ambiguous RTL Constructs (4)
BIT SELECTS

IEEE 1800-2009
Writing to an array with an invalid index
shall perform no operation.

Implementations may issue a warning if an

invalid index occurs for a read or write
operation of an array.

27
X-Propagation
Outline

• Introduction
• Background
– Sources of X in RTL
– Ambiguous RTL Constructs
– Existing Solutions We are here !

• X-Propagation Technology
– Introduction
– T-Merge/X-Merge
– Results

• Conclusions

28
X-Propagation
Existing Solutions

• RTL X-Optimism is not a new problem

• Common solutions

Solutions
Gate Level Simulation
RTL Coding Guidelines
Static X Randomization
Dynamic X Randomization
X-Propagation Technology

29
X-Propagation
Existing Solutions (1)
Gate Level Simulation

• Slow and labour intensive

– Reverse engineering of gate net-list is painful
– Slow simulation results in long debug cycle
– Large wave files. Scoping to manage file size
– Pessimistic results due to reconvergent logic paths

30
X-Propagation
Existing Solutions (1)
Gate Level Simulation

0
0
A=1 D=1
1
1
When A=1,
D=1

Reconvergent logic paths have pessimistic

simulation semantics at gate-level (X-Pessimism)
31
X-Propagation
Existing Solutions (1)
Gate Level Simulation

1
1
A=0 D=1
0
0
When A=0,
still D=1

Reconvergent logic paths have pessimistic

simulation semantics at gate-level (X-Pessimism)
32
X-Propagation
Existing Solutions (1)
Gate Level Simulation
But in gate
simulation,
D will go X
X
X
A=X D=X
X
X

Reconvergent logic paths have pessimistic

simulation semantics at gate-level (X-Pessimism)
33
X-Propagation
 Existing Solutions (1)
Gate Level Simulation
Selectively force nodes to known initial begin
(random) value to flush Xs. Must #5000;
resolve each case of reconvergent force dut.U3342.Q=$random;
logic simulation pessimism.
force dut.U195.Q=$random;
. . .
#10;
release dut.U3342.Q;
release dut.U195.Q;
. . .
end

• Tedious but robust !!

34
X-Propagation
Existing Solutions (2)
RTL Coding Guidelines

• Can we just write RTL that

avoids the problematic
constructs ???

35
X-Propagation
Existing Solutions (2)
RTL Coding Guidelines

• Can we just write RTL that

avoids the problematic
constructs ???

Construct Rule
IF / ELSE Replace with ternary operator ? :
CASE Default always assigns Xs to outputs
RTL X Assignment Don‟t optimize output D.C. conditions
Ambiguous Edges
No specific coding guideline
Bit Selects

36
X-Propagation
 Existing Solutions (2)
RTL Coding Guidelines

External IP Internal IP
Components Components

Legacy
Designs
New Design

• SoCs have RTL from many sources

• Difficult to enforce RTL coding guidelines with large teams
37
X-Propagation
 Existing Solutions (3)
Static X Randomization
Simulator

DUT
DUT
PLI 0 1 1
Initial: 0
00000
IF (node===X) THEN
XXXXX XXXXXXX
node = RAND();
0 XX
0000000

• At start of simulation, randomly

replace Xs with 0s or 1s

Test-bench

38
X-Propagation
 Existing Solutions (3)
Static X Randomization
Simulator

DUT
DUT
PLI 0 1 1
Initial: 0
00000
IF (node===X) THEN
00110 0110001
node = RAND();
0 01
0000000
• At start of simulation, randomly
replace Xs with 0s or 1s

Test-bench

39
X-Propagation
 Existing Solutions (3)
Static X Randomization
Simulator

DUT
DUT
PLI 0 1 1
Initial: 0
00000
IF (node===X) THEN
00110 0110001
node = RAND();
0 01
XXXXXX
• At start of simulation, randomly Protocol Error
replace Xs with 0s or 1s Violation Response

Test-bench
Testbench and RTL
! can re-introduce Xs!

40
X-Propagation
Existing Solutions (4)
Dynamic X Randomization
Simulator

DUT
DUT
PLI 0 1 1
0
Every clock: 00000
IF (node===X) THEN 00110 0110001
node = RAND(); 01
0
XXXXXX

Every clock cycle, randomly

replace Xs with 0s or 1s
Test-bench

41
X-Propagation
Existing Solutions (4)
Dynamic X Randomization
Simulator

DUT
DUT
PLI 0 1 1
0
Every clock: 00000
IF (node===X) THEN 00110 0110001
node = RAND(); 01
0
XXXXXX

Every clock cycle, randomly

replace Xs with 0s or 1s
Test-bench
Slows down simulation.
Observed ≈60% slow down

42
X-Propagation
 Existing Solutions (3,4)
Randomization Solutions

N state elements

2N possible initial states!!

Randomization techniques cover only a

subset of possible state space

43
X-Propagation
Existing Approaches

Solutions Issues
Gate Level Simulation Slow. Pessimistic
Labour intensive
RTL Coding Guidelines Partial solution
Difficult to enforce
Static X Randomization Partial solution
Limited state coverage
Dynamic X Randomization Slow
Limited state coverage

X-propagation offers a better approach!

44
X-Propagation
Outline

• Introduction
• Background
– Sources of X in RTL
– Ambiguous RTL Constructs
– Existing Solutions

• X-Propagation Technology
– Introduction We are here !
– T-Merge/X-Merge
– Results

• Conclusions

45
X-Propagation
What is X-Propagation?

• Advanced simulation technology that changes

conventional simulation semantics
– Xs propagate through IF/ELSE, CASE statements
– Behaviour of ambiguous edges is modeled
– Problems with vector indices are detected
• No changes required to RTL coding style

46
X-Propagation
What is X-Propagation?

• Advanced simulation technology

– Changes the RTL simulation semantics
– Xs propagate through IF/ELSE, CASE statements
if (select)
out <= 1’b0; select===1’bX
else
out <= 1’b1;

IEEE 1800-2009
X-Propagation Semantics
Semantics
out <= 1’b1; out <= 1’bx;

X is masked. Correct.
Optimistic Still at RTL
behaviour X-Propagation
47
T-Merge and X-Merge

• X-Propagation evaluates both/all branches

• The possible output values are merged:

if (select) select a b T-Merge X-Merge

out <= a; X 0 0 0 X
else X 0 1 X X
out <= b; X 1 0 X X
X 1 1 1 X

48
X-Propagation
T-Merge and X-Merge

• X-Propagation evaluates both/all branches

• The possible output values are merged:

if (select) select a b T-Merge X-Merge

out <= a; X 0 0 0 X
else X 0 1 X X
out <= b; X 1 0 X X
X 1 1 1 X

Mode Behaviour
T-Merge Only yields X if branches diverge
X-Merge Always yields X if selector is X

49
X-Propagation
Sequentials
Clean and Maybe Edges
• Clean posedge : 01
• Maybe posedge : 0X, 0Z, X1, Z1

50
X-Propagation
 Sequentials
Clean and Maybe Edges
• Clean posedge : 01
• Maybe posedge : 0X, 0Z, X1, Z1

merge
function
new previous
value value

maybe
posedge

• On occurrence of maybe posedge

Merge function is applied to new and previous values
51
X-Propagation
Invoking X-Propagation

vcs –xprop design.v

Configuration file enables:

 Selective enabling on a module/hierarchy basis

 Selection between T-merge and X-Merge

52
X-Propagation
Invoking X-Propagation

vcs –xprop design.v

And this solves all the

simulation issues and
they lived happily ever after

53
X-Propagation
Invoking X-Propagation

vcs –xprop design.v

And this solves all the

simulation issues and
they lived happily ever after

Not quite ….

54
X-Propagation
Invoking X-Propagation

• Generally enabling X-propagation in a complex

simulation environment will result
in simulation failures:

– Some due to simulation modeling issues

– Some due to potential bugs

55
X-Propagation
Outline

• Introduction
• Background
– Sources of X in RTL
– Ambiguous RTL Constructs
– Existing Solutions

• X-Propagation Technology
– Introduction
– T-Merge/X-Merge
– Results We are here !

• Conclusions

56
X-Propagation
Experience with X-Propagation

• Applied to large sub-system (370K flops) in the

Layer 2 section of a recent ASIC
• Ran with VCS 2011.03-03
Plain RTL Semantics X-Prop Semantics
Memory Sim Speed Memory Sim Speed
Usage (MB) (ns/sec) Usage (ns/sec)
85.6 127 88 87

• 30% simulation speed slowdown

57
X-Propagation
Experience with VCS X-Prop

• Applied to large sub-system (370K flops) in the

Layer 2 section of a recent ASIC
• Ran with VCS 2011.03-03
Plain RTL Semantics X-Prop Semantics
Memory Sim Speed Memory Sim Speed
Usage (MB) (ns/sec) Usage (ns/sec)
85.6 127 88 87

• 30% simulation speed slowdown

• Found 2 false negatives
• Found 2 verification “bugs”
• Made 2 preventive RTL changes
58
X-Propagation
T-Merge versus X-Merge
• We initially used T-Merge
• Resolved issues

• Then enabled X-Merge

• No additional issues found

• Generally X-Merge is not necessary

Mode Behaviour
T-Merge Only yields X if branches diverge
X-Merge Always yields X if selector is X

59
X-Propagation
False Negatives (1)
Multi-Cycle Reconvergence
• X-Prop changes semantics of combinatorial logic
• Reconvergence issues remain across clocks
• One issue of this nature was found in our design

60
X-Propagation
False Negatives (1)
Multi-Cycle Reconvergence
• X-Prop changes semantics of combinatorial logic
• Reconvergence issues remain across clocks
• One issue of this nature was found in our design

• Was resolved with force/release

61
X-Propagation
False Negatives (2)
Pessimistic Edges
• Modelling of flop with async reset:
always @( posedge clk or negedge resetN ) begin
if ( !resetN )
q <= 1’b0;
. . .

• DV environment drove X0 transition on resetN

• Considered ambiguous by X-Prop (incorrectly)

62
X-Propagation
False Negatives (2)
Pessimistic Edges
• Modelling of flop with async reset:
always @( posedge clk or negedge resetN ) begin
if ( !resetN )
q <= 1’b0;
. . .

• DV environment drove X0 transition on resetN

• Considered ambiguous by X-Prop (incorrectly)

• DV Changed to 10 transition on resetN

63
X-Propagation
DV Bug (1)
Assertion Qualification
mem_A_decoded = 1’b0;
mem_B_decoded = 1’b0;

casez (address)
8’b0??????? : mem_A_decoded = 1’b1;
8’b1??????? : mem_B_decoded = 1’b1;
endcase

assert zero_one_hot( .test_expr{ mem_A_decoded,

mem_B_decoded } );

• ZERO_ONE_HOT assertion on decode signals

64
X-Propagation
DV Bug (1)
Assertion Qualification
mem_A_decoded = 1’b0;
mem_B_decoded = 1’b0;
8’bxxxxxxx
casez (address)
8’b0??????? : mem_A_decoded = 1’b1;
8’b1??????? : mem_B_decoded = 1’b1;
endcase
mem_A_decoded = 1’b0; mem_B_decoded = 1’b0;
assert zero_one_hot( .test_expr{ mem_A_decoded,
mem_B_decoded } );

• In “classic” RTL, mem_decoded signals stay 0 when

address is X
• Assertion did not fire
65
X-Propagation
DV Bug (1)
Assertion Qualification
mem_A_decoded = 1’b0;
mem_B_decoded = 1’b0;
8’bxxxxxxx
casez (address)
8’b0??????? : mem_A_decoded = 1’b1;
8’b1??????? : mem_B_decoded = 1’b1;
endcase
mem_A_decoded = 1’bX; mem_B_decoded = 1’bX;
assert zero_one_hot( .test_expr{ mem_A_decoded,
mem_B_decoded } );

• In “X-Prop” RTL, mem_decoded signals go X when

address is X
• Assertion started firing with X-Prop
66
X-Propagation
DV Bug (1)
Assertion Qualification
mem_A_decoded = 1’b0;
mem_B_decoded = 1’b0;

casez (address)
8’b0??????? : mem_A_decoded = 1’b1;
8’b1??????? : mem_B_decoded = 1’b1;
endcase

assert zero_one_hot( .test_expr{ mem_A_decoded,

mem_B_decoded } );

• Qualify assertion with CPU access:

( cpu_read || cpu_write)

67
X-Propagation
DV Bug (2)
Incorrect Reset Modeling

Memory BIST
with
IF/ELSE construct

assign bist_reset = 1’b0;

Before

• BIST controller needed a negedge on reset

• DV had incorrectly tied reset to 1‟b0

68
X-Propagation
DV Bug (2)
Incorrect Reset Modeling

Memory BIST Memory BIST

with with
IF/ELSE construct IF/ELSE construct

assign bist_reset = 1’b0; bist_reset <= 1’b1;

@(posedge clk)
bist_reset <= 1’b0;
Before After

• BIST controller needed a negedge on reset

• DV had incorrectly tied reset to 1‟b0
• Solution was to update testbench

69
X-Propagation
Summary of Findings

Observation Number
False Negative : Multi-Cycle Reconvergence 1
False Negative : Pessimistic Handling of Edges 1
DV Bug : Assertion Qualification 1
DV Bug : Reset Modelling 1
Minor RTL Changes : Additional Resets 2

• It took time to resolve false negatives and DV bugs

• Two RTL changes made to make circuit more robust
• Overall, less effort and faster than gate simulation

70
X-Propagation
Outline

• Introduction
• Background
– Sources of X in RTL
– Ambiguous RTL Constructs
– Existing Solutions

• X-Propagation Technology
– Introduction
– T-Merge/X-Merge
– Results

• Conclusions We are here !

71
X-Propagation
Issues with Gate Simulation

• Starts late in verification cycle

• Long simulation times (often 10x slower vs. RTL)
• Intrinsic X-Pessimism on reconvergent paths

72
X-Propagation
Proposed RTL X-Prop Methodology

• Enable X-Prop early

– Resolve issues (false negatives, DV bugs)
• Regress with X-Prop prior to tape-out

73
X-Propagation
Proposed Future Work

• Multi-cycle reconvergence
– Can these be identified using formal or symbolic
simulation techniques?

• Standardization
– X-Prop Verilog semantics should be standardized
– Avoid divergence between different tools

74
X-Propagation
Comparison of Techniques
Simulation Style Accuracy of Human Effort Simulation
X Modelling to Debug Speed
“Plain” RTL Semantics Optimistic Low Fastest
Gate Simulation Statistical Medium Slow
with X Randomization
Gate Simulation Pessimistic High Slow
without X Randomization
RTL X-Propagation Slightly Medium Fast
Pessimistic

• X-Propagation provides a good trade-off

• Fast simulation
• Slightly pessimistic semantics
• Easy to debug

75
X-Propagation
Conclusions

• Using X-Propagation, RTL X-optimism issues can be

resolved earlier in the verification cycle

• Less effort and faster than gate simulation

– Achieves similar level of confidence

• Debug effort still required to investigate failures

76
X-Propagation
Acknowledgements

– Co-authors at Cisco
• Craig Forward, Julius Yam

– Technical leadership and management team - Cisco

• Eric Chesters, Shailesh Sutarwala, Tom Ponleithner,

– Technical Team at Synopsys for tool support

• Benjamin Chin, Jason Chen, Arturo Salz, Amar Amaresan

– SNUG Team for reviews and dry-runs

• Jean Fong, Leah Clark, Tammy Ross

77
X-Propagation
Thank You!

• Questions?

78
X-Propagation
Backup Slides

79
X-Propagation
Where do Xs Come From?
3. RTL Drives Xs
case (instruction)
`ADD : begin Simulator
alu_in1 <= add_op1;
alu_in2 <= add_op2; DUT
DUT
end
`SUB : begin
alu_in1 <= sub_op1; DC_OUTPUT <= ‘bx
alu_in2 <= sub_op2;
end
`NOOP : begin
alu_in1 <= ‘bx;
alu_in2 <= ‘bx;
end
endcase // instruction Test-bench

Appears to require 3:1 input mux in RTL.

80
X-Propagation
Where do Xs Come From?
3. RTL Drives Xs

Simulator
add_op1
0
DUT
DUT
sub_op1
1
DC_OUTPUT <= ‘bx

instruction == `SUB

Synthesis tool can optimize to a 2:1 mux

because inputs don’t matter for NOOP
Test-bench

81
X-Propagation
Ambiguous RTL Constructs (2)
CASE STATEMENTS
reg state;

#define INIT_STATE 0 Designer forgot

#define RUN_STATE 1 a reset

always @( posedge clock )

case ( state ) case_expression
`INIT_STATE : state <= . . . evaluates to X
`RUN_STATE : state <= . . .
default : state <= `INIT_STATE;
endcase
IN SIMULATION
default branch
executes and
flushes X

82
X-Propagation
Ambiguous RTL Constructs (2)
CASE STATEMENTS

IEEE 1800-2009
In a case_expression comparison, the
comparison only succeeds when each bit
matches exactly with respect to the values
0, 1, x, and z. As a consequence, care is
needed in specifying the expressions in the
case statement.

83
X-Propagation