Altera Quartus II Software v10.0 — Subscription Edition vs.

Web Edition
Categories Features Web Edition Software Subscription Edition Software
Getting started Download (www.altera.com/download) and DVD (www.altera.com/dvdrequest)
Windows: Vista (32 bit), XP (32 bit), 7 (32 bit) Windows: Vista (32/64 bit), XP (32/64 bit), 7 (32/64 bit)
General
Linux: SUSE Linux Enterprise 10 and 11 (32 bit), Linux: SUSE Linux Enterprise 10 and 11 (32/64 bit),
Information OS support
Red Hat Enterprise Linux 4 and 5 (32 bit) Red Hat Enterprise Linux 4 and 5 (32/64 bit)
CentOS 4 and 5 (32 bit) CentOS 4 and 5 (32/64 bit)
CPLD MAX® series devices: All MAX series devices: All
Low-cost FPGAs Cyclone® series devices: All Cyclone series devices: All
Arria® GX FPGAs: All Arria GX FPGAs: All
Mid-range FPGAs
Arria II GX FPGAs: EP2AGX45, EP2AGX65 Arria II GX FPGAs: All
Device Stratix V/V GX/V GS FPGAs: All
Support Stratix® IV/IV GX FPGAs: None
Stratix IV/IV GX/IV GT FPGAs: All
Stratix III FPGAs: EP3SE50, EP3SL70, EP3SL50
High-end FPGAs Stratix III FPGAs: All
Stratix II/II GX FPGAs: EP2S15, EP2SGX30
Stratix II / II GX FPGAs: All
Stratix FPGAs: EP1S10
Stratix / GX FPGAs: All
ASIC No HardCopy® series: All
®
Altera and partner IP Yes, including free OpenCore Plus evaluation feature
IP DSP: FIR, FFT, and NCO compilers
Full-license IP Base Suite IP available for purchase Interfaces: SerialLite II
Memory controllers: DDR1/2/3, QDR II, RLDRAM II
SOPC Builder Yes
Design Entry
Schematic entry and language support Schematic entry, Verilog, VHDL, and SystemVerilog
Design Tcl scripting , command line support Yes
Environment
Incremental compilation and team-based design No Yes
LogicLock™ No Yes
Multiprocessor support No Yes
Rapid Recompile No Yes
Physical synthesis optimizations Yes
Implementation Chip planner Yes
and
Optimization Live I/O checking Yes
Timing-driven placement Yes
TimeQuest timing analyzer and optimization advisor Yes
Synopsys design constraint (SDC) format support Yes
Early power estimator Available to download on www.altera.com for no cost
PowerPlay power analysis and optimization Yes
SignalTap™ II logic analyzer Available with TalkBack enabled Yes
SignalProbe feature Available with TalkBack enabled Yes
Transceiver toolkit No Yes
Verification ModelSim®-Altera Starter Edition Included
and Debug ModelSim - Altera Edition Sold as an option for $945
Embedded logic analyzer interface Yes
RTL viewer and technology map viewer Yes
Pin planner Yes
System Design Nios II Embedded Design Suite Free for both versions of Quartus® II software
Software DSP Builder Sold as an option for both versions of Quartus II software
Third-Party EDA partners Altera offers third-party support for synthesis, functional and timing simulation, static timing analysis,
Support board-level simulation, signal integrity (SI) analysis, and formal verification

Copyright © 2010 Altera Corporation. All rights reserved. Altera, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or
service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their
respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights. PDF; July 2010