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DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

Question Bank

Subject: Digital Communications

Regulation: R16
III Year – I SEMESTER

UNIT I: PULSE DIGITAL MODULATION

1 a) Explain delta modulation in detail with suitable diagram. [10M]
b) Given a sine wave of frequency fm and amplitude Am applied to a delta
modulator having step size _. Find the condition on Am for which slope overload
distortion will occur

2 a) Draw the block diagram of ADM system? Explain each block.

b) What are the noises in PCM? Derive an expression for quantization in noise in
PCM.
3 a) Explain quantization error and derive an expression for maximum SNR in PCM
system that uses Linear quantization.
b ) In a binary PCM system, the output signal to quantizing noise ratio is to be
held to a minimum value of 40dB. Determine the number of levels and find the
corresponding signal to quantizing noise ratio.
4 a) A Television signal having a bandwidth of 10.2 MHz is transmitted using
binary PCM system. Given that number of quantization levels is 512.Determine:
(i)Code Word length (ii) Transmission Bandwidth (iii) Final bit rate (iv) Output
signal to quantization noise ratio
b) What is slope overload and granular noise distortions are removed in ADM?
Explain
5 a) What is the necessity of non-uniform quantization and explain companding.
[10M]
b) If mp = 20V and 256 quantizing levels are employed, what is the voltage
between levels when there is no
compression? For μ = 255, what is the smallest and what is the largest effective
separation between levels?

6 a) Discuss in detail the noise effects in delta modulation

b) Briefly list out the differences between PCM and DM.
UNIT II: DIGITAL MODULATION TECHNIQUES
1 (a) Draw the block diagram of DPSK modulator and explain how
synchronization problem is avoided for its detection.
b) Write the power spectral density of BPSK and QPSK signals and draw the power
spectrum of each.
 2.(a)Explain the generation of M-ary ASK with a neat block
b) Explain the principle of QPSK system. Compare binary PSK and QPSK
schemes.

3 (a) Explain with neat block diagram the generation and recovery of BPSK
b) What are power spectra? Explain power spectra of BPSK and BFSK signals
along with graphs.

4.Determine the bandwidth required for M-ary FSK system. Draw the geometrical
representation of M-ary FSK signals and find out the distance between the sign
b) Sketch the QPSK waveform for the sequence 1101010010, assuming the
carrier frequency equal to bit rate.

5.(a)Discuss the ASK system in detail

b)Draw the block diagram of the DPSK modulator. Explain how the
synchronization problem is avoided in
this.

UNIT III: DATA TRANSMISSION

1.a) Explain about ASK system and derive the relation for error probability of
binary ASK.

b) A binary receiver system receives a bit rate of 1Mbps. The waveform amplitude
is 5mV and the noise power spectral density is 0.5x10-11 W/Hz.
Calculate the average bit error probability if the modulation schemes are ASK,
FSK and PSK.

2. a) Draw and explain the coherent system of signal reception. [10M]

b) Binary data is transmitted over a telephone line with usable bandwidth of 2400
Hz using the FSK
signaling scheme. The transmit frequencies are 2025 and 2225 Hz, and the data rate
is 300 bits/Sec. The average signal to noise power ratio at the output of the channel
is 6dB. Calculate Pe for the coherent and non coherent demodulation schemes..
 3.a) Explain about coherent binary PSK transmitter and receiver. Assuming
channel noise to be additive white Gaussian obtain expression for probability of
error.

b) Calculate the transfer function of the

Optimum filter. 4.(a)What is correlator
(b) Explain the optimum filter reception using correlator.
5(a)What is a matched filter? How it differs from a optimum filter.
(b)Derive an expression for impulse response of the matched filter.
6.Explain how integrator is used to detect the baseband signal. Obtain an
expression for S/N of integrator and dump receiver.
UNIT IV: INFORMATION THEORY
1. a). Define entropy.
 b). A source x generates four messages mo,m1, m2, m4 with probabilities 1/3,
1/6, 1/4, ¼ respectively. The successive messages emitted by the source are
statistically independent. Calculate entropy of the source X.

2. a) Define and explain the following. i) Information ii) Efficiency of coding iii)
Redundancy of coding.
b) Prove that H(X,Y) = H(X) + H(Y/X) = H(Y) + H(X/Y).

3. a) State and prove the condition for entropy to be maximum.

b) Prove that H(Y/X) ≤ H(Y) with equality if and only if X and Y are
independent.
4.(a) What is mutual information? State and prove the properties of it.
(b) If I(x1) is the information carried by symbol x1 and I(x2) id the information
carried by symbol x2 then prove that the amount of information carried compositely
due to x1and x2 is I(x1, x2)= I(x1) I(x2)

5 An analog signal band limited to 10HKz quantize is 8-lavels of PCM System

with probability of 1/4,1/5,1/4,1/10,1/20,1/10,1/20 and 1/10 respectively. Find
the entropy and rate of information.

6 a) Explain the concept of amount of information. [8M]

b)An analog signal is band limited to B Hz, sampled at the nyquist rate, and the
samples are quantized
into 4 levels. The quantization levels Q1, Q2, Q3 and Q4 (messages) are assumed
independent and occur with probabilities p1= p4=1/8 and p2= p3=3/8. Find the
information rate of the source.

UNIT V :SOURCE CODING

1 Explain the Huffman coding technique with example.

2a) Explain procedure of Shannon-fano coding and Huffman coding. b) A discrete

memory less source X has 5
symbols x1, x2 x3, x4 & x5 with P(x1)=0.4, P(x2)=0.19, P(x3)=0.16, P(x4)=0.15 &
p(x5)=0.1. (i) Construct a

Shannon-fano code for X, and calculate the efficiency of the code. (ii) Repeat for
the Huffman code and compare the results.

3 (a)Discuss the channel capacity for discrete and analog channels.

 (b)Apply Shannon Fano coding for the 5 messages with probabilities 0.4, 0.15,
0.15, 0.15, 0.15 and find the coding efficiency.

4.What is binary symmetric channel and derive expression for its capacity.

5.A discrete memory less source has an alphabet of seven symbols with probability
for its output, as described here:
Symb prob
ol .
S₀ 0.25
S₁ 0.25
S₂ 0.125
0.12
S₃ 5
0.12
S₄ 5
0.06
S₅ 25
0.062
S₆ 5
(i) Compute the Huffman code for this source and explain why the compute
source code has an efficiency of 100 percent. (ii) Calculate H
 UNIT VI :LINEAR BLOCK CODES&CONVOLUTION CODES

1.Define the linear block codes and explain matrix description of a linear block
codes.
( b) The generator matrix for a (6, 3) block code is given below. Find all code
vectors of this code. G= [ I : P]; where P= [ 0 1 1; 1 0 1; 1 1 0], & I = Identity
Matrix.

2.a) Explain the advantages and disadvantages of cyclic codes.

b)Construct the (7, 4) linear code word for the generator polynomial G(D) =
1+D2+D3 for the message bits 1001 and find the checksum for the same.

3.a) Explain the principle and operation of encoder for Hamming code.
b)An error control code has the following parity check matrix. H = [1 0 1 1 0 0; 1 1
0 0 1 0; 0 1 1 0 0 1] i)
Determine the generator matrix ‘G’ ii) Decode the received code word 110110.
Comment on error detection capability of this code.

4.A) State and explain the properties of cyclic codes.

b)The generator polynomial of a (7, 4) cyclic code is x3+x+1. Construct the
generator matrix for a systematic cyclic code and find the code word for the
message (1101) using the generated matrix.

5.a) Briefly describe the Viterbi algorithm for maximum-likelihood decoding of

convolutional codes.
b) For the convolutional encoder shown in figure 1, draw the state diagram and the
trellis diagram.

6 (a) What are code tree, trellis and state diagrams for a convolutional encoder?
(b) Draw the trellis diagram of a Convolutional code of code rate r=1/2 and
Constraint length of K=3 starting from the state table and state diagram for an
encoder which is commonly used.
Jntufastresult.com

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING
DIGITAL IC APPLICATIONS

Academic Year : 2018-2019

Year/Semester

: III YEAR– I SEMESTER

Regulation : R16
Subject : DIGITAL IC APPLICATIONS

UNIT 1 - Digital Logic Families and Interfacing

1. (a) Discuss the behaviour of a CMOS as an inverter.i) Inductive effects ii)
Propagation delay[5M]
(b) What are features of TTL logic family? Discuss about the fastest
logic family and mention the typical values of its various
parameters.[5M]
2. (a)Draw the circuit diagram of basic TTL NAND gate and explain
with the help of functional operation.[5M]
(b) What are the advantages and disadvantages of ECL gates?
Draw and explain the 2-input OR/NOR gate using ECL logic.[5M]
3. (a)Explain dynamic electrical behavior of a CMOS. [5M]
(b) Design a 4 input CMOS AND-OR-INVERT gate. Explain the
circuit with the help of logic diagram and function table.[5M]
4. (a) Explain the CMOS circuit behavior with resistive load. [5M]
(b) Describe the key benefit of schottky transistors in TTL. [3M]
(c ) Explain about CMOS steady state electrical behavior. [2M]
5. (a) Explain about CMOS/TTL interfacing.[5M]
(b) Draw a two input 10K ECL OR gate and verify the truth table. [5M]
6. (a) Explain the circuit behavior of CMOS with non ideal outputs. [5M]
(b) Design 2-input LS-TTL NAND gate and explain its operation.
Give the function table, truth table.[5M]
7. (a) Compare CMOS, TTL and ECL with reference to logic levels, DC
noise margin, propagation delay and fan-out.[8M]
(b) Write about the totem pole arrangement in case of TTL family. [8M]
8. (a) Differentiate between the TTL and DTL logic families.[4M]
(b) Discuss about dynamic electrical behavior. [4 M]
(c) Draw the schematic diagram of a tri-state buffer and explain its
operation. [2M]
UNIT-II- Introduction to VHDL
1. (a) What are the different data objects supported by VHDL? Explain scalar
types with suitable examples.[5M]
 (b) Write a VHDL Entity and Architecture for the following
function.F = a (XOR) b (XOR)c, Also draw the relevant logic diagram.[5M]
2. (a) Write short note on package declaration. [2M]
(b) Write a syntax of VHDL array declaration. [2M]
(c)What statement is primarily used to describe a design in dataflow style?
Explain about dataflow design elements of VHDL. [6M]
3. (a) What is the purpose of the ‘timescale’ compiler derivative? Give an
example. [6 M]
(b) Write a short note on Elements of VHDL. [2M]
(c)Write short notes on sub programs.[2M]
4. What is the use of packages and libraries in VHDL? Explain with
examples.[10M]
5. (a) Explain the terms entity, is, port, in, out and end pertaining to VHDL
complier.Write a VHDL program using all the above terms and explain the
same.[5M]
(b) Write the features VHDL. [3M]
(c)What are the comparison of VHDL and Verilog HDL[2M]
6. (a) Write VHDL Code of 8 x 1Mux using data flow. [5M]
(b) Write a VHDL code for a 4 bit counter using behavioral
modeling.[5M]
7. (a)Explain about Levels of Abstraction. [2M]
(b)Write a VHDL code for a full adder using two half adders in structural
modeling. [6M]
(c)Brief the objects in VHDL.[2M]
UNIT-III- Behavioral Modeling
1. (a) With Example explain Process statement, variable assignment
statement, signal assignment statement [6M]
(b) Explain Transport Delay Model [4M]
2. (a) With Example explain wait statement and if statement [4M]
(b) Write a short note on signal drivers [3M]
(c) With Example explain case statement [3M]
3. (a) With Example explain null statement, loop statement, exit statement,
next statement ,assertion Statement [6M]
(b) Explain Multiple Processes concept with example. [4M]
4. (a) Explain Inertial Delay Model [5M]
(b) Explain Other Sequential Statements [5M]
5. (a) How to Create Signal Waveforms [5M]
6. (a) Explain Logic Synthesis [5M]
(b) Write a short note on Inside a logic Synthesizer. [5M]
 UNIT-IV-Combinational Logic Design
1. (a) Write a VHDL code for a 4 bit up counter [4M]
(b) Draw the truth table and circuit diagram of a 2-to-4 decoder. [4M]
(c)Discuss about the implementation of comparator using digital IC. [8M]
2. (a) Explain about the Dual Priority Encoder with neat diagram.[8M]
(b) Write a VHDL code to simulate a full adder circuit. [4M]
(c)What is a floating point encoder? explain [4M]
3. (a) Design a full adder using two half adders. Write its structural code. [4M]
(b) Design the logic circuit and write a data-flow style VHDL program
for the following functions
F(X) = ΣA,B,C,D(0,1,3,5,14) + d(8,15) [8M]
4. (a) Write a data-flow style VHDL program for 4:1 MUX.[3 M]
(b) Explain the working of carry look ahead adder and its
advantages.[7 M]
5. (a) Design a 8bit ALU using two 74LS181 ICs.[8 M]
 (b) Write VHDL code for half subtractor using structural modeling. [2
M]
6. (a) Write a VHDL program for8X3 encoder. [2 M]
(b) Write VHDL code for 16 bit barrel shift. [3M]
(c)Implement the 32 input to 5 output priority encoder using four 74LS148
gates. [5M]
UNIT-V-Sequential Logic Design
1. (a) Write a VHDL program to design a modulo-8 counter. [5M]
(b) Write a VHDL program to simulate the behaviour of a
positive edge triggered J-K flip – flop.[5M]
2. (a) Explain in detail about the working of Johnson Counter using 74 LS194.
[5M]
(b) Discuss the logic circuit of 74×377 register. Write a VHDL
program for the same in structural style.[5M]
3. (a) Write a VHDL code for a 4 bit down counter. [2M]
(b) Design a 8 bit parallel-in and serial-out shift register. Explain
the operation of the above shift register with the help of timing
waveforms.[5M]
(c)Write a VHDL code for Ring counter. [3M]
4. (a) Design, explain and write VHDL code for Universal Shift Register. [8
M]
(b) Write VHDL code for T Flip Flop with asynchronous reset using
behavioural modelling.[2M]
5. (a) Design a 3 bit LFSR with an initial state of 6. [8M]
(b) Design a modulo 11 counter using 74x163. [8M]
6. (a) Write the differences between flip-flop and latch. [2M]
(b) Design a self-correcting 4-bit, 4-state ring counter with a
single circulating 0 using IC 74LS194.[5M]
(c)Explain the different Modes of Operation of Shift Registers. [3M]
7. (a) Design a 4 bit synchronous binary even counter and write its
behavioural model. [5M]
(b) Discuss the steps involved in the analysis of sequential circuits.
[2M]
(c)Write a VHDL program to simulate the behavior of a positive edge
triggered ‘D’flip – flop.[3M]
UNIT-VI- Synchronous and Asynchronous Sequential
Circuits
1. (a)Draw state diagrams of a sequence detector which can detect 011 [3M]
(b) Distinguish between Moore and Mealy Machines.[2M]
(c ) The output Z of a fundamental mode, two input sequential circuit is to
change from 0 to 1 only when x2 changes from 0 to 1 while x1=1. The
output changes from 1 to 0 only when x1 changes from 1 to 0 while x2=1.
Find a minimum row reduced flow table [6M]
2. (a) Draw the diagram of Mealy type FSM for serial adder. [2M]
(b) Explain the procedure of Meelay to Moore conversion [2M]
(c ) A clocked sequential circuit is provided with a single input x and
single output z, whenever the input produces a string pulsed 111 or 000 and
at the end of the sequence it produces an output z=1 and overlapping is also
allowed. [6M]
i)Obtain state diagram and state table.
ii) Find equivalence classes using partition method and design the circuit
using D flip- flop.

3.(a)Draw the state diagram of mod-8 Up - Down counter in Moore model and
obtain its state table.
(b) Explain the procedure of Meelay to Moore conversion
(c ) A clock mode sequential circuit has to provide z=1 whenever the input
completes the Sequence of pulses 1010 and overlapping is allowed. Draw
the state diagram and obtain minimal state using partition method

4. (a)Explain about sequential circuits, state table

and state diagram. (b)Write capabilities and
limitations of Finite- State machine.
 (c)A sequential circuit has 2 inputs w1=w2 and an output z. It's function is
to compare the i/p sequence on the two i/p's. If w1=w2 during any four
consecutive clock cycles, the circuit produces, z
=1 otherwise z = 0, w1= 0110111000110, w2= 1110101000111,
z=0000100001110.

5. (a) Define the state equivalence and machine equivalence with

reference to sequential machines. (b)Derive a circuit that realizes the FSM
defined by the state assigned table below using JK flip flops

(or)
Convert the following Mealy machine into a corresponding Moore machine?
(10M)

6. A clocked sequential circuit is defined by the following state table:

a) Using implementation table obtain equivalence classes.
b) Design the circuit using D-flip-flop.

(or)
Find the equivalence partition and a corresponding reduced machine
in a standard form for a given machine
 .
7. Convert the following Mealy machine into a corresponding Moore
Machine.
Jntufastresult.com

QUESTION BANK
COMPUTER ACHITECTURE AND ORGANIZATION
Class – III ECE – I Sem
UNIT –I
-5
1) a) Explain the Functional unit of a computer M
-5
b) Explain the Basic Operational concepts of a Computer M
-5
2) a) Explain about Bus structures M
-5
b) Explain about the System Software. M
-5
3) a) How to calculate the Performance of a computer Explain. M
-5
b) Explain the history of computer development. M
-5
4) a) Explain the Functional unit of a computer M
-5
b) Explain about Bus structures M
-5
5) a) Explain about the System Software. M
-5
b) How to calculate the Performance of a computer Explain. M
UNIT
–II
-5
1) a) Explain about the Register Transfer Notation M
-5
b) Explain about Assembly Language Notation M
 -5
2) a) Explain the Basic Instruction Types M
-5
b) Explain the different Addressing Modes M
-5
3) a) Explain about Basic Input/output Operations M
b) Explain the role of Stacks and Queues in computer -5
programming equation M
-5
4) a) Explain about Logic Instructions M
-5
b) Explain about shift and Rotate Instructions M
-5
5) a) Explain the Basic Instruction Types M
b) Explain the role of Stacks and Queues in computer -5
programming equation M
UNIT
–III
1) a) Explain about Arithmetic -5
Instructions. M
-5
b) Explain about Logic Instructions. M
-5
2) a) Explain about Branch Instructions. M
-5
b) Explain about Different Addressing modes M
-5
3) a) Explain about Diff input output operations M
-5
b) Explain about Different Addressing modes M
-5
4) a) Explain about Arithmetic Instructions. M
-5
b) Explain about Branch Instructions. M
 -5
5) a) Explain about Logic Instructions. M
-5
b) Explain about Different Addressing modes. M
UNIT
–IV
1) a) Explain about Accessing I/O -5
Devices M
-5
b) Explain about Interrupt Hardware M
-5
2) a) How do you Enabling and Disabling Interrupts M
-5
b) How do you handle Multiple Devices M
-5
3) a) Explain about Direct Memory Access M
-5
b) Explain about Synchronous Bus M
-5
4) a) Explain about Asynchronous Bus M
-5
b) Explain about Interface Circuits M
5) a) Explain about Peripheral Component Interconnect (PCI) -5
Bus M
-5
b) Explain about Universal Serial Bus (USB) M
UNIT
–V
1) a) Explain about Basic memory -5
circuits M
-5
b) Explain about Memory System Consideration M
-5
2) a) Explain about ROM M
-5
b) Explain about PROM M
 -5
3) a) Explain about EPROM M
-5
b) Explain about EEPROM M
-5
4) a) Explain about Flash Memory M
-5
b) Explain about Mapping Functions M
-5
5) a) Explain about Magnetic Hard Disks M
-5
b) Explain about Optical Disks M
UNIT
–VI
1) a) Explain about Register -5
Transfers M
-5
b) How to Perform Arithmetic Operations? Explain. M
-5
2) a) How to Perform Logic Operations ?Explain. M
-5
b) How to Fetch A Word From Memory? Explain. M
-5
3) a) Explain Execution of Complete Instruction M
-5
b) Explain about Hardwired Control M
-5
4) a) Explain about Microinstructions M
-5
b) Explain about Micro program Sequencing M
5) a) Wide Branch Addressing Microinstructions with next – -5
Address Field M
-5
b) Explain about Microinstructions M
 DEPARTMENT OF ELECTRONICS AND
COMMUNICATION ENGINEERING
LINEAR IC APPLICATIONS

Academic Year : 2018-2019

Year/Semester : III YEAR– I SEMESTER

Subject : LINEAR IC APPLICATIONS

[3
UNIT I - INTEGRATED M]
CIRCUITS

1a) Define differential amplifier and draw its block diagram.

Derive the AC analysis of Single Input Dual Output [7
Configuration in detail. M]
(or)
Derive the AC analysis of Dual Input Single Output
Configuration in detail.
b) (or)
Derive the AC analysis of Dual Input Dual Output
Configuration in detail.
(or)
Derive the AC analysis of Single Input Single Output
Configuration in detail.
co
Explain the operation of differential amplifier with swamping D
B
2a) resistors 4a
Why level translator is used with cascaded differential ) C
b) amplifier. de
b) D
3a) Explain the methods of realizing high input resistance.
b) Explain the Properties of other differential amplifier e
s
 ign 4 stage Cascade Differential Amplifier Stages and explain
why cascading is required. [7
5a)
Briefly explain about FET differential amplifier and calculate gain M]
b) Discuss the effect of RE to improve CMRR and what are the [3
methods to improve CMRR. M]
6.a) Explain the difference between constant current source [7 [5
and current mirror. M] M]
b)Why level translator is called [5
emitter follower [3 M] M]
(or) [5
M]
Explain why level translator is called voltage follower
[5
M]
[3
M]
[7
M]
 UNIT II- Characteristics of OP-Amps (IC 741)

Explain the terms (i) slew rates (ii) CMRR (iii) PSRR (iv) drift and
1a) List out ideal and
practical characteristics of above [7
parameters M]
An Op-Amp has a slew rate of 2V/μ sec. What is the maximum
b) frequency of an output
signal of peak value 5V at which the distortion sets in due to the [3
slew rate limitation? M]
2a) Explain stability of an Op-amp and ideal voltage transfer curve of [3
an Op-amp M]
b) Explain the operation of Op-amp along with block diagram in [7
detail. M]
3a) Explain the Frequency Compensation techniques of op-amp in [5
detail. M]
b) Draw the IC 741 op-amp pin diagram and explain the function of [5
each pin in detail. M]
Listout DC and AC characteristics of Explain the terms Input &
4a) opamp and Out put Off
[5
set voltages & currents. M]
b) List out the applications and Temperature ranges of IC 741 Op- [5
amp. M]
5a) Explain different Package Types of [3
op-amps. M]
(i)Explain open loop configurations
b) of CMRR. [3M]
(ii)Explain the basic processes used in silicon planer technology with
neat diagram. [4M]
[7
M
 [Each 2 ½
6. Write a brief note on M]
(a) Photo lithography
(b) Photo etching
(c) Epitaxial growth
(d) Diffusion
(a) Explain how the input offset voltage [3
7. compensated for. M]
(b) Why FET op-amps are better than BJT Op- [3
amps? M]
(c) Explain the term slew rate and how it affects the frequency response
of op-amp? [4M]
8. (a) Explain different IC packages. Mention the criteria for selecting an
IC package and give
[5M
different scales of integration. ]
[2M
(b)What do you mean by the term virtual ground? ]
( c)Explain the use of active load to improve .[3
CMRR M]
[Each 2
9. Explain the following compensation techniques M]
(a) Frequency compensation
(b) External compensation
( c) Internal compensation
(d ) Dominant pole compensation
(e) Pole-Zero compensation
 UNIT III- LINEAR & NON-LINEAR APPLICATIONS OF runnin
OP- AMPS 7 (a) E
1a)
Draw the non inverting op-amp circuit diagram and derive its initial
output voltage. b) Distin
trigger.
b) Draw the circuit diagram of differentiator &integrator by using IC
(
741 and explain its operation.
c)
Explain the summer and difference amplifier using IC 741 and 8 t
explain its operation.
2a)
Draw and explain Op amp Schmitt trigger.
b)
Draw the block diagram of log Amplifiers and explain its operation (
in detail.
What are the limitations of log amplifier and how to overcome 9 i
those limitations
3a) explain in
detail. 1
b) Draw the precision half wave rectifier, V to I and I to V 0
convertor circuit diagram and explain briefly.
Rf
c) Define virtual ground and Prove inverting Op amp gain is - .
R1

Explain the operation of Square wave generators along with

4a) circuit diagram.
Draw the block diagram of Non- Linear function generation and
b) explain its operation.
Draw the Instrumentation amplifier and explain its
5a) operation in detail.
Draw the Anti log Amplifiers circuit diagram and derive its
output voltage in detail.
6a) Explain how to obtain triangular wave using
square wave. [6 M]
(or)
Explain how to obtain triangular wave
using integrator (or)
Explain how to obtain triangular wave using schmitt trigger

b)What is the main advantage of comparator based triangular wave

generator over free
[3M]
[3M]
[4M]
[4M]
[6M]
[4M]

[3M]
[2M]
[5M]
[5M]
[5M]
 UNIT IV
ACTIVE FILTERS, ANALOG MULTIPLIERS AND
MODULATORS
[5
1a) Explain the operation of 1st/2nd/3rd order butterworth LP with upper M]
cutoff frequency 1Khz
b)
Explain the operation of 2nd/3rd/4th order band reject filter along [5
with circuit diagram. M]
2a) Define filters and Draw the frequency response and explain
characteristics of HPF, BPF, BRF and APF. [5M]
b)
Draw the block diagram of Four Quadrant multiplier and explain
its operation in detail. [5M]
3a) Design a second order low-pass Butterworth filter with a cut-off
frequency of 12 KHz and unity gain at low frequency. Also [5M]
determine the voltage transfer function magnitude
in dB at 15Hz for the filter. (Draw second order butterworth high
pass filter also draw its frequency response ) [2
b) List out the applications of analog switches. M]
c) Explain twin T notch filter [3
M]
4a) Draw the block diagram of balanced modulator and explain its
operation in detail and List out the features of IC 1496 balanced [7
modulator . M]
b) Design a wide band filter fh=400Hz , fl=2Khz, having the passband
gain 2. [3
M]
5a) Draw the circuit diagram of Sample & Hold amplifier and explain
its operation in detail. [5
b) Draw the circuit diagram of All pass filters and write its output M]
voltage equation.derive its output response. [5
M]

UNIT V- TIMERS & PHASE LOCKED LOOPS expressi

Draw th
1a)
Draw the pin diagram of IC 555 and explain each pin. 3a) operatio
b) Draw and Explain the principles and description of individual b) D
blocks of PLL in detail. Also discuss the applications of PLL in r
phase detector and VCO a
Explain the terms frequency multiplication, frequency translation, w
2a) tracking range and t
capture range of PLL. h
Give functional block diagram of VCO NE 565 and explain its e
b) working and necessary b
 lock diagram of Astable operations (free running) using IC 555
and derive its time constant.
Or
Draw the circuit diagram of Monostable multivibrator by using IC [3
555 timer and explain its operation and derive the expression of M]
time delay.
4a) Draw the circuit diagram of VCO 566 and explain its operation [7
with any example. M]
Discuss the role phase detector in PLL and explain thedigital phase
detector used in it. [5
b) M]
Drawthe block diagram of Astable operations (free running)
[5
5a) using OP-amp and M]
explain its working.
b) What are the modes of operations of 555 timer and explain [5
the working of Schmitt trigger using 555 timer? M]
c) Derive the expression for capture range for PLL where a single
RC network is used as a LPF. [5
M]

[6M]
[4M]

[5M]

[2
M]

[3
M]
 UNIT
VI
DIGITAL TO ANALOG AND ANALOG TO DIGITAL [3
CONVERTERS
M]
List out different ADCs and justify which A/D convertor is best in
1a) terms of speed. [7
Draw the block diagram of inverted R-2R DAC and explain its M]
b) operation in detail. [6
List out the DAC and ADC Specifications and compare them in M]
2a) detail. [4
Define the terms Linearity, resolution, settling time and accuracy M]
b) of A/D convertors.
An 8 bit ADC outputs all is when Vi=5.1v. Find resolution and [5
3a) digital output when M]
Vi=1.28v.
b) Draw the circuit diagram of weighted resistor DAC and explain
[5
its operation in detail. M]
4a) What are the basic DAC techniques?
[3
Draw the block diagram of successive approximation ADC and M]
explain its operation in detail.
b) Or
Draw the circuit diagram of counter type ADC and explain its [7
operation in detail M]
Or
Draw the block diagram of parallel Comparator type ADC and
explain the operation of it
Explain its operation with waveforms. What parameters decide its [5
M]
5a) conversion speed and
accuracy?
Draw the block diagram of dual slope ADC and explain its [5
operation in detail. M]
b) Or
Draw the circuit diagram of dual slope integration AD converter [5
and state its advantages. M]
What are the basic blocks preceding an ADC in a typical
[5
6a) application like digital audio M]
recording?
b) What are the different sources of errors in DAC? Explain.
Academic : 2018-2019
Year

Year/Seme : III –I Semester

ster
Subject : PULSE and DIGITAL CIRCUITS

QUESTION BANK
UNIT-I
1. a) Prove that a low pass circuit acts as an integrator. Derive an expression
for the output voltage levels under steady state conditions of a low pass
circuit excited by a ramp input.(5M)
b) Explain RLC ringing circuit with a neat sketch.(5M)
2. a) Draw the output waveform of an RC high-pass circuit with a square wave
input under different time constants. Derive the expression for percentage of
tilt. (5M)
b) What is an attenuator? How can an uncompensated attenuator be modified
as a compensated attenuator. Give the comparison between perfect
compensation, under compensation and over compensation. (5M)
3. a) Derive an expression for the output of low pass RC circuit excited by a step
input.Draw the output for different time constants.(5M)
b) Draw the response of an RC high pass circuit when applied with
exponential input. Explain
the
response for different time constants. (5M)
4. a) An RC low-pass filter is fed with a symmetrical square wave. The peak-to-
peak amplitude of the input waveform is 10 V and its average value is zero. It
is given that RC=T/2 where T is the period of the square wave. Determine the
peak-to-peak amplitude of the output waveform. (5M)
 b) Prove that et = T/2RC for ramp as input to the High pass RC-Circuit?
(5M)
5. a) Explain the working principle of rate-of-rise amplifier? (5M)
b) Explain the working of attenuator as a CRO Probe? (5M)

UNIT-II

1. a) Give the circuits of different types of shunt clippers and

explain their operation with the help of their transfer
characteristics .(5M)
b) State and prove clamping circuit theorem.(5M)
2. a) Write short notes on practical clamping circuits. (5M)
b) A voltage signal of (10 Sinwt) is applied to the circuit with ideal diodes
shown in figure below. Estimate the maximum & minimum values of output
waveform and maximum current through each diode. Also draw the input-output
waveforms with proper explanation.(5M)
3. a)Draw the basic circuit diagram of negative peak clamper circuit and explain its
Operation.
b) Give some applications of clipping & Clamping circuits. (5M)
4.a) With neat circuit diagram, explain the working of an emitter coupled clipper.
(5M)
b) Explain the clamping circuit considering the source resistance and the resistan
diode forward
(5M)
5. a) A symmetrical 50 Hz square wave whose peak to peak excursions are ce.
± 100 V with
respect to ground is to be positively clamped at 25 V. Draw the
necessary circuit diagram and output
waveform for this purpose. (5M)
b) Design a diode clamper to restore the negative peaks of the
input signal to zero level. Use a silicon diode with Rf= 50 Ω and
Rr= 400 kΩ. The frequency of the input signal is 5 kHz.(5M)

UNIT –III
1. Explain the terms pertaining to transistor switching characteristics.
i) Rise time.[2M] ii) Delay time. [2M] iii) Turn-
on time.[1M] iv) Storage time.[2M] v) Fall
time.[2M] vi) Turn-off time.[1M]
2. a) Describe the sequence of events in an n-p-n transistor to change from cutoff to
saturation and vice versa. How does temperature affect the saturation junction of a
transistor? (5M)
b) Briefly discuss the influence of breakdown voltages on the choice of supply
voltage in a
transis
tor
switch. (5M)
3.a) Design a Schmitt trigger circuit using npn silicon transistors with VBE = 0.7V,
VCE(sat) = 0.2V, hfe(min) = 60 and Ic(ON)= 3mA to meet the following specifications:
Vcc =12V, upper threshold voltage, VUT= 4V, lower threshold voltage,VLT=2V. (5M)
b) What are transpose capacitors? Explain how the commutating capacitors will
increase the speed of a fixed-bias binary. (5M)
4.a) With neat circuit diagram, Explain the working of fixed bias bistable multi
vibrator. (5M)
b)Calculate the component values of a mono stable multi vibrator developing an
output pulse of 500 μs duration. Assume hfe(min) = 25, ICE(min)= 5 mA, VCC= 10 V and
VBB = -4V. (5M)
5.a) Draw the circuit of a bistable multivibrator with symmetrical collector
triggering. (5M)
b)What are commutating capacitors? Show a symmetrical triggering arrangement
for bi-stable multivibrator
and explain its working. (5M)

UNIT -IV
1. a) Explain the operation of a Monostable multivibrator and derive for the pulse
width with necessary waveforms & circuirts. (5M)
b)Design a collector coupled astable multivibrator using NPN silicon transistors
with hfe=40, rbb=200ohms supploied with Vcc=10V and circuit component values
are Rc=1.2Kohms and C=270 pF. (5M)
2. a) Draw the circuit diagram of an astable multivibrator and obtain all the steady
state voltages and currents. Show how it acts as a voltage to frequency converter.
(5M)
b) Design and draw a collector-coupled ONE-SHOT using silicon npn
transistors with hFE(MIN) =20. In stable state, the transistor in cut-off has VBE = -1V
and the transistor in saturation has base current, IB which is
50% excess of the IB(MIN) value. Assume VCC = 8V, IC(SAT) =2mA, delay time =
2.5ms & R1 = R2. Find RC, R, R1, C and VBB . (5M)
3. a) Design a stable multi vibrator to generate a square wave of 1 kHz frequency
with a duty cycle of 25% using silicon n-p-n transistors with hFE(MIN) = 40. (5M)
b)Design a collector coupled one-shot with a gate width of 3 ms using NPN
transistors Assume necessary data. (5M)
4. Explain the operation of a Monostable multivibrator and derive for the pulse
width with necessary waveforms & circuirts.[10M]
5. a) Derive the equation for voltage-to-frequency converter when a stable multi
vibrator is used as a basic circuit. (5M)
b) The Schmitt trigger circuit also called sinusoidal to square converter? Explain
the working principle. (5M)

UNIT -V

1. Explain the working of a transistor Bootstrap sweep circuit

and derive expression for the slope sweep error. (10M)
2. a) Why the time base generators are called sweep circuits?
Give most important applications of time –base generators.
(5M)
b) What are the different methods of generating time-base
waveforms? Explain about each briefly. (5M)
3. Explain the working of Transistor Miller sweep circuit. What
are its advantages over Bootstrap sweep circuits? (5M)
4. a) Define and derive the terms slope error, displacement error and
transmission error. (5M)
b) How is deviation of linearity expressed? What do you
mean by sweep time and restoration time? (5M)
5. Explain the basic principles of Miller and Bootstrap time-base generators.
Give the comparison of both the generation methods. (10M)
UNIT-VI
1. a) Draw the circuit diagram of a unidirectional sampling gate
which delivers an output only at the coincidence of a number of
control voltages and explain its working. (5M)
b) Explain how to cancel the pedestal in a sampling gate with suitable
circuit diagram. (5M)
2. a) Explain the function of a sampling gate used in Sampling
Scopes also explain how sampling gate is used in chopping
amplifiers. (5M)
b) Explain how the loading of the control signal is reduced
when the number of inputs increases in a sampling gate. (5M)
3. a) Explain about unidirectional diode sampling gate.
Write its advantages and disadvantages. (5M)
b) With neat circuit diagram, Explain bidirectional sampling gate using
transistors. (5M)
4. a) What is meant by synchronization? Why it is needed? Explain. (5M)
 b) Explain about four diode sampling gate. (5M)
5. a) Explain about phase delay and phase jitters. (5M)
b) Explain how pedestal can be reduced in gate circuit. (5M)
 QUESTION
BANK
Academic Year : 2018-2019

Regulation : R16
Antenna and Wave
Subject : Propagation

UNIT-I
Sketch and comment on the current distributions and radiation patterns of
1. a) vertical antennas of length
l/2, l, 3l/2, 2l. [5M]
Derive the relationship between effective aperture area and gain of
b) antenna. [5M]
Define the terms: i)
2. a) Effective length ii) Effective aperture area. [5M]
Calculate effective length and effective aperture area of antenna whose
b) radiation resistance is 73
ohms. [5M]
3. a) Define and explain the following terms: [5M]
(i)
Directivity (ii) Gain (iii) Aperture Efficiency
An antenna has a radiation resistance of 72Ω, a loss resistance of 8Ω and a
b) power gain of 12 dB.
Determine the antenna efficiency and its directivity. [5M]
a) Explain the terms Isotropic, Directional, Omni directional patterns
4. and Radiation intensity.
[5M]
 b) Show that the radiation resistance of a λ/4 monopole is 36.5ohms. [5M]
5. a) Discuss the current distribution on a thin wire antenna. [5M]
b) In a microwave communication link, two identical antennas operating at 10
GHz are used with power gain of 40 dB. If the transmitter power is 1W.
Find the received power, if the range of the
[5
link is 30Km. M]

UNIT-II
1. a) Calculate the relative amplitudes of Radiation, Induction and Electrostatic
Fields at a distance of 2λ
[5
from the short current element. M]
b) Prove that if Power radiated (Pr) is expressed in terms of capacitance and
voltage and if the voltage is held constant, that the radiated power will then
proportional to the fourth power of frequency for a
[5
Hertzian Di-Pole. M]
2. a) The radiation intensity of a particular antenna is given by Ø(θ, Ø) = sin2θ.
Calculate the directivity of
[5
the antenna. M]
b) Show that the radiation resistance of a small loop is equal to 320π 4(A/λ2)
ohms where A is loop area. [5M]
3. a) Derive the expressions for electric field in case of short current element
and hence obtain the
[5
conditions for the field to be in Franhofer region. M]
b) Find the distance from a radiating element with 60Hz current such that
radiation and induction fields
are equal. [5M]
Show that the radiation resistance of half wave dipole is
4. a) 73ohm. [5M]
b) Distinguish between Dipole and Monopole. [5M]
Explain the concept of retarded scalar and vector
5. a) potentials. [5M]
Obtain expression for potential fields due to sinusoidally varying
b) sources and bring out the
importance of Lorentz guage condition. [5M]

UNIT-III
Explain the principle of pattern multiplication. What is the effect of earth
1. a) on the radiation pattern of
antennas. [5M]
 b) A uniform linear array consists of 16 isotropic point source with a spacing
of λ/4 if the phase
difference α=-900. i. ii. Directivity iii. Effective
Find HPBW. aperture [5M]
2. a) Compare the performance of Broadside and End fire array. [5M]
b) Show that the width of principle lobe of an end fine array is greater than
that of broadside array of
the same length. [5M]
3. Show that directivity of a BSA of two identical isotropic in phase point
a) sources Spaced a distance
d=λ/2 is given by D = {2/[1 + 1/ßdsinßd]}. [5M]
The radiation intensity U=A0sinθ for an antenna. Determine
b) the directivity. [5M]
4. a) Derive the conditions for the linear array of N isotropic elements to radiate
in end fire and find the
first two side lobe levels. [5M]
Prove that the level of secondary lobe is -13.5dB below that of major lobe
b) in a uniform linearly
array. [5M]
5.
a) Briefly explain the following: [5M]
i. Principle of pattern multiplication ii. Binomial array
 A linear broadside array consists of four equal isotropic in phase
b) point sources with λ/3
spacing & overall length of the array is λ. Find the directivity
& beam width. [5M]
UNIT-
IV

Distinguish between Traveling wave and Standing wave

1. a) antennas. [3M]
Compare Resonant and Non Resonant
b) antennas. [3M]
c) Explain the working of Rhombic antenna. [4M]
Describe the characteristics of long wire traveling wave antenna. Sketch
2. a) their pattern for lengths of:
i.λ/2 ii. 5 λ iii. 20 λ. [5M]
With reference to paraboloides, Explain
b) the following: [5M]
(i)Aperture (ii)Front to back (iii)Types of
efficiency ratio feeds
Explain the construction and radiation characteristics of
3. a) Helical Antenna. [5M]
b) Discuss how the directivity of horn antenna can be measured. [5M]
Explain the principle and working of Yagi
4. a) Antenna. [5M]
Design YagiUda antenna of six elements to provide a gain of
b) 12dB if the operating frequency is
200MHz. [5M]
5. a) What is Zoning? What are its advantages? [5M]
With neat setup, explain the absolute method of measuring the
b) gain of an antenna. [5M]
UNIT-
V
Describe the methods for measuring the below parameters for
1. a) an antenna [5M]
ii) Directivity with a neat block
i) Gain diagram
Distinguish between sectoral, pyramidal and conical horns, with neat
b) sketches. List out their utility
and applications. [5M]
 a List out the differences between active and passive corner
2. ) reflectors. [5M]
With reference to paraboloids, explain the
b) following: [5M]
i) f/D ii) Spill over and aperture iii) Front to back
ratio efficiency ratio

3. a) Explain the principle of formation of images in an active corner reflector

antenna. Hence sketch the image formation for a 90o corner reflector.
Obtain array factor for 90o corner reflector. [5M]
b) What is the principle of equality of path length? How is it applicable to
Horn antennas? Obtain an

expression for the directivity of a pyramidal horn in terms of its [5

aperture dimensions. M]
4. a) With neat set up, explain the absolute method of measuring the [5
gain of an antenna. M]
 Discuss about Dielectric and metal Lens Antennas and their [5
b) applications. M]
5. Explain the Cassegrain and offset feed of Parabolic Antenna [5
a) in detail. M]

b) How is the field pattern of a receiving antenna experimentally determined.

Explain with a neat

[5
diagram. M]

UNIT-VI
Describe briefly the salient features of ground
1. a) wave propagation. [5M]
What should be the polarization of EM wave for the ground wave
b) propagation? Justify. [5M]
Explain the term” wave tilt of surface
2. a) waves”. [5M]
List out the modes of propagation and their frequency ranges for radio
b) waves. Show that the electric
4 ℎ
field strength of space wave propagation is ℎ
given by = 2 [5M]
0
Write a short ii) Virtual
3. notes on: i) MUF Height
iv) Multihop
iii) Skip Distance Transmission. [10M]
Derive the relationship between MUF and
4. a) critical frequency. [5M]
b) Show that the radius of curvature of ray path is given by 2/(dεr/dh) for
tropospheric waves. 5M

5. a) Describe any two types of fading normally encountered in radio wave

propagation. How are the

[5
problems of fading overcome? M]
b) Determine the change in the electron density of E-layer when the critical
frequency changes from 4

[
5
MHz to 1 MHz between mid - day and M
sun-set. ]