Wireless Components

434 MHz ASK/FSK Transmitter in 10-pin Package

TDK 5100 F Version 0.1

Target Specification July 2003

Confidential
Preliminary
 Confidential
Revision History

Current Version: Version 0.1 as of July 2003

Previous Version:

Page Page Subjects (major changes since last revision)

(in previous (in current
Version) Version)

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Edition 31.10.2002
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 TDK 5100 F
Preliminary

Product Info

Product Info

General Description The TDK 5100 F is a single chip ASK/ Package

FSK transmitter for the frequency band
433-435 MHz. The IC offers a high
level of integration and needs only a
few external components. The device
contains a fully integrated PLL synthe-
sizer and a high efficiency power ampli-
fier to drive a loop antenna. A special
circuit design and an unique power
amplifier design are used to save cur-
rent consumption and therefore to save
battery life. Additional features are a
power down mode and a divided clock
output.

Features ■ fully integrated frequency synthe- ■ voltage supply range 2.1 - 4 V

sizer
■ temperature range −40 ... +125°C
■ VCO without external components
■ power down mode
■ ASK and FSK modulation
■ crystal oscillator 13.56 MHz
■ frequency range 433-435 MHz
■ FSK-switch
■ high efficiency power amplifier
■ divided clock output for µC
(typically 5 dBm)
■ low external component count
■ low supply current (typically 7mA)

Applications ■ Tire pressure monitoring systems ■ Alarm systems

■ Keyless entry systems ■ Communication systems
■ Remote control systems

Ordering Information

Type Ordering Code Package

TDK 5100 F t.b.d. P-TSSOP-10
available on tape and reel

Wireless Components Product Info Target Specification, July 2003

1 Product Description

Contents of this Chapter

1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
 TDK 5100 F
Preliminary

Product Description

1.1 Overview

The TDK 5100 F is a single chip ASK/FSK transmitter for the frequency band
433-435 MHz. The IC offers a high level of integration and needs only a few
external components. The device contains a fully integrated PLL synthesizer
and a high efficiency power amplifier to drive a loop antenna. A special circuit
design and an unique power amplifier design are used to save current con-
sumption and therefore to save battery life. Additional features are a power
down mode and a divided clock output.
The IC can be used for both ASK and FSK modulation.

1.2 Applications

■ Tire pressure monitoring systems

■ Keyless entry systems
■ Remote control systems
■ Alarm systems
■ Communication systems

1.3 Features

■ fully integrated frequency synthesizer

■ VCO without external components
■ ASK and FSK modulation
■ switchable frequency range 433-435 MHz
■ high efficiency power amplifier (typically 5 dBm)
■ low supply current (typically 7 mA)
■ voltage supply range 2.1 - 4 V
■ temperature range −40°C ... 125°C
■ power down mode
■ crystal oscillator 13.56 MHz
■ FSK-switch
■ divided clock output for µC
■ low external component count

Wireless Components 1-2 Target Specification, July 2003

 TDK 5100 F
Preliminary

Product Description

1.4 Package Outlines

1.1 max.

+0.08
0.85 ±0.1

0.125 -0.05
0.15 max.
3 ±0.1
C

6 max.
H

0.5

0.09
A 0.1 A
0.22 ±0.05 0.42 +0.15
-0.1
0.08 M ABC
4.9
0.25 M ABC

3 ±0.1
B
Index Marking

Figure 1-1 P-TSSOP-10

Wireless Components 1-3 Target Specification, July 2003

2 Functional Description

Contents of this Chapter

2.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3 Functional Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.4 Functional Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.4.1 PLL Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.4.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.4.3 Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.4.4 Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.4.4.1 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.4.4.2 PLL Enable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.4.4.3 Transmit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.4.5 Recommended Timing Diagrams for ASK- and FSK-Modulation . 2-10
 TDK 5100 F
Preliminary

Functional Description

2.1 Pin Configuration

CLKOUT 1 10 PDWN

VS 2 9 PAOUT

GND 3 TDK 5100F 8 PAGND

FSKOUT 4 7 FSKDTA

COSC 5 6 ASKDTA

Pin_config.wmf

Figure 2-1 IC Pin Configuration

Table 2-1
Pin No. Symbol Function
1 CLKOUT Clock Driver Output (847.5 kHz)
2 VS Voltage Supply
3 GND Ground
4 FSKOUT Frequency Shift Keying Switch Output
5 COSC Crystal Oscillator Input (13.56 MHz)
6 ASKDTA Amplitude Shift Keying Data Input
7 FSKDTA Frequency Shift Keying Data Input
8 PAGND Power Amplifier Ground
9 PAOUT Power Amplifier Output (434 MHz)
10 PDWN Power Down Mode Control

Wireless Components 2-2 Target Specification, July 2003

 TDK 5100 F
Preliminary

Functional Description

2.2 Pin Definitions and Functions

Table 2-2
Pin Symbol Interface Schematic1) Function
No.
1 CLKOUT Clock output to supply an external device.
VS An external pull-up resistor has to be added
in accordance to the driving requirements of
1 the external device.

300 Ω The clock frequency is 847.5 kHz.

2 VS This pin is the positive supply of the trans-

mitter electronics.
An RF bypass capacitor should be con-
nected directly to this pin and returned to
GND (pin 3) as short as possible.
3 GND General ground connection.
4 FSKOUT This pin is connected to a switch to GND
VS VS (pin 3).

The switch is closed when the signal at

FSKDTA (pin 7) is in a logic low state.

200 µA The switch is open when the signal at

FSKDTA (pin 7) is in a logic high state.
1.5 kΩ
4
FSKOUT can switch an additional capacitor
to the reference crystal network to pull the
crystal frequency by an amount resulting in
the desired FSK frequency shift of the trans-
mitter output frequency.

5 COSC This pin is connected to the reference oscil-

VS VS lator circuit.
The reference oscillator is working as a neg-
ative impedance converter. It presents a
6 kΩ negative resistance in series to an induc-
tance at the COSC pin.
5

100 µA

Wireless Components 2-3 Target Specification, July 2003

 TDK 5100 F
Preliminary

Functional Description

6 ASKDTA Digital amplitude modulation can be

VS + 1.2 V imparted to the Power Amplifier through this
pin.
60 kΩ
6
A logic high (ASKDTA > 1.5 V or open)
+ 1.1 enables the Power Amplifier.
90 kΩ
A logic low (ASKDTA < 0.5 V)
5 0 pF 30 µA disables the Power Amplifier.

7 FSKDTA Digital frequency modulation can be

VS + 1.2 V imparted to the Xtal Oscillator by this pin.
The VCO-frequency varies in accordance to
the frequency of the reference oscillator.
60 kΩ
7
A logic high (FSKDTA > 1.5V or open)
+ 1.1 V
90 kΩ
sets the FSK switch to a high impedance
state.
3 0 µA
A logic low (FSKDTA < 0.5 V)
closes the FSK switch
from FSKOUT (pin 4) to GND (pin 3).
A capacitor can be switched to the reference
crystal network this way. The Xtal Oscillator
frequency will be shifted giving the designed
FSK frequency deviation.
8 PAGND Ground connection of the power amplifier.
9 The RF ground return path of the power
amplifier output PAOUT (pin 9) has to be
concentrated to this pin.
9 PAOUT RF output pin of the transmitter.
A DC path to the positive supply VS has to
8
be supplied by the antenna matching net-
work.

10 PDWN Disable pin for the complete transmitter cir-

VS cuit.
40 µA ∗ (ASKDTA+FSKDTA)
A logic low (PDWN < 0.7 V) turns off all
transmitter functions.
5 kΩ
10
A logic high (PDWN > 1.5 V) gives access to
"ON" all transmitter functions.
150 kΩ
PDWN input will be pulled up by 40 µA inter-
nally by either setting FSKDTA or ASKDTA
250 kΩ to a logic high-state.

1) Indicated voltages and currents apply for PLL Enable Mode and Transmit Mode.
In Power Down Mode, the values are zero or high-ohmic.

Wireless Components 2-4 Target Specification, July 2003

 Wireless Components
Figure 2-2
FSK ASK Power Power
Data Data Down Supply
Input Input Control VS

7 6 10 2

Pow er
OR

2-5
FSK
Supply
4
Switch
On
XTA L Pow er 9 Power

Functional Block diagram

PFD :64 V CO :2 Amplifier
5 Os c A MP Output
Crystal
2.3 Functional Block diagram

13.56 M Hz

8 Power
Amplifier
LF Ground
:16

1 3
Clock
Ground
Output
Preliminary

Target Specification, July 2003

TDK 5100 F

Functional Description

Blockdiagram.wmf
 TDK 5100 F
Preliminary

Functional Description

2.4 Functional Blocks

2.4.1 PLL Synthesizer

The Phase Locked Loop synthesizer consists of a Voltage Controlled Oscillator

(VCO), an asynchronous divider chain, a phase detector, a charge pump and a
loop filter. It is fully implemented on chip. The tuning circuit of the VCO consist-
ing of spiral inductors and varactor diodes is on chip, too. Therefore no addi-
tional external components are necessary. The nominal center frequency of the
VCO is 868 MHz. The oscillator signal is fed both, to the synthesizer divider
chain and to the power amplifier. The overall division ratio of the asynchronous
divider chain is 64. The phase detector is a Type IV PD with charge pump. The
passive loop filter is realized on chip.

2.4.2 Crystal Oscillator

The crystal oscillator operates at 13.56 MHz.

The crystal frequency is divided by 16. The resulting 847.5 kHz are available at
the clock output CLKOUT (pin1) to drive the clock input of a micro controller.

To achieve FSK transmission, the oscillator frequency can be detuned by a

fixed amount by switching an external capacitor via FSKOUT (pin 4).
The condition of the switch is controlled by the signal at FSKDTA (pin 7).

Table 2-3
FSKDTA (pin7) FSK Switch
Low 1) CLOSED
Open2), High3) OPEN
1) Low: Voltage at pin < 0.5 V
2) Open: Pin open
3) High: Voltage at pin > 1.5 V

Wireless Components 2-6 Target Specification, July 2003

 TDK 5100 F
Preliminary

Functional Description

2.4.3 Power Amplifier

The VCO frequency is divided by 2 and fed to the Power Amplifier.

The Power Amplifier can be switched on and off
by the signal at ASKDTA (pin 6).

Table 2-4
ASKDTA (pin 6) Power Amplifier
Low 1) OFF
Open2), High3) ON
1) Low: Voltage at pin < 0.5 V
2) Open: Pin open
3) High: Voltage at pin > 1.5 V

The Power Amplifier has an Open Collector output at PAOUT (pin 9) and
requires an external pull-up coil to provide bias. The coil is part of the tuning and
matching LC circuitry to get best performance with the external loop antenna.
To achieve the best power amplifier efficiency, the high frequency voltage swing
at PAOUT (pin 9) should be twice the supply voltage.
The power amplifier has its own ground pin PAGND (pin 8) in order to reduce
the amount of coupling to the other circuits.

2.4.4 Power Modes

The IC provides three power modes, the POWER DOWN MODE, the PLL
ENABLE MODE and the TRANSMIT MODE.

2.4.4.1 Power Down Mode

In the POWER DOWN MODE the complete chip is switched off.
The current consumption is typically 0.3 nA at 3 V 25°C.
This current doubles every 8°C. The values for higher temperatures are
typically 14 nA at 85°C and typically 600 nA at 125°C.

2.4.4.2 PLL Enable Mode

In the PLL ENABLE MODE the PLL is switched on but the power amplifier is
turned off to avoid undesired power radiation during the time the PLL needs to
settle. The turn on time of the PLL is determined mainly by the turn on time of
the crystal oscillator and is less than 1 msec when the specified crystal is used.
The current consumption is typically 3.5 mA.

Wireless Components 2-7 Target Specification, July 2003

 TDK 5100 F
Preliminary

Functional Description

2.4.4.3 Transmit Mode

In the TRANSMIT MODE the PLL is switched on and the power amplifier is
turned on too.
The current consumption of the IC is typically 7 mA when using a proper trans-
forming network at PAOUT, see Figure 3-1.

2.4.4.4 Power mode control

The bias circuitry is powered up via a voltage V > 1.5 V at the pin PDWN (pin10).
When the bias circuitry is powered up, the pins ASKDTA and FSKDTA are
pulled up internally.
Forcing the voltage at the pins low overrides the internally set state.
Alternatively, if the voltage at ASKDTA or FSKDTA is forced high externally, the
PDWN pin is pulled up internally via a current source. In this case, it is not nec-
essary to connect the PDWN pin, it is recommended to leave it open.

Wireless Components 2-8 Target Specification, July 2003

 TDK 5100 F
Preliminary

Functional Description

The principle schematic of the power mode control circuitry is shown in

Figure 2-5
.

PDW N
A SKDTA
OR
FSKDTA
On

Bias
Sourc e
120 kΩ

Bias Voltage
120 kΩ FSKOUT
FSK
On
434 PA
PLL PA OUT
MHz
IC

Power_Mode.wmf

Figure 2-5 Power mode control circuitry

Table 2-5 provides a listing of how to get into the different power modes

Table 2-5
PDWN FSKDTA ASKDTA MODE
Low1) Low, Open Low, Open
POWER DOWN
Open2) Low Low

High3) Low, Open, High Low

PLL ENABLE
Open High Low
High Low, Open, High Open, High
Open High Open, High TRANSMIT
Open Low, Open, High High
1) Low: Voltage at pin < 0.7 V (PDWN)
Voltage at pin < 0.5 V (FSKDTA, ASKDTA)
2) Open: Pin open
3) High: Voltage at pin > 1.5 V

Other combinations of the control pins PDWN, FSKDTA and ASKDTA are not
recommended.

Wireless Components 2-9 Target Specification, July 2003

 TDK 5100 F
Preliminary

Functional Description

2.4.5 Recommended Timing Diagrams for ASK- and FSK-Modulation

ASK Modulation using FSKDTA and ASKDTA, PDWN not connected

M o de s: P ow er D o w n P L L E na ble T ran sm it

H igh
FSK DTA
Lo w
to t

DATA
O p en , H igh
A SK DTA
Lo w
to t

m in. 1 m sec.

ASK_mod.wmf

Figure 2-6 ASK Modulation

FSK Modulation using FSKDTA and ASKDTA, PDWN not connected

M o de s: P ow er D o w n P L L E na ble T ran sm it

DATA
H igh
FSK DTA
Lo w
to t

H igh
A SK DTA
Lo w
to t

m in. 1 m sec.

FSK_mod.wmf

Figure 2-7 FSK Modulation

Wireless Components 2 - 10 Target Specification, July 2003

 TDK 5100 F
Preliminary

Functional Description

Alternative ASK Modulation, FSKDTA not connected.

M o de s: P ow er D ow n P LL E na ble Tran sm it

H igh
P DW N
Lo w
to t

D AT A
O p en , H igh
A SK DTA
Lo w
to t

m in . 1 m se c.

Alt_ASK_mod.wmf

Figure 2-8 Alternative ASK Modulation

Alternative FSK Modulation

M o de s: P ow er D o w n P L L E na ble T ran sm it

H igh
PDW N
Lo w
to t

O p en , H igh
A SK D TA
Lo w
to t
DATA
O p en , H igh
FSK D TA
Lo w
to t

m in. 1 m sec.
Alt_FSK_mod.wmf

Figure 2-9 Alternative FSK Modulation

Wireless Components 2 - 11 Target Specification, July 2003

 TDK 5100 F
Preliminary

Functional Description

Wireless Components 2 - 12 Target Specification, July 2003

3 Applications

Contents of this Chapter

3.1 50 Ohm-Output Testboard Schematic . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.2 50 Ohm-Output Testboard Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Bill of material (50 Ohm-Output Testboard) . . . . . . . . . . . . . . . . . . . . 3-4
3.4 Application Hints on the Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . 3-5
3.5 Design Hints on the Clock Output (CLKOUT). . . . . . . . . . . . . . . . . . . 3-7
3.6 Application Hints on the Power-Amplifier . . . . . . . . . . . . . . . . . . . . . . 3-8
 TDK 5100 F
Preliminary

Applications

3.1 50 Ohm-Output Testboard Schematic

T.b.d.

50ohm_test.wmf

Figure 3-1 50Ω-output testboard schematic

Wireless Components 3-2 Target Specification, July 2003

 TDK 5100 F
Preliminary

Applications

3.2 50 Ohm-Output Testboard Layout

T.b.d.

Figure 3-2 Top Side of TDK 5100 F-Testboard with 50 Ω-Output

T.b.d.

Figure 3-3 Bottom Side of TDK 5100 F-Testboard with 50 Ω-Output

Wireless Components 3-3 Target Specification, July 2003

 TDK 5100 F
Preliminary

Applications

3.3 Bill of material (50 Ohm-Output Testboard)

The bill of materials is to be determined.

Wireless Components 3-4 Target Specification, July 2003

 TDK 5100 F
Preliminary

Applications

3.4 Application Hints on the Crystal Oscillator

1. Application Hints on the crystal oscillator

The crystal oscillator achieves a turn on time less than 1 msec when the
specified crystal is used. To achieve this, a NIC oscillator type is implemented
in the TDK 5100 F. The input impedance of this oscillator is a negative resis-
tance in series to an inductance. Therefore the load capacitance of the crystal
CL (specified by the crystal supplier) is transformed to the capacitance Cv.

-R L f, C L Cv

IC

1
Cv = Formula 1)
1
+ ω 2L
CL

CL: crystal load capacitance for nominal frequency

ω: angular frequency
L: inductance of the crystal oscillator

Example for the ASK-Mode:

Referring to the application circuit, in ASK-Mode the capacitance C7 is replaced

by a short to ground. Assume a crystal frequency of 13.56 MHz and a crystal
load capacitance of CL = 20 pF. The inductance L at 13.5 MHz is about 4.6 µH.
Therefore C6 is calculated to 12 pF.

1
Cv = = C6
1
+ω 2L
CL

Wireless Components 3-5 Target Specification, July 2003

 TDK 5100 F
Preliminary

Applications

Example for the FSK-Mode:

FSK modulation is achieved by switching the load capacitance of the crystal as

shown below.

FS KD TA

FS KO U T

C sw

-R L f, C L C v1 C v2
COSC

IC

The frequency deviation of the crystal oscillator is multiplied with the divider
factor N of the Phase Locked Loop to the output of the power amplifier. In case
of small frequency deviations (up to +/- 1000 ppm), the two desired load
capacitances can be calculated with the formula below.

∆f 2(C 0 + CL )
CL m C 0 (1 + )
N * f1 C1
CL ± =
∆f 2(C 0 + CL)
1± (1 + )
N * f1 C1

CL: crystal load capacitance for nominal frequency

C0: shunt capacitance of the crystal
f: frequency
ω: ω = 2πf: angular frequency
N: division ratio of the PLL
df: peak frequency deviation

Because of the inductive part of the TDK 5100 F, these values must be cor-
rected by Formula 1. The value of Cv± can be calculated.

1
Cv± =
1
+ ω 2L
CL ±

Wireless Components 3-6 Target Specification, July 2003

 TDK 5100 F
Preliminary

Applications

If the FSK switch is closed, Cv_ is equal to Cv1 (C6 in the application diagram).
If the FSK switch is open, Cv2 (C7 in the application diagram) can be calculated.

Csw ∗ Cv1 − (Cv +) ∗ (Cv1 + Csw)

Cv 2 = C 7 =
(Cv +) − Cv1

Csw: parallel capacitance of the FSK switch (3 pF incl. layout parasitics)

Remark: These calculations are only approximations. The necessary values

depend on the layout also and must be adapted for the specific
application board.

3.5 Design Hints on the Clock Output (CLKOUT)

The CLKOUT pin is an open collector output. An external pull up resistor (RL)
should be connected between this pin and the positive supply voltage. The
value of RL is depending on the clock frequency and the load capacitance CLD
(PCB board plus input capacitance of the microcontroller). RL can be calculated
to:

1
RL =
fCLKOUT * 8 * CLD

Table 3-1
fCLKOUT=847 kHz

CL[ pF] RL[ kOhm ]

5 27
10 12
20 6.8

Remark: To achieve a low current consumption and a low

spurious radiation, the largest possible RL should be chosen.

Even harmonics of the signal at CLKOUT can interact with the crystal oscillator
input COSC preventing the start-up of oscillation. Care must be taken in layout
by sufficient separation of the signal lines to ensure sufficiently small coupling.

Wireless Components 3-7 Target Specification, July 2003

 TDK 5100 F
Preliminary

Applications

3.6 Application Hints on the Power-Amplifier

The power amplifier operates in a high efficient class C mode. This mode is
characterized by a pulsed operation of the power amplifier transistor at a current
flow angle of θ<<π. A frequency selective network at the amplifier output
passes the fundamental frequency component of the pulse spectrum of the
collector current to the load. The load and its resonance transformation to the
collector of the power amplifier can be generalized by the equivalent circuit of
Figure 3-4. The tank circuit L//C//RL in parallel to the output impedance of the
transistor should be in resonance at the operating frequency of the transmitter.

VS
L C RL

Equivalent_power_wmf.

Figure 3-4 Equivalent power amplifier tank circuit

The optimum load at the collector of the power amplifier for “critical” operation
under idealized conditions at resonance is:

V S2
R LC =
2 * PO

The theoretical value of RLC for an RF output power of Po= 5 dBm (3.16 mW) is:

32
R LC = = 1423 Ω
2 * 0 .00316

“Critical” operation is characterized by the RF peak voltage swing at the

collector of the PA transistor to just reach the supply voltage VS.
The high degree of efficiency under “critical” operating conditions can be
explained by the low power losses at the transistor. During the conducting
phase of the transistor, its collector voltage is very small. This way the power
loss of the transistor, equal to iC*uCE , is minimized. This is particularly true for
small current flow angles of θ<<π.
In practice the RF-saturation voltage of the PA transistor and other parasitics
reduce the “critical” RLC.

Wireless Components 3-8 Target Specification, July 2003

 TDK 5100 F
Preliminary

Applications

The output power Po is reduced by operating in an “overcritical” mode

characterised by RL > R LC.
The power efficiency (and the bandwidth) increase when operating at a slightly
higher RL, as shown in Figure 3-5.
The collector efficiency E is defined as

PO
E=
VS I C

The diagram of Figure 3-5 was measured directly at the PA-output at VS = 3 V.

Losses in the matching circuitry decrease the output power by about 1.5 dB. As
can be seen from the diagram, 550 Ω is the optimum impedance for operation
at 3 V. For an approximation of ROPT and POUT at other supply voltages those
two formulas can be used:

ROPT ~ VS

and

POUT ~ ROPT

1 0 *E
P o [m W ]
7
6
5
4
3
1 0 *E
2
Po
1
0
0 1000 2 000 30 00

R L [O h m ]

Power_output.wmf

Figure 3-5 Output power Po (mW) and collector efficiency E vs. load resistor RL.

The DC collector current Ic of the power amplifier and the RF output power Po
vary with the load resistor RL. This is typical for overcritical operation of class C
amplifiers. The collector current will show a characteristic dip at the resonance
frequency for this type of “overcritical” operation. The depth of this dip will
increase with higher values of RL.

Wireless Components 3-9 Target Specification, July 2003

 TDK 5100 F
Preliminary

Applications

As Figure 3-6 shows, detuning beyond the bandwidth of the matching circuit
results in an increase of the collector current of the power amplifier and in some
loss of output power. This diagram shows the data for the circuit of the test
board at the frequency of 434 MHz. The effective load resistance of this circuit
is RL = 550 Ω, which is the optimum impedance for operation at 3 V. This will
lead to a dip of the collector current of approx. 40%.

T.b.d.

tbd.wmf

Figure 3-6 Output power and collector current vs. frequency

C3, L2-C2 and C8 are the main matching components which are used to
transform the 50 Ω load at the SMA-RF-connector to a higher impedance at the
PA-output (700 Ω @ 3 V). L1 can be used for some finetuning of the resonant
frequency but should not become too small in order to keep its losses low.

The transformed impedance of 550+j0 Ω at the PA-output-pin can be verified

with a network analyzer using the following measurement procedure:
1. Calibrate your network analyzer.
2. Connect some short, low-loss 50 Ω cable to your network analyzer with an
open end on one side. Semirigid cable works best.
3. Use the „Port Extension“ feature of your network analyzer to shift the refer-
ence plane of your network analyzer to the open end of the cable.
4. Connect the center-conductor of the cable to the solder pad of the pin „PA“
of the IC. The outer conductor has to be grounded. Very short connections
have to be used. Do not remove the IC or any part of the matching-compo-
nents!
5. Screw a 50 Ω dummy-load on the RF-I/O-SMA-connector
6. Be sure that your network analyzer is AC-coupled and turn on the power
supply of the IC. The TDK 5100 F must not be in Transmit-Mode.
7. Measure the S-parameter S11

Wireless Components 3 - 10 Target Specification, July 2003

 TDK 5100 F
Preliminary

Applications

T.b.d.

tbd.wmf

Figure 3-7 S-parameters of the load at the PA-output

Above you can see the measurement of the evalboard with a span of 100 MHz.
The evalboard has been optimized for 3 V. The load is about 550+j0 Ω at
the transmit frequency.
A tuning-free realization requires a careful design of the components within the
matching network. A simple linear CAE-tool will help to see the influence of
tolerances of matching components.
Suppression of spurious harmonics may require some additional filtering within
the antenna matching circuit. The total spectrum of a typical 50 Ω-Output
testboard can be summarized as:

Table 3-2
Frequency Output Power
434 MHz Testboard
Fundamental +5 dBm
Fund −13.56 MHz t.b.d.
Fund + 13.56 MHz t.b.d.

2nd harmonic t.b.d.

3rd harmonic t.b.d.

Wireless Components 3 - 11 Target Specification, July 2003

1 Reference

Contents of this Chapter

1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3.1 AC/DC Characteristics at 3V, 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3.2 AC/DC Characteristics at 2.1 V ... 4.0 V, -40°C ... +125°C. . . . . . . . . 1-5
 TDK 5100 F
Preliminary

Reference

1.1 Absolute Maximum Ratings

The AC / DC characteristic limits are not guaranteed. The maximum ratings

must not be exceeded under any circumstances, not even momentarily and
individually, as permanent damage to the IC may result.

Table 1-1
Parameter Symbol Limit Values Unit Remarks
Min Max
Junction Temperature TJ −40 +150 °C
Storage Temperature Ts −40 +125 °C
Thermal Resistance RthJA t.b.d. K/W
Supply voltage VS −0.3 +4.0 V
Voltage at any pin Vpins -0.3 VS + 0.3 V
excluding pin 9
Voltage at pin 9 Vpin9 -0.3 2 * VS V No ESD-Diode to
VS
Current into pin 4 Ipin4 -10 10 mA
ESD integrity, all pins VESD -1 +1 kV JEDEC Standard
JESD22-A114-B
ESD integrity, all pins VESD -2 +2 kV JEDEC Standard
excluding pin 9 JESD22-A114-B

Ambient Temperature under bias: TA = −40°C to +125° C

Note: All voltages referred to ground (pins) unless stated otherwise.
Pins 3 and 8 are grounded.

1.2 Operating Range

Within the operational range the IC operates as described in the circuit

description.

Table 1-2
Parameter Symbol Limit Values Unit Test Conditions
Min Max
Supply voltage VS 2.1 4.0 V
Ambient temperature TA -40 125 °C

Wireless Components 1-2 Target Specification, July 2003

 TDK 5100 F
Preliminary

Reference

1.3 AC/DC Characteristics

1.3.1 AC/DC Characteristics at 3V, 25°C

Table 1-3 Supply Voltage V S = 3 V, Ambient temperature Tamb = 25° C

Parameter Symbol Limit Values Unit Test Conditions
Min Typ Max
Current consumption
Power Down mode IS PDWN 0.3 100 nA V (Pins 10, 6 and 7)
< 0.2 V
PLL Enable mode IS PLL_EN 3.5 4.2 mA
Transmit mode 434 MHz IS TRANSM 7 mA
Output frequency
Output frequency fOUT 434 MHz fOUT = 32 * fCOSC
Clock Driver Output (Pin 1)
Output current (High) ICLKOUT 5 µA VCLKOUT = VS

Saturation Voltage (Low)1) VSATL 0.56 V ICLKOUT = 1 mA

FSK Switch Output (Pin 4)

On resistance RFSKOUT 250 Ω VFSKDTA = 0 V
On capacitance CFSKOUT 6 pF VFSKDTA = 0 V
Off resistance RFSKOUT 10 kΩ VFSKDTA = VS

Off capacitance CFSKOUT 1.5 pF VFSKDTA = VS

Crystal Oscillator Input (Pin 5)

Load capacitance CCOSCmax 5 pF
Serial Resistance of the crys- 100 Ω f = 13.56 MHz
tal
Input inductance of the 4.6 µH f = 13.56 MHz
COSC pin
ASK Modulation Data Input (Pin 6)
ASK Transmit disabled VASKDTA 0 0.5 V
ASK Transmit enabled VASKDTA 1.5 VS V
Input bias current ASKDTA IASKDTA 30 µA VASKDTA = VS

Input bias current ASKDTA IASKDTA -20 µA VASKDTA = 0 V

ASK data rate fASKDTA 20 kHz

Wireless Components 1-3 Target Specification, July 2003

 TDK 5100 F
Preliminary

Reference

Table 1-3 Supply Voltage V S = 3 V, Ambient temperature Tamb = 25° C

Parameter Symbol Limit Values Unit Test Conditions
Min Typ Max
FSK Modulation Data Input (Pin 7)
FSK Switch on VFSKDTA 0 0.5 V
FSK Switch off VFSKDTA 1.5 VS V
Input bias current FSKDTA IFSKDTA 30 µA VFSKDTA = VS

Input bias current FSKDTA IFSKDTA -20 µA VFSKDTA = 0 V

FSK data rate fFSKDTA 20 kHz
Power Amplifier Output (Pin 9)

Output Power2) at 434 MHz POUT434 5 dBm

transformed to 50 Ohm
Power Down Mode Control (Pin 10)
Power Down mode V PDWN 0 0.7 V VASKDTA < 0.2 V
VFSKDTA < 0.2 V
PLL Enable mode V PDWN 1.5 VS V VASKDTA < 0.5 V
Transmit mode V PDWN 1.5 VS V VASKDTA > 1.5 V
Input bias current PDWN IPDWN 30 µA VPDWN = V S

1) Derating linearly to a saturation voltage of max. 140 mV at ICLKOUT = 0 mA

2) Power amplifier in overcritical C-operation
Matching circuitry as used in the 50 Ohm-Output Testboard at the specified frequency.
Tolerances of the passive elements not taken into account.

Wireless Components 1-4 Target Specification, July 2003

 TDK 5100 F
Preliminary

Reference

1.3.2 AC/DC Characteristics at 2.1 V ... 4.0 V, -40°C ... +125°C

Table 1-4 Supply Voltage V S = 2.1 V ... 4.0 V, Ambient temperature T amb = -40° C ... +125° C
Parameter Symbol Limit Values Unit Test Conditions
Min Typ Max
Current consumption
Power Down mode IS PDWN 4 µA V (Pins 10, 6 and 7)
< 0.2 V
PLL Enable mode IS PLL_EN 3.5 4.6 mA
Transmit mode IS TRANSM 7 mA
Output frequency

Output frequency1) fOUT 434 MHz fOUT = 32 * fCOSC

Clock Driver Output (Pin 1)

Output current (High) ICLKOUT 5 µA VCLKOUT = VS

Saturation Voltage (Low)2) VSATL 0.5 V ICLKOUT = 0.6 mA

FSK Switch Output (Pin 4)

On resistance RFSKOUT 280 Ω VFSKDTA = 0 V
On capacitance CFSKOUT 6 pF VFSKDTA = 0 V
Off resistance RFSKOUT 10 kΩ VFSKDTA = VS

Off capacitance CFSKOUT 1.5 pF VFSKDTA = VS

Crystal Oscillator Input (Pin 5)

Load capacitance CCOSCmax 5 pF
Serial Resistance of the crys- 100 Ω f = 13.56 MHz
tal
Input inductance of the 4.6 µH f = 13.56 MHz
COSC pin
ASK Modulation Data Input (Pin 6)
ASK Transmit disabled VASKDTA 0 0.5 V
ASK Transmit enabled VASKDTA 1.5 VS V
Input bias current ASKDTA IASKDTA 33 µA VASKDTA = VS

Input bias current ASKDTA IASKDTA -20 µA VASKDTA = 0 V

ASK data rate fASKDTA 20 kHz

Wireless Components 1-5 Target Specification, July 2003

 TDK 5100 F
Preliminary

Reference

Table 1-4 Supply Voltage V S = 2.1 V ... 4.0 V, Ambient temperature T amb = -40° C ... +125° C
Parameter Symbol Limit Values Unit Test Conditions
Min Typ Max
FSK Modulation Data Input (Pin 7)
FSK Switch on VFSKDTA 0 0.5 V
FSK Switch off VFSKDTA 1.5 VS V
Input bias current FSKDTA IFSKDTA 33 µA VFSKDTA = VS

Input bias current FSKDTA IFSKDTA -20 µA VFSKDTA = 0 V

FSK data rate fFSKDTA 20 kHz
Power Amplifier Output (Pin 9)

Output Power 3) at 434 MHz POUT, 434 dBm VS = 2.1 V

transformed to 50 Ohm.
POUT, 434 5 dBm VS = 3.0 V

POUT, 434 dBm VS = 4.0 V

Power Down Mode Control (Pin 10)

Power Down mode V PDWN 0 0.5 V VASKDTA < 0.2 V
VFSKDTA < 0.2 V
PLL Enable mode V PDWN 1.5 VS V VASKDTA < 0.5 V
Transmit mode V PDWN 1.5 VS V VASKDTA > 1.5 V
Input bias current PDWN IPDWN 38 µA VPDWN = V S

1) a) When the minimum TA is increased by tbd.°C, the minimum fVCO decreases by 1 MHz.
b) When the maximum TA is decreased by tbd.°C, the maximum fVCO increases by 1 MHz.
c) When the minimum VS is increased by tbd. mV, the maximum fVCO increases by 1 MHz.
Restriction of c): The maximum fVCO must not be increased by more than tbd. MHz
by increasing V S.
All three measures can be taken independently and additive.

2) Derating linearly to a saturation voltage of max. 140 mV at ICLKOUT = 0 mA

3) Matching circuitry as used in the 50 Ohm-Output Testboard.

Tolerances of the passive elements not taken into account.
Range @ 2.1 V, +25°C: dBm +/- dBm
Typ. temperature dependency at 2.1 V: + dBm@-40°C and - dBm@+125°C, reference +25°C
Range @ 3.0 V, +25°C: 5.0 dBm +/- dBm
Typ. temperature dependency at 3.0 V: + dBm@-40°C and - dBm@+125°C, reference +25°C
Range @ 4.0 V, +25°C: dBm +/- dBm
Typ. temperature dependency at 4.0 V: + dBm@-40°C and - dBm@+125°C, reference +25°C

Wireless Components 1-6 Target Specification, July 2003