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Q1.Aclocking Resources

The document discusses clocking resources in 7 series FPGAs. It states that each I/O bank contains clock-capable input pins connected to internal clock sources like global, regional and I/O clock networks. Specifically, it notes there are 12 global clock networks, 4 regional clock networks, and 4 I/O clock networks per clock region.

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Parth Vibhandik
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36 views3 pages

Q1.Aclocking Resources

The document discusses clocking resources in 7 series FPGAs. It states that each I/O bank contains clock-capable input pins connected to internal clock sources like global, regional and I/O clock networks. Specifically, it notes there are 12 global clock networks, 4 regional clock networks, and 4 I/O clock networks per clock region.

Uploaded by

Parth Vibhandik
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Q1.

AClocking Resources

1. High Performance clocking:


Modern application has complicated clocking rquirements
Support for a wide frequency range and stability
De-skewing and aligning clocks
2. Each I/O bank contains clock-capable input pins to bring user clocks onto the 7 series FPGA
clock routing resources. In conjunction with dedicated clock buffers, the clock-capable input bring
user clocks on to:
•Global clock lines in the same top/bottom half of the device
•I/O clocks lines within the same I/O bank and vertically adjacent I/O banks
•Regional clock lines within the same clock region and vertically adjacent clock regions
•CMTs within the same clock region and, with limitations, vertically adjacent clock regions
3.Global clock Buffer
High fanout clock distribution buffer
4.Clock management tile(CMT)-frequency synthesis &filtering

Fpga 7 series has 4 clock capable inputs in each bank-These are regular I/O pins with dedicated
connections to the internal clock sources
Therefore Resources per clock region:

• 12 Global clock networks


• 4 regional clock networks
• 4 I/O clock networks
Q1 B
Randomization is the process of making something random; SystemVerilog randomization is the
process of generating random values to a variable. Verilog has a $random method for generating the
random integer values. This is good for randomizing the variables alone, but it is hard to use in case
of class object randomization. for easy randomization of class properties, SystemVerilog provides
rand keyword and randomize() method.

Random Variables:

• The class variables which get random values on randomization are called random variables
• There are two types of random variables; rand and randc. rand is the random variable
which gets any random value wheras randc is the cyclic random variable which gets
random values which are not repeated.

We use randomization for 2 reasons


1. In Very Large DUTs or Codes ,to reduce the time required to write the directed test case as
this reduces the number of test cases we may need write. One good random test case would
be good enough to test the design.
2. To hit the most worst-case scenarios which we may not have thought of or would be difficult
to hit with the directed case.

Example:
class packet;
rand bit [2:0] addr1;
randc bit [2:0] addr2;
endclass

module rand_methods;
initial begin
packet pkt;
pkt = new();
repeat(10) begin
pkt.randomize();//start randomization
$display("\taddr1 = %0d \t addr2 = %0d",pkt.addr1,pkt.addr2);
end
end
endmodule
Constrained randomization
Simply running ramdomized tests do not make sense because there will be many invalid cases and
in some situations it is required to control the values getting assigned on randomization, this can be
achieved by writing constraints. By writing constraints to a random variable, the user can get
specific value on randomization. constraints to a random variable shall be written in constraint
blocks.
Eg: rand bit [1:0] mode;
constraint c_mode1 { mode < 3; }

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