WORKBOOK

FOR
MICROPROCESSORS
AND
MICROCONTROLLERS
(Paper code – CS502)
B. Tech CSE 3rd Year (5th semester)
Faculty Name: - Souvik Saha

Name: -_________________________________________________
Enrolment Number: -______________________________________
Class: -__________________________________________________
Section: -________________________________________________
Batch: -_________________________________________________

Department of Electronics and Communication Engineering

UNIVERSITY OF ENGINEERING & MANAGEMENT, JAIPUR
Title of Course: Microprocessors and Microcontrollers

Course Code: CS502

L-T Scheme: 3-1

Course Credits: 3

Introduction:
Microprocessors are used extensively in the design of any computing facility. It contains units
to carry out arithmetic and logic calculations, fast storage in terms of registers and associated
control logic to get instructions from memory and execute them. A number of devices can be
interfaced with them to develop a complete system application. On the other hand,
microcontrollers are single chip computers, integrating processor, memory and other
peripheral modules into a single System-on-Chip (SoC). Apart from input-output ports, the
peripherals often include timers, data converters, communication modules, and so on. The
single chip solution makes the footprint of the computational element small in the overall
system package, eliminating the necessity of additional chips on board. However, there exists
a large range of such products. While the simpler microcontrollers are cheap, their capabilities
(in terms of program size and analog and digital peripherals) are also limited. Such processors
may be suitable for small applications. Microcontrollers like 8051, PIC belong to this category.
On the other hand, advanced microcontrollers are often much more powerful, comparable to
the very advanced microprocessors. The AVR and ARM processors are of this category.

Objectives:
This subject will start with a discussion on a simple microprocessor, 8085. Understanding this
architecture is the basis to follow any other complex CPU architecture. It will be followed by
a complete overview of a range of microcontrollers covering 8051, PIC, AVR and ARM. The
hardware intricacies of these processors and their programming will be covered. Different
system design examples built around these processors will also be elaborated.
Learning Outcomes:
Knowledge:
Once the student has successfully completed this course, he/she will be able to answer the
following questions or perform following activities:
a. Students will be able to understand components of the computers, microprocessors and
microcontrollers.
b. Students will be able to understand 8085, 8086, 8051, PIC, AVR and ARM processors,
their addressing modes, registers and instruction sets and writing program in assembly.
c. Students will be able to debug their assembly language programs.
d. Students will be able to program in embedded C.
e. Students will be able to design memory systems, design memory system layout and
analyse timing and electrical compatibility of the memory units.
f. Students will be able to use different kind of mini and major project.

Reference Books: -

1. R. Gaonkar, “Microprocessor Architecture, Programming and Applications with the 8085”,

Prentice Hall, 2014.
2. M.A. Mazidi, R.D. McKinlay, J.G. Mazidi, “The 8051 Microcontroller: A Systems Approach”,
Pearson, 2013.
3. M.Bates, “PIC Microcontrollers”, Newnes, 2011.
4. M.A. Mazidi, S. Naimi, S. Naimi, “The AVR Microcontroller and Embedded Systems: Using
Assembly and C”, Prentice Hall, 2011.
5. W.A. Smith, “ARM Microcontroller Interfacing: Hardware and Software, Eketor, 2010.
Course Contents:

Module 1:
Overview of microcomputer systems and their building blocks, memory interfacing, concepts of
interrupts and Direct Memory Access, instruction sets of microprocessors (with examples of 8085 and
8086);
Module 2:
Interfacing with peripherals - timer, serial I/O, parallel I/O, A/D and D/A converters; Arithmetic
Coprocessors; System level interfacing design;

Module 3:

Concepts of virtual memory, Cache memory, Advanced coprocessor Architectures- 286, 486, Pentium;
Microcontrollers: 8051 systems,

Module 4:

Introduction to PIC controller; AVR, ARM processor.

Module 5:
Peripheral Interfacing: - 8255, 8257and 8259 (with 8085).
 Introduction of Basic Computer Organization
1. A processor has the size of its Read Only Memory (ROM) to be 8kB. If ROM chips of
size 1kb are only available, how many such chips are required to realize the ROM of
the processor? Also, what is the minimum number of address lines required to realize
the ROM? (Notation: b – bit, B – Byte)
a. 64, 13
b. 8, 13
c. 8, 8
d. 64, 8

Ans: -

2. A processor has a memory address range of 00000H – 3FFFFH. If the processor has
a read-only memory (ROM) of size 64k bytes with a starting address of 0000H, and
assuming that it is mapped onto a 2-fold folding addressing scheme, determine the
range, as well as the size, of the remaining memory in the processor. Also, determine
the number of address lines in the processor.

a. 20000H – 3FFFFH, 128k bytes, 17

b. 10000H – 3FFFFH, 192k bytes, 18
c. 10000H – 3FFFFH, 192k bytes, 17
d. 20000H – 3FFFFH, 128k bytes, 18
Ans: -
3. An 8-bit positive edge-triggered register in a processor has the following timing
diagram. Determine the value of parallel_out when the logic of output_enable is
HIGH. The values of parallel_in are mentioned in hexadecimal number system.

a. 8FH
b. 83H
c. A1H
d. A7H
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4. Which of the following sequence of operations conforms to an instruction cycle?

a. Execute, Fetch, Decode
b. Fetch, Execute, Decode
c. Decode, Fetch, Execute
d. Fetch, Decode, Execute

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5. An 8-bit processor has a 16-bit program counter (PC), whose value points to the
memory address of 00FFH. If the sizes of the instructions ADD, MOV, and LDI are 4-
byte, 2-byte, and 1-byte respectively, determine the value of the PC of the following
sequence of instructions after each and every instruction.
ADD A, #3F
MOV R0, A
LDI 00H
a. 0400H, 0600H, 0700H
b. 0103H, 0105H, 0106H
c. 04FFH, 06FFH, 07FFH
d. 0104H, 0106H, 0107H
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6. The number range in the decimal number system that can be represented using a 6
bit 2’s complement representation is
a. -31 to 31
b. -32 to 32
c. -32 to 31
d. -31 to 32

Ans: -
7. The following circuit implements which of the following statements

a. Y=A+B
b. Y=A+B+1
c. Y = A - B in 1's Complement Method
d. Y = A - B in 2's Complement Method

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8. Determine which of the following solutions of x and y satisfies the following
expressions.
(23) base x = (43) base y and (23) base y = 15
a. x = 12, y = 6
b. x = 14, y = 7
c. x = 16, y = 6
d. x = 10, y = 5

Ans: -

9. Which of the following expressions represents the expression of Y with minimum

number of literals?

a. C'
b. AC'+ A'C
c. A'
d. A'C'+ AC

Ans: -
10. Which of the following expressions represents the expression of Y with minimum
number of literals?

a. A'C' + AC
b. C
c. AC' + A'C
d. A'

Ans: -
11. Determine the equivalent Boolean expressions of the following multiplexer logic
circuits.

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12. The counter shown below is initially set to 1 (thus, Q1Q0=11). Neglecting the propagation
delays, determine the value of Q1Q0 after five pulses of the clock signal. [Left flip-flop’s
signals have the subscript 0 and right flip-flop’s signals have the subscript 1.]

a. Q1Q0=00
b. Q1Q0=01
c. Q1Q0=10
d. Q1Q0=11

Ans: -
13. he following logic circuit corresponds to which arithmetic circuit?

a. Full Subtractor
b. Two Half Subtractors
c. Two Half Adders
d. Full Adder

Ans: -
14. Which of the following statements is TRUE regarding the directionality of the buses
on a microprocessor that has the following composition:
A0-A7: Dedicated Address Bus
A8-A11: Multiplexed Address/Data Bus
D0-D3: Dedicated Data Bus?
a. A0-A7: Unidirectional, A8-A11: Unidirectional, and D0-D3: Bidirectional
b. A0-A7: Bidirectional, A8-A11: Unidirectional, and D0-D3: Bidirectional
c. A0-A7: Bidirectional, A8-A11: Bidirectional, and D0-D3: Unidirectional
d. A0-A7: Unidirectional, A8-A11: Bidirectional, and D0-D3: Bidirectional

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15. A microprocessor has a 16-bit address bus A15–A0, where A15 is the MSB and A0 is
the LSB, and a 64KB of memory. Unfortunately, two address lines, namely A13 and
A6 have become faulty and are stuck at logic 0. In such a situation, which of the
following address locations cannot be accessed in the memory?
a. None of the others
b. 0000H
c. 1F1FH
d. 1FFFH

Ans: -
 Introduction of 8085

1. After the execution of the instruction XRA A the contents of A, carry and zero flags are
respectively
a. A = 00, CY = 0, Z = 1
b. A = 00, CY = 0, Z = 0
c. A = 00, CY = 1, Z = 0
d. A = 00, CY = 1, Z = 1

Ans: -

2. The content of the accumulator after the execution of the following set of instructions is

MVI A, 95
ANI F0H
RLC
RLC
RLC
RLC
a. 05
b. 09
c. 90
d. 50

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3. How many times will the following loop be executed?

XRA A
MVI C, 05H
LOOP: DCR C
JNZ LOOP

a. Depends on the initial value of A

b. Infinite times
c. Once
d. Five times

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4. What is the status of the ZERO flag and the contents of the accumulator after the execution
of the following 8085 assembly code? Assume that contents of all other registers and
memory locations are unknown.

MOV A, 65H
MOV B, 32H
CMP B
a. 0, 65H
b. 1, 65H
c. 0, 00H
d. 1, 00H

Ans: -
5. How many bytes does the following set of instructions occupy?

MVI A, 35H
MVI B, 23H
ADD B
a. Three bytes
b. Six bytes
c. Five bytes
d. Four bytes

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6. Determine the instruction, as well as its starting address, for the following timing diagram.

Ans: -
7. What will be the contents of the registers A, B, and C, respectively, after the execution of the
following 8085 program?

MVI C, 03H
LXI H, 2000H
MOV A, M
DCR C
L1: INX H
MOV B, M
CMP B
JNC L2
MOV A, B
L2: DCR C
JNZ L1
STA 2100H
HLT

Contents of the memory locations are as follows.

2000H: 18H
2001H: 10H
2002H: 2BH

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8. If an 8085 microprocessor works at a frequency of 1 MHz, determine the total delay of the
following sequence of instructions (in seconds).

MVI A, 0FH
MVI B, 0FH
L1: DCR B
JNZ L1

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9. With respect to an 8085 microprocessor, match column X with column Y.

Column X Column Y
1. INTR 1. Non-maskable
2. RST 5.5 2. Maskable
3. TRAP 3. Software
4. RST 1 4. Non-vectored
a. X1-Y2, X2-Y1, X3-Y4, X4-Y3
b. X1-Y4, X2-Y2, X3-Y1, X4-Y3
c. X1-Y3, X2-Y2, X3-Y4, X4-Y1
d. X1-Y1, X2-Y4, X3-Y2, X4-Y3

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10. What does the following set of instructions do in an 8085 microprocessor?

EI
MVI A, 08H
SIM

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11. In a 8085 processor, suppose the DE register pair contains value 2. In the following code,
how many times is the JNZ instruction executed?
...
...
LOOP: DCX D
JNZ LOOP

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12. In 8085 processor, suppose the D register contains value 2. In the following code, how many
times is the JNZ instruction executed?
LOOP: DCR D
JNZ LOOP
Ans: -
 Introduction of 8051
1. With respect to an 8051 microcontroller, match Column X with Column Y.

Column X Column Y

1. MOV A, #25H 1. Indexed Addressing Mode

2. MOV R6, A 2. Register Indirect Addressing Mode

3. MOV 56H, A 3. Register Addressing Mode

4. MOV @R0, A 4. Direct Addressing Mode

5. MOVC A, @A+DPTR 5. Immediate Addressing Mode

a. X1 – Y1, X2 – Y2, X3 – Y3, X4 – Y4, X5 – Y5

b. X1 – Y2, X2 – Y3, X3 – Y4, X4 – Y5, X5 – Y1
c. X1 – Y5, X2 – Y3, X3 – Y4, X4 – Y2, X5 – Y1
d. X1 – Y5, X2 – Y4, X3 – Y3, X4 – Y2, X5 – Y1

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2. If CY = 1, A = 95H, and B = 4FH prior to the execution of “SUBB A, B”, what will be the
contents of A after the subtraction?

Ans: -
3. The instruction ‘MOV A, #36H’ is followed by the instruction ‘RR’ 354 times. What will be the
contents of the register A after the 8085 microcontroller executes the above set of
instructions?

Ans: -

4. Which of the following flags are affected by the instruction ‘DIV AB’ of an 8051
microcontroller?

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5. What can one infer from the instruction ‘MOV TMOD, #02H’ in an 8051 microcontroller?

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6. What will be the contents of the registers R5 and R6 after the following instructions are
executed?
MOV DPTR, #23FF H
MOV R5, DPL
MOV R6, DPH

Ans: -
7. What will be the address of the memory location whose contents will be present in the
Accumulator after the following set of instructions are executed?
MOV DPTR, #2004H
MOV A, #4
MOVC A, @A + DPTR

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8. MOV SP, #0X50

PUSH 0X20
PUSH 0X35
POP 0X30
PUSH 0X24
POP 0X40
Which of the following is true?

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9. What is the value of the bits 4-7 of R0 after the following set of instructions are executed?
MOV @R0, #04H
MOV A, #11H
XCHD A, @R0

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10. The following program generates a square wave on pin P1.5 Using timer 1. Find the
frequency. Consider XTAL = 11.0592 MHz.
MOV TMOD, #10H
AGAIN: MOV TL1, #26H
MOV TH1, #71H
SETB TR1
BACK: JNB TF1, BACK
CLR TR1
CPL P1.5
CLR TF1
SJMP AGAIN

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11. Assuming XTAL = 11.0592 MHz, which of the following program will generate a square wave
of 100 Hz frequency on pin P2.3.
a. MOV TMOD, #10H
AGAIN: MOV TL1, #00H
MOV TH1, #DCH
 SETB TR1
BACK: JNB TF1, BACK
CLR TR1
CPL P2.3
CLR TF1
SJMP AGAIN
b. MOV TMOD, #10H
AGAIN: MOV TL1, #00H
MOV TH1, #DEH
SETB TR1
BACK: JNB TF1, BACK
CLR TR1
CPL P2.3
CLR TF1
SJMP AGAIN

c. MOV TMOD, #10H

AGAIN: MOV TL1, #00H

MOV TH1, #EEH
SETB TR1
BACK: JNB TF1, BACK
CLR TR1
CPL P2.3
CLR TF1
SJMP AGAIN
d. MOV TMOD, #10H
AGAIN: MOV TL1, #FFH
MOV TH1, #EEH
SETB TR1
BACK: JNB TF1, BACK
CLR TR1
CPL P2.3
CLR TF1
SJMP AGAIN
Ans: -
12. What is the default interrupt priority in 8051?
a. INT0 > TF0 > RI + TI > INT1 > TF1
b. INT01 > TF1 > RI + TI > INT0 > TF0
c. INT0 > TF0 > INT1 > TF1 > RI + TI
d. INT1 > TF1 > INT0 > TF0 > RI + TI

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13. Which bits in the PCON register of an 8051 microcontroller correspond to the idle and
power-down modes?
a. PCON.0 – Idle mode, PCON.1 – Power-down mode
b. PCON.1 – Idle mode, PCON.0 – Power-down mode
c. PCON.0 – Idle mode/Power-down mode
d. PCON.1 – Idle mode/Power-down mode

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14. Determine the contents of the top of the stack and the value of the stack pointer (SP) after
the following instructions are executed in an 8051.

MOV SP, #6FH

MOV R1, #10H
MOV R6, #0FH
MOV 3, #03H
MOV 2, #FFH
PUSH 3
 PUSH 2
PUSH 1
PUSH 6
a. SP = 74H, Top of the stack = 03H
b. SP = 73H, Top of the stack = 03H
c. SP = 74H, Top of the stack = 0FH
d. SP = 73H, Top of the stack = 0FH

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15. How many times the instruction CPL A is executed in the following program of an 8051?

MOV A, #F0H
MOV R1, #60
NEXT: MOV R6, #10H
AGAIN: CPL A
DJNZ R6, AGAIN
DJNZ R1, NEXT
a. 600 times
b. 900 times
c. 690 times
d. 960 times

Ans: -
16. Which among the below mentioned program segments represent the code of an 8051?
a. MOV SP, #54H
MOV TCON, #00100000C
SETC ET1
SETC TR0
SJMP $
b. MOV SP, #54H
MOV TMOD, #00100000C
SETC ET0
SETC TR0
SJMP $
c. MOV SP, #54H
MOV TMOD, #00100000C
SETC ET1
SETC TR1
SETC EA
SJMP $
d. MOV SP, #54H
MOV TMOD, #00100000C
SETC ET0
SETC TR1
SETC EA
SJMP $

Ans: -
17. Which among the below mentioned sequence of program instructions represent the correct
chronological order for the generation of 2 kHz square wave frequency in an 8051?
1. MOV TMOD, #00000010B
2. MOV TL0, #06H
3. MOV TH0, #06H
4. SETB TR0
5. CPL P1.0
6. ORG 0000H

a. 6, 5, 2, 4, 1, 3
b. 6, 1, 3, 2, 4, 5
c. 6, 5, 4, 3, 2, 1
d. 6, 2, 4, 5, 1, 3

Ans: -
 Introduction of PIC, AVR and ARM processor
1. ARM was originally known as
a. Acron RISC Machine
b. Advanced RISC Machine
c. Ashton Raggatt McDougall
d. Automatic RISC Machine

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2. Which of the following ARM instructions is same as multiplying the contents of r0 by nine
and storing the product in r7?
a. ADD r0, r7, r7, LSL #3
b. ADD r0, r7, r0, LSL #3
c. ADD r7, r7, r0, LSL #3
d. ADD r7, r0, r0, LSL #3

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3. Which of the following instructions corresponds to a Multiply Accumulate instruction in ARM

architecture?
a. MUL
b. UMULL
c. SMULL
d. SMLAL

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4. Which of the following instructions corresponds to loading a signed half word in ARM
architecture?
a. LDR
b. LDRS
c. LDRSH
d. LDRH
Ans: -

5. Which of the following instructions corresponds to storing a signed byte in ARM

architecture?
a. STR
b. STRSB
c. STRB
d. STRSH

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6. ARM10TDMI is a
a. 3-stage pipeline processor
b. 5-stage pipeline processor
c. 6-stage pipeline processor
d. 8-stage pipeline processor

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7. ARM instruction set supports

a. Multiple load/store instruction that allows to load/store up to 4 registers at once
b. Multiple load/store instruction that allows to load/store up to 8 registers at once
c. Multiple load/store instruction that allows to load/store up to 16 registers at once
d. Multiple load/store instruction that allows to load/store up to 32 registers at once

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8. When a procedure call is made in ARM, the return address is automatically placed into
a. Program Counter (r15)
b. Link Register (r14)
c. Stack Pointer (r15)
d. Stack Pointer (r13)

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9. In which of the following modes of an ARM processor, CPSR cannot be modified?

a. Fast Interrupt Processing (FIQ) mode
b. Normal Interrupt Processing (IRQ) mode
c. User mode
d. Supervisor (SVC) mode

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10. Which of the following is a valid multiplication (not multiply accumulate) instruction in ARM
architecture?
a. MUL r15, r0, r3
b. MLA r1, r1, r6
c. MUL r10, r2, r5
d. MLA r10, r2, r1, r5

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11. The address range and the capacity of the data memory, respectively, of a PIC18F452
microcontroller are
a. Address Range: 00H – FFH, Capacity: 256 bytes
b. Address Range: 00H – FFH, Capacity: 4096 bytes
c. Address Range: 000H – FFFH, Capacity: 256 bytes
d. Address Range: 000H – FFFH, Capacity: 4096 bytes

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12. he widths of the address buses for program (APM) and data (ADM) memory, respectively, of
the PIC18F family of microcontrollers are
a. APM: 21 bits, ADM: 21 bits
b. APM: 21 bits, ADM: 12 bits
c. APM: 12 bits, ADM: 21 bits
d. APM: 12 bits, ADM: 12 bits

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13. The widths of the data buses for program (DPM) and data (DDM) memory, respectively, of
the PIC18F family of microcontrollers are
a. DPM: 8 bits, DDM: 8 bits
b. DPM: 8 bits, DDM: 16 bits
c. DPM: 16 bits, DDM: 8 bits
d. DPM: 16 bits, DDM: 16 bits

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14. Which of the following input/output (I/O) pins in a PIC18F microcontroller can also be
configured with Capture2 input/Capture2 output/PWM output (CCP2) functionality?
a. RB3
b. RB2
c. RA3
d. RA2

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15. Which of the following features are correctly mentioned with respect to an AVR AT90S2313
microcontroller?
a. 2K bytes of In-System Programmable Flash, 128 bytes SRAM
b. 2K bytes of In-System Programmable Flash, 256 bytes SRAM
c. 4K bytes of In-System Programmable Flash, 128 bytes SRAM
d. 4K bytes of In-System Programmable Flash, 256 bytes SRAM

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16. Which of the following represents the correct combination of X-, Y-, and Z-registers in an
AVR microcontroller (<A, B> denotes concatenation of the registers A and B, where A is the
higher byte register and B is the lower byte register)?
a. X-register: <R27, R26>, Y-register: <R29, R28>, Z-register: <R30, R31>
b. X-register: <R27, R26>, Y-register: <R28, R29>, Z-register: <R31, R30>
c. X-register: <R27, R26>, Y-register: <R29, R28>, Z-register: <R31, R30>
d. X-register: <R26, R27>, Y-register: <R29, R28>, Z-register: <R31, R30>

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17. Which of the following statements is TRUE with respect to an ARM processor?
a. ARM has higher code density compared to THUMB
b. THUMB code uses up to 30% more power than ARM code
c. THUMB code, on an average, requires 30% less space
d. THUMB has three address formats

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18. Which of the following combinations should be used for the best cost and power efficiency,
with respect to an ARM processor?
a. 16-bit memory and ARM instruction set
b. 32-bit memory and ARM instruction set
c. 16-bit memory with THUMB code
d. 32-bit memory with THUMB code

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19. Which of the following representations related to the AVR microcontrollers is correct?
a. Timer/Counter 0 is an 8-bit up counter and timer/counter 1 is an 8-bit up counter
b. Timer/Counter 0 is an 8-bit up counter and timer/counter 1 is a 16-bit up counter
c. Timer/Counter 0 is a 16-bit up counter and timer/counter 1 is an 8-bit up counter
d. Timer/Counter 0 is a 16-bit up counter and timer/counter 1 is a 16-bit up counter

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20. Which of the following represents the best description of an AVR timer/counter source
when CS02 = 0, CS01 = 1, and CS00 = 1?
a. Stop, the timer/counter is stopped
b. CPU frequency is divided by 8 (CK/8)
c. CPU frequency is divided by 64 (CK/64)
d. CPU frequency is divided by 256 (CK/256)

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21. Which of the following is the Program Address of the Serial Transfer Complete interrupt in
an AVR microcontroller?
a. $000
b. $00C
c. $012
d. $014

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 Introduction of Interfacing device with 8085

1. Why interface chips are necessary in a microcontroller-based system?

a. To resolve the speed problem
b. To synchronize the data transfers between the CPU and the I/O device
c. To synchronize the data transfers between the CPU and the I/O device, as well as to
resolve the speed problem
d. None of the given options

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2. With respect to 8255 Programmable Peripheral Interface (PPI), which of the following
statement(s) are correct?
1. Mode 0: Any port can be used as input/output ports.
2. Mode 1: Both Port A and B can be used as input/output ports.
3. Mode 2: Port B can be used either in Mode 0 or Mode 1.
a. Only 1 is correct.
b. Only 2 is correct.
c. Only 3 is correct.
d. All 1, 2 and 3 are correct.

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3. Find the control word of the 8255 for resetting BIT 7 of Port C.
a. 00001111
b. 10001111
c. 00001110
d. 10001110

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4. To get 6 displayed by a 7 Segment display, what should be the combination of 8051 pins
(P1.7 – P1.0)?
a. 01111101
b. 10111110
c. 01111111
d. 01100000

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5. Which of the following is the correct combination to select Port A in an 8255 chip?
a. CS = 0, A1 = 0, A0 = 0
b. CS = 0, A1 = 0, A0 = 1
c. CS = 0, A1 = 1, A0 = 0
d. CS = 1, A1 = 0, A0 = 0

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 Introduction of 8086

1. Which of the following statement(s) is/are correct?

a. If MN/MX’ is low, 8086 cannot be associated with any co-processor.
b. If MN/MX’ is low, 8086 can be associated with any co-processor.
c. If MN/MX’ is low, 8086 is in Maximum Mode.
d. If MN/MX’ is high, 8086 is in Minimum Mode.

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2. How many 16-bit Segment Registers does 8086 have?

a. 4
b. 8
c. 2
d. 6

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3. The 8086 microprocessor is operating in Maximum Mode. If the outputs of the status signals
(S2’, S1’, S0’) equals to 001, which CPU cycle is being performed?
a. I/O Read
b. I/O Write
c. Read Memory
d. Write Memory

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4. In 8086, the address bus is __________ bits wide.
a. 20
b. 16
c. 12
d. 10

Ans: -

5. Match the following.

(A) CF (i) Carry Flag
(B) SF (ii) Conditional Flag
(C) OF (iii) Service Flag
(D) IF (iv) Sign Flag
(v) Overflow Flag
(vi) Over Flag
(vii) Initial Flag
(viii) Interrupt Flag
a. A (i), B (iv), C (v), D (viii)
b. A (ii), B (iv), C (vi), D (vii)
c. A (i), B (iii), C (v), D (vii)
d. A (ii), B (iii), C (vi), D (viii)

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6. Which of the following address lines in an 8086 microprocessor are multiplexed with status
signals?
a. A19 – A15
b. A19 – A16
c. A14 – A11
d. A3 – A0

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7. Which of the following pins in an 8086 microprocessor are multiplexed with data and
address signals?
a. AD15 – AD0
b. AD19 – AD0
c. AD19 – AD1
d. AD19 – AD4

Ans: -