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1) Alan Thelliyil Augustine graduated from Indian Institute of Technology Madras in 2018 with a B Tech in Electrical Engineering and a minor in Maths for Computer Science, achieving an 8.75 CGPA. 2) He had internships at NVIDIA and CEWiT IIT Madras Research Park where he worked on projects related to test log parsing, GUI applications, and path loss modeling. 3) His projects at IIT Madras included hardware implementation of DCT algorithm and behavioral modeling of a cache coherency protocol.

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118 views2 pages

Core 1

1) Alan Thelliyil Augustine graduated from Indian Institute of Technology Madras in 2018 with a B Tech in Electrical Engineering and a minor in Maths for Computer Science, achieving an 8.75 CGPA. 2) He had internships at NVIDIA and CEWiT IIT Madras Research Park where he worked on projects related to test log parsing, GUI applications, and path loss modeling. 3) His projects at IIT Madras included hardware implementation of DCT algorithm and behavioral modeling of a cache coherency protocol.

Uploaded by

Ridhi
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Alan Thelliyil Augustine | EE14B006

Indian Institute of Technology Madras

EDUCATION
Program Institution %/CGPA Year of completion
B Tech in Electrical
Indian Institute of Technology Madras, Chennai 8.75 2018
Engineering
(Minor in Maths for
Computer Science)
XII Marygiri Senior Secondary School, (CBSE) 94.6 2013
X Ursuline English Medium School, (CBSE) 10 2011
SCHOLASTIC ACHIEVEMENTS
 All India Rank 403 in JEE ADVANCED 2014.
 All India Rank 529 in JEE MAIN 2014 with state rank 6.
 Secured 7th rank in Kerala State Engineering Entrance Examination 2014 (among 100,000 candidates).
PROFESSIONAL EXPERIENCE
 VIDIA Internship (May 2017 –July 2017)
 Created Test-Log Parser Framework by creating a python application
 Optimised a parsing python script, achieved an speed up of 270x.
 Created a GUI application for launching regression.
 Updated and replaced the attributes in the map file.
 Internship at CEWiT ,IIT Madras Research Park (May 2016-July 2016)
 Worked in a team of five, on the problem of path loss modelling for 2G frequency signals.
 Developed an android application which acquires different parameters for path loss measurement.
 Analysed the data collected, using MATLAB and fitted the data to a path loss equation.
 Modelled path loss for rural areas just outside of Chennai
PROJECTS
 Mapping Signal Processing Algorithms to DSP Architectures Project ( March 2017-April 2017)
 Hardware implementation of DCT algorithm in Zybo board and performed software hardware comparison
achieved a speedup of 7.5 with a maximum error of 0.04%.
 C code for DCT written in Vivado HLS. Optimisations in addition, multiplication, memory access as well as
directives were added so as to get the maximum throughput.
 Code was synthesised and exported as ip and connected to Zynq processor, along with a timer module for
performing the HW/SW comparison.
 Digital Design Verification Project (Feb 2017-April 2017)
 Implemented the behavioural modelling of MESI cache coherency protocol for a 3 core processor with private
L1 cache for each core and a shared L2 cache; in Verilog.
 Wrote properties for checking the correctness of the design, identified bugs in the code, and ensured correctness
of the design.
RELEVANT COURSE WORKS
 Computational Engineering  Digital Signal Processing
 Computer Organization  GPU Programming*
 Combinational Optimization  Computer Aided Design(C and Scientific Python)
 Computer Organisation and Architecture  Communication Systems
 Data Structures and Algorithms  Networks and Systems
SKILLS SET
 Programming Skills : C, C++, Python, Verilog,  Skilled in algorithmic programming
MATLAB (Hackerrank Points: 1713.55)
 Tools: Vivado HLS, SDK.  Operating Systems: Windows, Ubuntu
POSITIONS OF RESPONSIBILITY
 Mentor under Mitr(SAC approved Student Body ) (2015-2016)
 Contributed towards organising Mitr activities for freshmen. 
 Provided guidance to a group of 8 first year students on various academic and extra-curricular activities.
 Shaastra Finance Coordinator (2015-2016)
 Worked in a team of five, ensured the timely delivery of money to the vendors.
 Contacted vendors for getting quotations for T-shirts and merchandise.
EXTRA-CURRICULAR ACTIVITIES
 Active participant in basketball schroeter (inter hostel sports competition).
  Represented hostel in the first, second and third year for schroeter 
 Regional Coordinator, Tensors 2016, mock entrance exam for JEE aspirants conducted by students of IITM in
helping students familiarising with the exam.

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