JK Flip-Flop

JK flip – flop is named after Jack Kilby, the electrical engineer who invented IC.

A JK flip – flop is called a Universal Programmable flip – flop because, using its inputs J, K
Preset and Clear, function of any other flip – flop can be imitated.

A JK flip – flop is the modification of SR flip – flop with no illegal state. In this the J input is
similar to the SET input of SR flip – flop and the K input is similar to the RESET input of SR
flip – flop.

The symbol of JK flip – flop is shown below.

JK flip flop Logic Diagram

JK flip – flop logic diagram is shown in the below figure. Logic diagram consists of three
input NAND gates replacing the two input NAND gates in SR flip – flop and the inputs are
replaced with J and K from S and R.

The design of the JK flip – flop is such that the three inputs to one NAND gate are J, clock
signal along with a feedback signal from Q’ and the three inputs to the other NAND are K,
clock signal along with a feedback signal from Q. This arrangement eliminates the
indeterminate state in SR flip – flop.
Truth Table

Operation
 Case 1 : When both the inputs J and K are LOW, then Q returns its previous state
value i.e. it holds the previous data.
When we apply a clock pulse to the J K flip flop and the J input is low(0) then irrespective of
the other NAND gates, the NAND gate-1 output becomes HIGH(1). In the same manner, if
the K input is low(0) then output of NAND gate-2 is also HIGH(1). So thus the output
remains in the same state i.e. no change in the state of flip flop.

 Case 2 : When J is LOW and K is HIGH, then flip flop will be in Reset state i.e. Q
= 0, Q’ = 1.
When we apply a clock pulse to the J K flip flop and the inputs are J is low and K is high the
output of the NAND gate connected to J input becomes 1. Then Q becomes 0. This will reset
the flip flop again to its previous state. So the Flip flop will be in RESET state.
  Case 3 : When J is HIGH and K is LOW, then flip – flop will be in Set state i.e. Q
= 1, Q’ = 0
When we apply a clock pulse to the J K flip flop and the inputs are J is high and K is low the
output of the NAND gate connected to K input becomes 1. Then Q’ becomes 0. This will set
the flip flop with the high clock input. So the Flip flop will be in SET state.

 Case 4 : When both the inputs J and K are HIGH, then flip – flop is in Toggle
state. This means that the output will complement of the previous state.
Truth Table
The truth table of JK flip – flop is shown below.

Race around condition of JK Flip Flop

For high inputs of J K flip flop, only the lower NAND gates are triggered by the outputs that
are compliment to each other i.e Q and Q’. So while high inputs are connected to flip – flop,
at any instant, one gate is enabled and other gate will be disabled. If the upper gate is in
disabled state, it will drive the flip flop to SET state, later when the lower gate is enabled, it
will drive the flip flop to RESET state which causes the toggling of output. This will cause
the Race around condition in J K flip – flop.

Steps to avoid racing condition

1. We can avoid the Race around condition by setting up the clock-on time less than the
propagation delay of the flip flop. It can be achieved by edge triggering.
2. By making the flip flop to toggle over one clock period. This concept is introduced in
Master Slave J K flip flop.

Master-Slave JK Flip Flop

The Master-Slave J K Flip flop is a “Synchronous” device which allows the data to pass with
the timing of the clock signal. A master – slave flip flop consists of two clocked flip – flops
connected in series, which isolate the input from output and hence the terminology “master –
slave”. Apart from eliminating the race around problem in normal JK flip – flops, a master –
slave JK flip – flop can also imitate the functions of SR flip – flop, clocked flip – flop, D flip
– flop and Toggle flip – flop. The Q and Q’ outputs of the slave flip – flop are fed back to the
master flip – flop while the outputs of the master flip – flop are connected as one of the inputs
to the slave flip – flop.
When the clock input is high, the master is active and the slave is inactive. Depending on the
inputs, the output of the master flip – flop is set or reset and the output of the slave flip flop is
not changed and so it remains in previous state. As the slave flip flop become active at low
clock input, the outputs of slave flip – flop changes. When the clock is high, the output of the
master flip – flop are put on hold as the slave is inactive during this period. When the clock is
low, the output of the master flip – flop are seen by the slave flip – flop and pass them to the
output. The output of the slave flip flop is the final output of the Master – Slave flip – flop.
The final output is available at the end of the clock pulse.

Construction
A master slave JK flip – flop is a cascaded combination of two SR flip – flops with the
feedbacks from output of the slave to the input of the master. The circuit of master – slave
flip – flop is shown below

Positive clock pulses are applied to the master flip flop and they are inverted before applying
to slave i.e. master flip – flop is active during positive transition while slave flip – flop is
active during negative transition. During the positive edge of the clock, the data from inputs J
and K are passed to the master flip – flop and are held there till the occurrence of negative
edge transition of the clock. Then the data or information is passed to the slave flip – flop,
here the output is collected.

The symbolic representation of a master – slave JK flip – flop with two JK flip – flops is
shown below.
The truth table of master – slave JK flip – flop along with preset and clear inputs is shown
below.

When the clock input is low, and the two inputs of master flip flop i.e. J and K inputs will
have no effect on the output of Master Slave flip flop.

When the clock input is high

 If J is low & K is low: No change in state.

 If J is low & K is high: Master Slave flip flop will be in reset state.
 If J is high & K is low: Master Slave flip flop will be in set state.
 If J is high & K is high: Toggled state.

Timing Diagram
The width of the input pulse may be less or more than the propagation delay of the flip flop, it
doesn’t affect the output state. But the value of J and K inputs at the instance of positive edge
of clock will affect the output state of master – slave flip – flop provided the setup and hold
time are not violated.

Applications
JK flip – flops are one of the most widely used flip – flops in digital electronics. This is
because of their universal programmable feature.
Some of the applications of JK flip – flop include
• Shift Registers
• Frequency Dividers
• Switching Applications
• Parallel Data Transfer
• Serial Data Transfer
• Binary Counter
• Sequence Detector

Designing of T Flip Flop

T flip – flop is also known as “Toggle Flip – flop”. To avoid the occurrence of intermediate
state in SR flip – flop, we should provide only one input to the flip – flop called Trigger input
or Toggle input (T). Then the flip – flop acts as a Toggle switch. Toggling means ‘Changing
the next state output to complement of the present state output’.

We can design the T flip – flop by making simple modifications to the JK flip – flop. The T
flip – flop is a single input device and hence by connecting J and K inputs together and giving
them with single input called T we can convert a JK flip – flop into T flip – flop. So a T flip –
flop is sometimes called as single input JK flip – flop.
The logic symbol of T flip – flop is shown below. It has one Toggle input (T) & one clock
signal input (CLK).

T Flip – flop Circuit

We can construct a T flip – flop by any of the following methods.

Connecting the output feedback to the input, in SR flip – flop.

Connecting the XOR of T input and Q PREVIOUS output to the Data input, in D flip – flop.
Hard – wiring the J and K inputs together and connecting it to T input, in JK flip – flop.

Construction
T flip – flop can be constructed by modifying D flip – flop. In D flip – flop, the output
QPREV is XORed with the T input and given at the D input. The circuit of a T flip – flop
constructed from a D flip – flop is shown below.

The simplest of the constructions of a D flip – flop is with JK flip – flop. The J input and K
input of the JK flip – flop are connected together and provided with the T input. The logic
circuit of a T flip – flop constructed from a JK flip – flop is shown below.
Working
T flip – flop is an edge triggered device i.e. the low to high or high to low transitions on a
clock signal of narrow triggers that is provided as input will cause the change in output state
of flip – flop.

Truth Table of T flip – flop

The truth table of a T flip – flop is shown below.

As mentioned earlier, T flip – flop is an edge triggered device. For example, consider a T flip
– flop made of NAND SR latch as shown below.
If the output Q = 0, then the upper NAND is in enable state and lower NAND gate is in
disable condition. This allows the trigger to pass the S inputs to make the flip – flop in SET
state i.e. Q = 1.

If the output Q = 1, then the upper NAND is in disable state and lower NAND gate is in
enable condition. This allows the trigger to pass the R inputs to make the flip – flop in
RESET state i.e. Q =0.

In simple terms, the operation of the T flip – flop is

When the T input is low, then the next sate of the T flip flop is same as the present state.

 T = 0 and present state = 0 then the next state = 0

 T = 1 and present state = 1 then the next state = 1

When the T input is high and during the positive transition of the clock signal, the next state
of the T flip – flop is the inverse of present state.

 T = 1 and present state = 0 then the next state = 1

 T = 1 and present state = 1 then the next state = 0

As each incoming trigger alternately changes the set and reset inputs, the flip – flop toggles.
So to complete one full cycle of output wave form it need two triggers. This means that the T
flip flop produces the output at exactly half of the frequency of input frequency. So a T flip –
flops will act as “Frequency Divider Circuit”.

The main disadvantage of T flip – flop is that the state of the flip – flop at an applied trigger
pulse is known only when the previous state is known.
Generally, T flip flops are not available as ICs. So they can be constructed by using JK flip –
flop and SR flip – flop and D flip – flop. The symbol of T flip – flop made from JK flip – flop
is shown below.

Applications

 Frequency Division Circuits.

 2 – Bit Parallel Load Registers.

Introduction to Counters

Like shift registers and other combinational circuits, there is another important element in
digital electronics which we use most. They are counters. Counters are used not only for
counting but also for measuring frequency and time ; increment memory addresses .

Counting means incrementing or decrementing the values of an operator, with respect to its
previous state value. So to perform the mathematical operation we use no devices other than
counters. We cannot perform this action (counting) with any other logic devices rather than
counters.

Types of counters
There are two types of counters available for digital circuits, they are

1. Synchronous counters
2. Asynchronous counters

Different types of counters are explained below.

Synchronous counters

The counters which use clock signal to change their transition are called “Synchronous
counters”. This means the synchronous counters depends on their clock input to change state
values. All flip flops in the synchronous counters are triggered by same clock signal.

Features:

 Their construction is very simple in design. All the flip flops are interconnected and will
be driven by same clock signal.
  The state output of the previous flip flop determines the state change of the present flip
flop.
 As all the flip flops will work synchronously, the synchronous counters don’t require
settling.
 We require number of logic gates to implement the synchronous counters.
 Their operation is fast.

Asynchronous counters

Definition: The counters in which the change in transition doesn’t depend upon the clock
signal input is known as “Asynchronous counters”. In these counters, the first flip flop is
connected to the external clock signal, and the rest are clocked by the state outputs (Q & Q’)
of the previous flip flop.

Features:

 Another name for Asynchronous counters is “Ripple counters”.

 These are very simple in design.
 As its design is simple, they use less number of logic gates to construct an asynchronous
counter.
 Operation of asynchronous counters is very slow compared to synchronous counters.

Asynchronous Vs Synchronous Counters

Let’s compare the operation and features of synchronous and asynchronous counters. Their
differences are listed below.

SYNCHRONOUS COUNTERS ASYNCHRONOUS COUNTERS

The propagation delay is very low. Propagation delay is higher than that of

synchronous counters.

Its operational frequency is very The maximum frequency of operation is very

high. low.

These are faster than that of ripple These are slow in operation.

counters.
SYNCHRONOUS COUNTERS ASYNCHRONOUS COUNTERS

Large number of logic gates are Less number of logic gates required.

required to design

High cost. Low cost.

Synchronous circuits are easy to Complex to design.

design.

Standard logic packages available for For asynchronous counters, Standard logic

synchronous. packages are not available.

Practical example of counter

We use counters in many applications. Where ever we come across the use of timers, there
we use counters of synchronous type.

 For suppose, in our kitchen appliances, we use microwave ovens. In that we set some
temperature to heat the food item kept in it. Internally the counter calculates the increase
or decrease in temperature and time. If it reaches the pre-set temperature, then it
prevents from further heating and spoiling of that food item.
 Washing machines: We use counters in washing machines also. Similar to the counting
operation in microwave oven, the counter in washing machine counts the time which we
set it to operate.
 In both microwave oven and washing machine, we set the device to particular time, and
it starts decreasing for every second. When the value of counter becomes zero, it
activates the switch ON / OFF. Thus the operation of the device is controlled by
counters.

Some other applications of counters: To calculate the number of people entering and leaving
a stadium or auditorium we use , counters at entry gate or door. These counters will count the
persons. For entry of each person, the value of counter increases by 1. In the same manner,
for every leaving of each person, the counter value decreases by 1.

Applications of counters
Counter found their applications in many digital electronic devices. Some of their
applications are listed below.
  Frequency counters
 Digital clocks
 Analog to digital convertors.
 With some changes in their design, counters can be used as frequency divider circuits.
The frequency divider circuit is that which divides the input frequency exactly by ‘2’.
 In time measurement. That means calculating time in timers such as electronic devices
like ovens and washing machines.
 We can design digital triangular wave generator by using counters.

3 bit synchronous up counter using T Flip flop

Step 1: To design a synchronous up counter, first we need to know what number of flip flops
are required. we can find out by considering number of bits mentioned in question. So, in this
we required to make 3 bit counter so the number of flip flops required are 3 [2 n where n is
number of bits].

Step 2: After that, we need to construct state table with excitation table.
Note: To construct excitation table from state table you should know the excitation table of
respective flip flip in this case it is T flip flop. So check the excitation table for T flip flop
Which is:

T Flip Flop Excitation Table

Present state Next State T

0 0 0

0 1 1

1 0 1

1 1 0

So, the above table is excitation table for T Flip Flop.

State Table with excitation table

Present State Next State Flip Flop

Q3 Q2 Q1 Q'3 Q'2 Q'1 T3 T2 T1

0 0 0 0 0 1 0 0 1

0 0 1 0 1 0 0 1 1

0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1

1 0 0 1 0 1 0 0 1

1 0 1 1 1 0 0 1 1

1 1 0 1 1 1 0 0 1

1 1 1 0 0 0 1 1 1

Above table is created as per follow :

When Q3 =0 which is present state and Q3'=0 which is next state then T3 become 0 [As per
excitation table, have a look ]
Similarly, if Q3 is 0 and Q3' is 1 then T3 become 1.
In similar way it goes on .

Step 3: After making the excitation table the next thing to do is dig out the equation from the
boolean algebra or K map for the design of the counter. So, for T1 , T2 and T3 we got
1, Q1 and Q1.Q2

K-Map

For T3 Flip flop,

T3= Q1.Q2

For T2 Flip flop,

T2= Q1

For T1 Flip flop,

T1=1

Step 4: Lastly according to the equation got from K map create the design for 3 bit
synchronous up counter.

In above design T1 is getting input 1 and T2 is getting input from output of the T1 flip flop and
lastly, T3 is getting input from the output of T1 and T2 . A clock is attached to it which is in
blue color.