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Input Filter Design Example PDF

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479 views5 pages

Input Filter Design Example PDF

Uploaded by

LeonardoMartin
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EMI Filter Design Example

This is a very small 1 hour session


based on our 2 Day EMI Filter Design
Workshop
© Biricha Digital Power Ltd
Parkway Dr Dr Ali Shirsavar
Reading
RG4 6XG – UK Biricha Digital Power Ltd
April - 2018
1
DC/DC Single Stage CM & DM EMI Filter Design Cheat Sheet
L_source ½ L1
𝐶𝑑 𝑉𝑖𝑛2 𝜂
𝐶1 ≅ 𝑍𝑖𝑛 ≈
Cd
• PSU Specification 5 𝑃𝑜𝑢𝑡
L_CM1
Cpi C1
‒ Input voltage  Vin = 12V 1
Rd
𝑓𝑐/𝑜 =
‒ Output power  Pout = 6.75W 2 𝜋 𝐿𝐶
‒ Efficiency   =85%
𝐿∗ 2 x ½ C_CM1
‒ PSU closed loop input impedance  Zin = 18 𝑍𝑜 = ½ L1
𝐶

‒ Desired single stage filter output impedance  Zo = Zin/10 < 2 Where L = L1 , C = C1, R = Rd Chassis
1 𝐿
‒ Input current  Iin = Vin/Zin = 660mA 𝑄≅𝑅 𝐶
𝐷𝑒𝑠𝑖𝑟𝑒𝑑 𝐴𝑚𝑝𝑙𝑖𝑡𝑢𝑑𝑒 𝑎𝑓𝑡𝑒𝑟 𝑓𝑖𝑙𝑡𝑒𝑟𝑖𝑛𝑔 𝑓𝑐/𝑜
‒ Switching frequency  Fs = 200kHz 𝐺𝑎𝑖𝑛2𝑛𝑑_𝑜𝑟𝑑𝑒𝑟@𝑓 = =
𝐴𝑚𝑝𝑙𝑖𝑡𝑢𝑑𝑒 𝑏𝑒𝑓𝑜𝑟𝑒 𝑓𝑖𝑙𝑡𝑒𝑟𝑖𝑛𝑔 𝑓
‒ Lowest frequency of interest  Fh = 200kHz
‒ Harmonic number of Fh  n = 1 𝐼𝑟𝑟_𝑛𝑡ℎ_𝐻𝑎𝑟𝑚𝑜𝑛𝑖𝑐_𝑅𝑀𝑆 =
0.45 𝑃𝑜𝑢𝑡
𝑠𝑖𝑛 𝑛 × 180𝑜 × 𝐷
𝑛 𝑉𝑖𝑛 ×𝑒𝑓𝑓𝑖𝑐𝑖𝑒𝑛𝑦×𝐷
‒ PSU Loop cross over frequency  Fx = 2kHz
‒ Reflected Ripple Current** @ Fh (no filtering, simulated)  Irr_RMS = 760mA 1 𝐹𝑝𝑖 ≅ 1 2𝜋 𝐿_𝑠𝑜𝑢𝑟𝑐𝑒||𝐿1 × 𝐶𝑝𝑖
𝐹_𝐸𝑆𝑅0 =
‒ Estimated Duty /  = 42% 2𝜋 𝐶1 𝐸𝑆𝑅𝐶1
‒ Reflected Ripple Current @ Fh (no filtering, calculated)  Irr_RMS=
Cpi Rules:
‒ Source Inductance  L_source = 100uH (standard LISN) 1
2
• Filter Specification
3
‒ Desired Irr after filtering  Irr_filtered_RMS = 100dBuV (i.e. 2mA)
‒ Gain of single stage filter @ Fh  Gain_2ndorder = 0.05
𝑉𝑜𝑙𝑡𝑎𝑔𝑒 𝑖𝑛 𝑑𝐵𝜇𝑉 1𝜇𝑉
‒ single stage filter cut-off of frequency  Fc/o = 10.3kHz 𝑑𝐵𝜇𝑉 𝑡𝑜 𝐴𝑚𝑝𝑠 = 10 20 =
50Ω
‒ Desired cut-off frequency of common mode filter  Fc/o_CM = 75kHz
1
Fc/o_CM =
2𝜋 𝐿𝐶𝑀1 𝐶𝐶𝑀1
Note 1: We have 2 CM caps
* L = L_source + L1  for worse case Zo calculations only Note 2: Typically 1 decade below where CM noise starts
** Reflected ripple current with no filtering is the same as Input Terminal Ripple Current © Biricha Digital Power 2018
DC/DC Single Stage CM & DM EMI Filter Design Example

• Single Cell/Stage LC EMI Specification


‒ Min Capacitance  C1_min = 8uF C1_max
‒ Max Capacitance  C1_max = 20uF C1_min

‒ Min Inductance  L1_min = 10uH


‒ Max Inductance  L1_max = 30uH

‒ Selected C1 & Part No = 1 x 10uF + (3 x 4.7uF on-board)


‒ Total C1 after DC Bias Loss = 7.1uF + 12.3uF = ~20uF
‒ Combined ESR of C1 @ Fs = ~1m
‒ Frequency of ESR Zero due to C1  F_ESR0 = 8MHz

‒ Selected L1 & Part No = ~10uH


‒ Actual Fc/o = 10kHz
‒ Actual Zo (not including L_source) = 0.7
‒ Actual Zo (including L_source) = 2.3

‒ Calculated Damping Cap  Cd =


‒ Calculated Damping Resistor  Rd =
‒ Actual Damping Cap  Cd = 100uF L1_max
L1_min
‒ Actual Damping R  Rd = 0.42
‒ Q (not including L_source) = 1.7
‒ Q (including L_source) = 5.6
EMI Filter Design Workshop
Day 1: Introduction to EMI Filter Design
• Filter design from ground up including LC & Pi filters with and without damping
• Power supply stability, Middlebrook’s stability criteria and input filter interaction
• Becoming comfortable with using spectrum analysers, LISNs and network
analysers
• Using Biricha’s DC-DC EMI filter design software to speed up the design process Aschheim (Near Munich)
• Hands-on Labs, including: June 19th to 20th 2018
• LISN and Spectrum Analyser set-up for pre-compliance and EMC testing
• Filter measurement with Bode100 network analyser
• Step-by-step input and out filter design, implementation and testing
Day 2: AC/DC Line Filter Design
• Single Phase CCM Boost PFC topology operation & filtering needs
• Correct component selection, common mode chokes, differential mode choke, For full details, syllabus and
capacitors registration, please visit
• Designing high order/2-stage EMI filters
• AC-DC Line filter design & Biricha’s step-by-step Line filter design guide
• Hands-on Labs, including: www.biricha.com/emc
• AC/DC Line filter design and measurement for PFCs
• High order, 2 stage filter design and measurement
• Correct filter component selection and routing
4
DC/DC Single Stage CM & DM EMI Filter Design Example

• Cpi Design Calculations


‒ Rule 1: Cpi < C1/5
‒ Max Cpi due to C1 = 20uF/ 5 = 4uF

‒ Rule 2: Fpi should be ± 1 octave away from Fs


‒ Actual L1 = 10uH
‒ Source Impedance L_source = 100uH
‒ Fs to avoid resonance = 200kHz
‒ So Cpi should be bigger than = 280nF
‒ Or Cpi should be smaller than = 17nF

‒ Rule 3: Z_Cpi @ Fs < 5


‒ Cpi >= 160nF

‒ Min Cpi Capacitance= 280nF


‒ Max Cpi Capacitance= 4uF

‒ Actual Cpi Selected = 1uF


‒ Fpi = 52.8kHz

• CM Choke Calculations
‒ Calculated CM Choke Inductance L_CM1 = 0.5mH
‒ Selected L_CM1 & Part Number =
‒ Calculated CM filter capacitance 2 x ½ C_CM1 = 9nF
‒ Selected ½ C_CM1 & Part No= 2 x 4.7nF

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