UNIT-1

1.Distinguish between channeled gate array and channel less gate array
basic ASIC
2. What are the functional blocks in fpFPGA building blocks:
• Programmable logic blocks Implement combinatorial and sequential
logic
• Programmable interconnect Wires to connect inputs and outputs to
logic blocks
• Programmable I/O blocks Special logic blocks at the periphery of device
for external connections

3. What are the features of full custom ASIC.

Full-custom design potentially maximizes the performance of the chip, and

minimizes its area, but is extremely labor-intensive to implement. Full-
custom design is limited to ICs that are to be fabricated in extremely high
volumes, notably certain microprocessors and a small number of ASICs.

4. Differentiate PAL and PLA.

PAL: programmable AND array and fixed OR array

PLA: programmable AND and OR arrays

pLA stands for programmable logic Array which means there are set of
programmable And gate Array horizontally stacked and set of programmable
OR gate arrays Vertically stacked.You can implement combinational logic
function in SOP expression using these arrays.
5. State difference types of ASICs.

Types of ASICs • The classification of ASIC

6. What is an antifuse. List the types of antifuse

An antifuse is an electrical device that performs the opposite function to

a fuse. Whereas a fuse starts with a low resistance and is designed to
permanently break an electrically conductive path (typically when
the current through the path exceeds a specified limit), an antifuse starts
with a high resistance and is designed to permanently create an electrically
conductive path (typically when the voltage across the antifuse exceeds a
certain level). This technology has many applications.

Dielectric antifuses
Amorphous silicon antifuses
Zener antifuses
7. Give some of the important CAD tools.

Current systems are very complex.

• Design abstraction and decomposition is done to manage complexity.

• Tools automate the process of converting your design from one abstraction
level to another.

• Design Automation Tools improve productivity. • Different tools are

required in different steps.

Editors – Allows specification of the design either textually or graphically. •

Simulators – Models the response of a system to input stimuli. •

Analyzers – Used at different levels to check for correctness and compliance

to rules. •

Synthesis – Transformation of representation between different abstraction

levels

8. compare Antifuse, SRAM, EPROM and EEPROM with respect to erasing

mechanism.

9.What is meant by CBIC.

ASICs , for which all of the logic cells are predesigned and some (possibly all)
of the mask layers are customized are called semi custom ASICs. ... One can
apply the term CBICto any IC that uses cells, but it is generally accepted that
a cell-based ASIC or CBIC means a standard- cell basedASIC.

10. differentiate between standard cell based asic and custom ASIc
11.differentiate between standard cell based asic and custom ASIc

Net: Set
of two
or more
pins
that
have
the
same
electric

potential •

Netlist: Set of all nets. • Congestion: Where the shortest routes of several
nets are incompatible because they traverse the same tracks.

• Fixed-die routing: Chip outline and routing resources are fixed. •

Variable-die routing: New routing tracks can be added as needed

UNIT-II

1.What are the objectives of partitioning?

1. The functionality of a system is implemented with a set of

interconnected system components, such as ASIC’s, memories, CPU’s,
buses.
2. The designer must solve two problems:  select a set of system
components (allocation),
3. partition the system’s functionality among these components
(partitioning).  The final implementation has to satisfy a set of design
constraints, such as cost, performance and power consumption.

2. Differentiate between global and detailed routing.

Global routing is the routing with estimated values(delay values based
on the fanout of the wire)..this estimated values can be taken
according to statics by observing previous manufactured chips....

detailed routing is the routing with actual delays of the wires....this

actual delays can be obtained by several optimizations..(Timing
optimizations,CTS with good effort(if our design has multiple clocks))

Global Routing
 Define the routing regions.
 Generate a tentative route for each net.
 Each net is assigned to a set of routing regions.
 Does not specify the actual layout of wires.

Detailed Routing
 For each routing region, each net passing through that
region is assigned particular routing tracks.
 Actual layout of wires gets fixed.
 Associated sub problems: channel routing and switchbox routing.

3. What are the objectives of placement?

Measurement of Placement Goals and Objectives Key terms and
concepts: trees on graphs (or just trees) • Steiner trees • rectilinear
routing • Manhattan routing • Euclidean distance • Manhattan distance
• minimum rectilinear Steiner tree (MRST) • complete graph •
complete-graph measure • bounding box • half-perimeter measure (or
bounding-box measure) • meander factor • interconnect congestion •
maximum cut line • cut size • timing-driven placement • metal usage

4. Floorplanning Goals and Objectives

Key terms and concepts: Floorplanning is a mapping between the
logical description (the netlist) and the physical description (the
floorplan).
Goals of floorplanning:
• arrange the blocks on a chip,
• decide the location of the I/O pads,
• decide the location and number of the power pads,
• decide the type of power distribution, and • decide the location and
type of clock distribution. Objectives of floorplanning are:
• to minimize the chip area, and • minimize delay

5. List the advantages of global routing.

Global routing seeks to − determine whether a given placement is
routable,
 and − determine a coarse routing for all nets within available routing
regions • Considers goals such as − minimizing total wirelength,
and − reducing signal delays on critical nets

6.State the governing equation for RC interconnect delay model.in asic

7.What is meant by net cutest and edge cutest.

UNIT-III
1. What are the different methods of Logic Minimization?

2. Expand edif and illustrate the hierarchical nature of an edif file.

for exchanging information between EDA tools is the electronic design
interchange format ( EDIF ). We will describe EDIF version 2 0 0. The
most important features added in EDIF 3 0 0 were to handle buses, bus
rippers, and buses across schematic pages. EDIF 4 0 0 includes new
extensions for PCB and multichip module (MCM) data. The Library of
Parameterized Modules ( LPM ) standard is also based on EDIF. The
newer versions of EDIF have a richer feature set, but the ASIC industry
seems to have standardized on EDIF 2 0 0. Most EDA companies now
support EDIF. The FPGA companies Altera and Actel use EDIF as their
 netlist format, and Xilinx has announced its intention to switch from its
own XNF format to EDIF. We only have room for a brief description of
the EDIF format here. A complete description of the EDIF standard is
contained in the Electronic Industries Association ( EIA ) publication,
Electronic Design Interchange Format Version 2 0 0 (ANSI/EIA Standard
548-1988) [ EDIF, 1988].

4. EDIF Syntax

3. The structure of EDIF is similar to the Lisp programming language or

the Postscript printer language. This makes EDIF a very hard language
to read and almost impossible to write by hand. EDIF is intended as an
exchange format between tools, not as a design-entry language. Since
EDIF is so flexible each company reads and writes different “flavors” of
EDIF. Inevitably EDIF from one company does not quite work when we
try and use it with a tool from another company, though this situation
is improving with the gradual adoption of EDIF 3 0 0. We need to know
just enough about EDIF to be able to fix these problems.

FIGURE 9.8  The hierarchical nature of an

EDIF file.

  
5.What is ATPG and why?

ATPG (acronym for both Automatic Test Pattern Generation

and Automatic Test Pattern Generator) is an electronic design
automation method/technology used to find an input (or test) sequence that,
when applied to a digital circuit, enables automatic test equipment to
distinguish between the correct circuit behavior and the faulty circuit
behavior caused by defects.

The generated patterns are used to test semiconductor devices after

manufacture, or to assist with determining the cause of failure (failure
analysis[1]). The effectiveness of ATPG is measured by the number of
modeled defects, or fault models, detectable and by the number of
generated patterns. These metrics generally indicate test
quality (higher with more fault detections) and test application time
(higher with more patterns). ATPG efficiency is another important
consideration that is influenced by the fault model under consideration,
the type of circuit under test (full scan, synchronous sequential, or
asynchronous sequential), the level of abstraction used to represent
the circuit under test (gate, register-transfer, switch), and the
required test quality.

6. What is podem algorithm

PODEM (Path-Oriented Decision Making) is an Automatic Test
Pattern Generation (ATPG) algorithm which was created to
overcome the inability of D-Algorithm (D-ALG) to generate test
vectors for circuits involving Error Correction and Translation.
7. What is standard format for interchanging information BETWEEN
DIFFERENT EDA TOOLS?
The data can be used to reconstruct all or part of the artwork to be
used in sharing layouts, transferring artwork between different EDA
tools, or creating photo masks for fabrication.
8. What is the function of PIP in the interconnect architecture of Xilinx?

Programmable Interconnect Points (PIP)

Programmable interconnect points, or PIPs, provide the routing paths

used to connect the inputs and outputs of IOBs and CLBs into logic
networks.

A PIP is a CMOS transistor switch that you can program to turn on or

off.

9. LIST THE LOW LEVEL DESIGN LANGUAGES.

ABEL is a PLD programming language from Data I/O.

• CUPL is a PLD design language from Logical Devices.
• PALASM is a PLD design language from AMD/MMI
10. Mention the types of simulation used to provide the details of
hardware at gate level.

11. Give the syntax for data types in VHDL.

 Syntax:

[not] <identifier> [
[and | or | nor | nand | xor | xnor | ... ]
[<identifier>]
];

Examples:

 not signal_1;
 signal_1 and signal_2;
 (not signal_1) and (signal_2 xor (signal_3 or (not
signal_4))
xor signal_5);
12. What is features of ATPG?

his section describes test features that are included in the RTL to ensure that
the DFT implementation meets minimum requirements:

 Wrapper
 Enabling sections of the core
 Reset handling.
 Safe shift RAM signals.

UNIT-4

1. Draw the basic logic cell of Actel 1 FPGA.

 The ACT1 basic logic cell used in the multiplexer-based field-

programmable logic family from ACTEL semiconductor
(www.actel.com).

 Each input of the cell can be connected to I/O pins or outputs from the
same or other cells via the interconnection network. Click the input
 switches or type the '1' .. '8' bindkeys to control the eight inputs to the
logic cell.

 See the next few applets for example logic functions realized with this
multiplexer based cell. The design software for these FPGAs uses
special logic-synthesis algorithms which can efficiently map arbitrary
circuits onto the multiplexer based cells.

 Warning: the multiplexers used in the ACTEL datasheets (and most

books showing the ACTEL architecture) use the opposite data-input
ordering (A0/A1) as the Hades 2:1 multiplexer
(hades.models.gates.Mux21). This makes no functional difference, but
means that the layout of the circuits shown in the following applets are
permutations of the circuits shown in the databooks.

2.Indicate the design flow technology using FPGA.

 3.implement carry output of half adder using actel 1 fpga

4. what are the advantages and disadvantages of FPGA compared to

ASIC.
FPGA sythesis is much more easier than ASIC. • In FPGA you need
not do floor-planning, tool can do it efficiently. In ASIC you have do
it

5. ASIC Design Disadvantages •

Time-to-market: Some large ASICs can take a year or more to
design. A good way to shorten development time is to make
prototypes using FPGAs and then switch to an ASIC.
• Design Issues: In ASIC you should take care of DFM issues, Signal
Integrity isuues and many more. In FPGA you don't have all these
because ASIC designer takes care of all these.
( Don't forget FPGA isan IC and designed by ASIC design
enginner !!) • Expensive Tools: ASIC design tools are very much
expensive. You spend a hug

6. What is fine grain and coarse grain.

A coarse-grained description of a system regards large

subcomponents.

A fine-grained description regards smaller components of which the

larger ones are composed.
 UNIT-V

1. What are the factors considered in the SOC design.

• System performance • System reliability and flexibility •
System cost • Power consumption • Development tools • Future
roadmap

2. Soc features.
Canonical definition – 100,000+ gates? –
Programmable core? – Memory?
– Plenty of virtual components?
– Moderate volume product? –
Short time-to-market? –
Consumer electronics product?

3. How is soc configured

Customer requirements • System specification • Architecture design
• Hardware vs. software • Component design • Integration •
Verification • Manufacture • Test

This section describes the SoC configuration and contains the following
subsections:

 Configuring the chip

 Entering test mode
 Controlling debug
 Configuring security.
4.. SoCs can be fabricated by several technologies, including:

 Full custom application-specific integrated circuit (ASIC)

 Standard cell ASIC
 Field-programmable gate array (FPGA)
 A system on a chip or system on chip (SoC or SOC) is an integrated
circuit (also known as an "IC" or "chip") that integrates all components
of a computer or other electronic systems. These components typically
include a central processing unit (CPU), memory, input/output ports
and secondary storage – all on a single substrate. It may
contain digital, analog, mixed-signal, and often radio-
frequencyfunctions, depending on the application. SoCs are very
 common in the mobile computing market because of their low power
consumption.[1]SoCs are commonly applied in the area of embedded
systems.

5. What are the applications of soc.

VERILOG AND LOGIC

SYNTHESIS
VERILOG AND LOGIC
SYNTHESIS
• module MyChip_ASIC()
// behavioral "always", etc. ...
SecondLevelStub1 port mapping
SecondLevelStub2 port mapping
endmoduleInput1; endmodule
module SecondLevelStub2() ... assign
Output2 = ~Input2;
of thStub1() ... assign Output1 =
~endmodule
module SecondLevelcomponent pieces
Eventually the Verilog modules will
correspond to the
various e ASIC.
VHDL and Logic Synthesis
• Most logic synthesizers insist we follow a set of rules
when we use a
logic system to ensure that what we synthesize matches
the behavioral
description. Here is a typical set of rules for use with
the IEEE VHDL
nine-value system:
• logic values corresponding to states '1' , 'H' , '0' , and
'L' in any manner
Can be used.
• Some synthesis tools do not accept the uninitialized
logic state 'U' .
• You can use logic states 'Z' , 'X' , 'W' , and '-' in signal
and variable
assignments in any manner. 'Z' is synthesized to three-
state logic.
• The states 'X' , 'W' , and '-' are treated as unknown or
don’t care values.
• The values 'Z' , 'X' , 'W' , and '-' may be used in
conditional clauses such
as the comparison in an if or case statement. However,
some synthesis
tools will ignore them and only match surrounding '1'
and '0' bits.
Consequently, a synthesized design may behave
differently from the
simulation if a stimulus uses 'Z' , 'X' , 'W' or '-' . The
IEEE synthesis
packages provide the STD_MATCH function for
comparisons.
EDIF
• The structure of EDIF is similar to the Lisp
programming
language or the Postscript printer language. This
makes EDIF
a very hard language to read and almost
impossible to write by
hand.
• EDIF is intended as an exchange format
between tools, not as
a design-entry language. Since EDIF is so
flexible each
company reads and writes different “flavors” of
EDIF.
EDIF
• Within an EDIF file are one or more libraries
of cell
descriptions. Each library contains technology
information that
is used in describing the characteristics of the
cells it contains.
Each cell description contains one or more user-
named views
of the cell.
• Each view is defined as a particular view Type
and contains
an interface description that identifies where the
cell may be
connected to and, possibly, a contents
description that
identifies the components and related
interconnections that
make up the cell.
• The semantics of EDIF are defined by the
EDIF keywords .
Keywords are the only types of name that can
immediately
follow a left parenthesis.
EDIF
• The EDIF syntax consists of a series of
statements in the
following format:
(keywordName {form})
• A left parenthesis (round bracket) is always
followed by
a keyword name , followed by one or more
EDIF forms (a
form is a sequence of identifiers, primitive data,
symbolic
constants, or EDIF statements), ending with a
right
parenthesis..
CFI Design Representation
• The CAD Framework Initiative ( CFI ) is an
independent nonprofit
organization working on the creation of standards
for the electronic
CAD industry. One of the areas in which CFI is
working is the
definition of standards for design representation
( DR ). The CFI 1.0
standard [ CFI, 1992] has tackled the problems of
ambiguity in the
area of definitions and terms for schematics by
defining
an information model ( IM ) for electrical
connectivity information.
• It helps to solidify the concepts of the terms and
definitions such as
cell, net, and instance that we have already
discussed. However,
there are additional new concepts and terms to
define in order to
present the standard model, so this is not a good way
to introduce
schematic terminology.
• The ASIC design engineer is becoming more of a
programmer and
less of a circuit designer. This trend shows no sign
of stopping as
ASICs grow larger and systems more complex. A
precise
understanding of how tools operate and interact is
becoming
increasingly important

CFI CONNECTIVITY
MODEL